1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * MPC832x RDB Device Tree Source
4 *
5 * Copyright 2007 Freescale Semiconductor Inc.
6 */
7
8 /dts-v1/;
9
10 / {
11 model = "MPC8323ERDB";
12 compatible = "MPC8323ERDB", "MPC832xRD
13 #address-cells = <1>;
14 #size-cells = <1>;
15
16 aliases {
17 ethernet0 = &enet1;
18 ethernet1 = &enet0;
19 serial0 = &serial0;
20 serial1 = &serial1;
21 pci0 = &pci0;
22 };
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 PowerPC,8323@0 {
29 device_type = "cpu";
30 reg = <0x0>;
31 d-cache-line-size = <0
32 i-cache-line-size = <0
33 d-cache-size = <16384>
34 i-cache-size = <16384>
35 timebase-frequency = <
36 bus-frequency = <0>;
37 clock-frequency = <0>;
38 };
39 };
40
41 memory {
42 device_type = "memory";
43 reg = <0x00000000 0x04000000>;
44 };
45
46 soc8323@e0000000 {
47 #address-cells = <1>;
48 #size-cells = <1>;
49 device_type = "soc";
50 compatible = "simple-bus";
51 ranges = <0x0 0xe0000000 0x001
52 reg = <0xe0000000 0x00000200>;
53 bus-frequency = <0>;
54
55 wdt@200 {
56 device_type = "watchdo
57 compatible = "mpc83xx_
58 reg = <0x200 0x100>;
59 };
60
61 pmc: power@b00 {
62 compatible = "fsl,mpc8
63 reg = <0xb00 0x100 0xa
64 interrupts = <80 0x8>;
65 interrupt-parent = <&i
66 };
67
68 i2c@3000 {
69 #address-cells = <1>;
70 #size-cells = <0>;
71 cell-index = <0>;
72 compatible = "fsl-i2c"
73 reg = <0x3000 0x100>;
74 interrupts = <14 0x8>;
75 interrupt-parent = <&i
76 dfsrr;
77 };
78
79 serial0: serial@4500 {
80 cell-index = <0>;
81 device_type = "serial"
82 compatible = "fsl,ns16
83 reg = <0x4500 0x100>;
84 clock-frequency = <0>;
85 interrupts = <9 0x8>;
86 interrupt-parent = <&i
87 };
88
89 serial1: serial@4600 {
90 cell-index = <1>;
91 device_type = "serial"
92 compatible = "fsl,ns16
93 reg = <0x4600 0x100>;
94 clock-frequency = <0>;
95 interrupts = <10 0x8>;
96 interrupt-parent = <&i
97 };
98
99 dma@82a8 {
100 #address-cells = <1>;
101 #size-cells = <1>;
102 compatible = "fsl,mpc8
103 reg = <0x82a8 4>;
104 ranges = <0 0x8100 0x1
105 interrupt-parent = <&i
106 interrupts = <71 8>;
107 cell-index = <0>;
108 dma-channel@0 {
109 compatible = "
110 reg = <0 0x80>
111 cell-index = <
112 interrupt-pare
113 interrupts = <
114 };
115 dma-channel@80 {
116 compatible = "
117 reg = <0x80 0x
118 cell-index = <
119 interrupt-pare
120 interrupts = <
121 };
122 dma-channel@100 {
123 compatible = "
124 reg = <0x100 0
125 cell-index = <
126 interrupt-pare
127 interrupts = <
128 };
129 dma-channel@180 {
130 compatible = "
131 reg = <0x180 0
132 cell-index = <
133 interrupt-pare
134 interrupts = <
135 };
136 };
137
138 crypto@30000 {
139 compatible = "fsl,sec2
140 reg = <0x30000 0x10000
141 interrupts = <11 0x8>;
142 interrupt-parent = <&i
143 fsl,num-channels = <1>
144 fsl,channel-fifo-len =
145 fsl,exec-units-mask =
146 fsl,descriptor-types-m
147 sleep = <&pmc 0x030000
148 };
149
150 ipic:pic@700 {
151 interrupt-controller;
152 #address-cells = <0>;
153 #interrupt-cells = <2>
154 reg = <0x700 0x100>;
155 device_type = "ipic";
156 };
157
158 par_io@1400 {
159 #address-cells = <1>;
160 #size-cells = <1>;
161 reg = <0x1400 0x100>;
162 ranges = <3 0x1448 0x1
163 compatible = "fsl,mpc8
164 device_type = "par_io"
165 num-ports = <7>;
166
167 qe_pio_d: gpio-control
168 #gpio-cells =
169 compatible = "
170 reg = <3 0x18>
171 gpio-controlle
172 };
173
174 ucc2pio:ucc_pin@2 {
175 pio-map = <
176 /* port pin dir ope
177 3 4
178 3 5
179 3 21
180 3 23
181 0 18
182 0 19
183 0 20
184 0 21
185 0 22
186 0 23
187 0 24
188 0 25
189 0 26
190 0 27
191 0 28
192 0 29
193 0 30
194 0 31
195 };
196 ucc3pio:ucc_pin@3 {
197 pio-map = <
198 /* port pin dir ope
199 0 13
200 3 24
201 1 0
202 1 1
203 1 2
204 1 3
205 1 4
206 1 5
207 1 6
208 1 7
209 1 8
210 1 9
211 1 10
212 1 11
213 1 12
214 1 13
215 };
216 };
217 };
218
219 qe@e0100000 {
220 #address-cells = <1>;
221 #size-cells = <1>;
222 device_type = "qe";
223 compatible = "fsl,qe";
224 ranges = <0x0 0xe0100000 0x001
225 reg = <0xe0100000 0x480>;
226 brg-frequency = <0>;
227 bus-frequency = <198000000>;
228 fsl,qe-num-riscs = <1>;
229 fsl,qe-num-snums = <28>;
230
231 muram@10000 {
232 #address-cells = <1>;
233 #size-cells = <1>;
234 compatible = "fsl,qe-m
235 ranges = <0x0 0x000100
236
237 data-only@0 {
238 compatible = "
239 "
240 reg = <0x0 0x4
241 };
242 };
243
244 spi@4c0 {
245 #address-cells = <1>;
246 #size-cells = <0>;
247 cell-index = <0>;
248 compatible = "fsl,spi"
249 reg = <0x4c0 0x40>;
250 interrupts = <2>;
251 interrupt-parent = <&q
252 cs-gpios = <&qe_pio_d
253 mode = "cpu-qe";
254
255 mmc-slot@0 {
256 compatible = "
257 "
258 reg = <0>;
259 gpios = <&qe_p
260 &qe_p
261 voltage-ranges
262 spi-max-freque
263 };
264 };
265
266 spi@500 {
267 cell-index = <1>;
268 compatible = "fsl,spi"
269 reg = <0x500 0x40>;
270 interrupts = <1>;
271 interrupt-parent = <&q
272 mode = "cpu";
273 };
274
275 enet0: ucc@3000 {
276 device_type = "network
277 compatible = "ucc_geth
278 cell-index = <2>;
279 reg = <0x3000 0x200>;
280 interrupts = <33>;
281 interrupt-parent = <&q
282 local-mac-address = [
283 rx-clock-name = "clk16
284 tx-clock-name = "clk3"
285 phy-handle = <&phy00>;
286 pio-handle = <&ucc2pio
287 };
288
289 enet1: ucc@2200 {
290 device_type = "network
291 compatible = "ucc_geth
292 cell-index = <3>;
293 reg = <0x2200 0x200>;
294 interrupts = <34>;
295 interrupt-parent = <&q
296 local-mac-address = [
297 rx-clock-name = "clk9"
298 tx-clock-name = "clk10
299 phy-handle = <&phy04>;
300 pio-handle = <&ucc3pio
301 };
302
303 mdio@3120 {
304 #address-cells = <1>;
305 #size-cells = <0>;
306 reg = <0x3120 0x18>;
307 compatible = "fsl,ucc-
308
309 phy00:ethernet-phy@0 {
310 reg = <0x0>;
311 };
312 phy04:ethernet-phy@4 {
313 reg = <0x4>;
314 };
315 };
316
317 qeic:interrupt-controller@80 {
318 interrupt-controller;
319 compatible = "fsl,qe-i
320 #address-cells = <0>;
321 #interrupt-cells = <1>
322 reg = <0x80 0x80>;
323 big-endian;
324 interrupts = <32 0x8 3
325 interrupt-parent = <&i
326 };
327 };
328
329 pci0: pci@e0008500 {
330 interrupt-map-mask = <0xf800 0
331 interrupt-map = <
332 /* IDSEL 0x10
333 0x8000 0x0 0x
334
335 /* IDSEL 0x11
336 0x8800 0x0 0x
337 0x8800 0x0 0x
338 0x8800 0x0 0x
339 0x8800 0x0 0x
340
341 /* IDSEL 0x12
342 0x9000 0x0 0x
343 0x9000 0x0 0x
344 0x9000 0x0 0x
345 0x9000 0x0 0x
346
347 interrupt-parent = <&ipic>;
348 interrupts = <66 0x8>;
349 bus-range = <0x0 0x0>;
350 ranges = <0x42000000 0x0 0x800
351 0x02000000 0x0 0x900
352 0x01000000 0x0 0xd00
353 clock-frequency = <0>;
354 #interrupt-cells = <1>;
355 #size-cells = <2>;
356 #address-cells = <3>;
357 reg = <0xe0008500 0x100
358 0xe0008300 0x8>;
359 compatible = "fsl,mpc8349-pci"
360 device_type = "pci";
361 sleep = <&pmc 0x00010000>;
362 };
363 };
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