1 // SPDX-License-Identifier: GPL-2.0-or-later <<
2 /* 1 /*
3 * MPC832x RDB Device Tree Source 2 * MPC832x RDB Device Tree Source
4 * 3 *
5 * Copyright 2007 Freescale Semiconductor Inc. 4 * Copyright 2007 Freescale Semiconductor Inc.
>> 5 *
>> 6 * This program is free software; you can redistribute it and/or modify it
>> 7 * under the terms of the GNU General Public License as published by the
>> 8 * Free Software Foundation; either version 2 of the License, or (at your
>> 9 * option) any later version.
6 */ 10 */
7 11
8 /dts-v1/; 12 /dts-v1/;
9 13
10 / { 14 / {
11 model = "MPC8323ERDB"; 15 model = "MPC8323ERDB";
12 compatible = "MPC8323ERDB", "MPC832xRD 16 compatible = "MPC8323ERDB", "MPC832xRDB", "MPC83xxRDB";
13 #address-cells = <1>; 17 #address-cells = <1>;
14 #size-cells = <1>; 18 #size-cells = <1>;
15 19
16 aliases { 20 aliases {
17 ethernet0 = &enet1; 21 ethernet0 = &enet1;
18 ethernet1 = &enet0; 22 ethernet1 = &enet0;
19 serial0 = &serial0; 23 serial0 = &serial0;
20 serial1 = &serial1; 24 serial1 = &serial1;
21 pci0 = &pci0; 25 pci0 = &pci0;
22 }; 26 };
23 27
24 cpus { 28 cpus {
25 #address-cells = <1>; 29 #address-cells = <1>;
26 #size-cells = <0>; 30 #size-cells = <0>;
27 31
28 PowerPC,8323@0 { 32 PowerPC,8323@0 {
29 device_type = "cpu"; 33 device_type = "cpu";
30 reg = <0x0>; 34 reg = <0x0>;
31 d-cache-line-size = <0 35 d-cache-line-size = <0x20>; // 32 bytes
32 i-cache-line-size = <0 36 i-cache-line-size = <0x20>; // 32 bytes
33 d-cache-size = <16384> 37 d-cache-size = <16384>; // L1, 16K
34 i-cache-size = <16384> 38 i-cache-size = <16384>; // L1, 16K
35 timebase-frequency = < 39 timebase-frequency = <0>;
36 bus-frequency = <0>; 40 bus-frequency = <0>;
37 clock-frequency = <0>; 41 clock-frequency = <0>;
38 }; 42 };
39 }; 43 };
40 44
41 memory { 45 memory {
42 device_type = "memory"; 46 device_type = "memory";
43 reg = <0x00000000 0x04000000>; 47 reg = <0x00000000 0x04000000>;
44 }; 48 };
45 49
46 soc8323@e0000000 { 50 soc8323@e0000000 {
47 #address-cells = <1>; 51 #address-cells = <1>;
48 #size-cells = <1>; 52 #size-cells = <1>;
49 device_type = "soc"; 53 device_type = "soc";
50 compatible = "simple-bus"; 54 compatible = "simple-bus";
51 ranges = <0x0 0xe0000000 0x001 55 ranges = <0x0 0xe0000000 0x00100000>;
52 reg = <0xe0000000 0x00000200>; 56 reg = <0xe0000000 0x00000200>;
53 bus-frequency = <0>; 57 bus-frequency = <0>;
54 58
55 wdt@200 { 59 wdt@200 {
56 device_type = "watchdo 60 device_type = "watchdog";
57 compatible = "mpc83xx_ 61 compatible = "mpc83xx_wdt";
58 reg = <0x200 0x100>; 62 reg = <0x200 0x100>;
59 }; 63 };
60 64
61 pmc: power@b00 { 65 pmc: power@b00 {
62 compatible = "fsl,mpc8 66 compatible = "fsl,mpc8323-pmc", "fsl,mpc8349-pmc";
63 reg = <0xb00 0x100 0xa 67 reg = <0xb00 0x100 0xa00 0x100>;
64 interrupts = <80 0x8>; 68 interrupts = <80 0x8>;
65 interrupt-parent = <&i 69 interrupt-parent = <&ipic>;
66 }; 70 };
67 71
68 i2c@3000 { 72 i2c@3000 {
69 #address-cells = <1>; 73 #address-cells = <1>;
70 #size-cells = <0>; 74 #size-cells = <0>;
71 cell-index = <0>; 75 cell-index = <0>;
72 compatible = "fsl-i2c" 76 compatible = "fsl-i2c";
73 reg = <0x3000 0x100>; 77 reg = <0x3000 0x100>;
74 interrupts = <14 0x8>; 78 interrupts = <14 0x8>;
75 interrupt-parent = <&i 79 interrupt-parent = <&ipic>;
76 dfsrr; 80 dfsrr;
77 }; 81 };
78 82
79 serial0: serial@4500 { 83 serial0: serial@4500 {
80 cell-index = <0>; 84 cell-index = <0>;
81 device_type = "serial" 85 device_type = "serial";
82 compatible = "fsl,ns16 86 compatible = "fsl,ns16550", "ns16550";
83 reg = <0x4500 0x100>; 87 reg = <0x4500 0x100>;
84 clock-frequency = <0>; 88 clock-frequency = <0>;
85 interrupts = <9 0x8>; 89 interrupts = <9 0x8>;
86 interrupt-parent = <&i 90 interrupt-parent = <&ipic>;
87 }; 91 };
88 92
89 serial1: serial@4600 { 93 serial1: serial@4600 {
90 cell-index = <1>; 94 cell-index = <1>;
91 device_type = "serial" 95 device_type = "serial";
92 compatible = "fsl,ns16 96 compatible = "fsl,ns16550", "ns16550";
93 reg = <0x4600 0x100>; 97 reg = <0x4600 0x100>;
94 clock-frequency = <0>; 98 clock-frequency = <0>;
95 interrupts = <10 0x8>; 99 interrupts = <10 0x8>;
96 interrupt-parent = <&i 100 interrupt-parent = <&ipic>;
97 }; 101 };
98 102
99 dma@82a8 { 103 dma@82a8 {
100 #address-cells = <1>; 104 #address-cells = <1>;
101 #size-cells = <1>; 105 #size-cells = <1>;
102 compatible = "fsl,mpc8 106 compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
103 reg = <0x82a8 4>; 107 reg = <0x82a8 4>;
104 ranges = <0 0x8100 0x1 108 ranges = <0 0x8100 0x1a8>;
105 interrupt-parent = <&i 109 interrupt-parent = <&ipic>;
106 interrupts = <71 8>; 110 interrupts = <71 8>;
107 cell-index = <0>; 111 cell-index = <0>;
108 dma-channel@0 { 112 dma-channel@0 {
109 compatible = " 113 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
110 reg = <0 0x80> 114 reg = <0 0x80>;
111 cell-index = < 115 cell-index = <0>;
112 interrupt-pare 116 interrupt-parent = <&ipic>;
113 interrupts = < 117 interrupts = <71 8>;
114 }; 118 };
115 dma-channel@80 { 119 dma-channel@80 {
116 compatible = " 120 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
117 reg = <0x80 0x 121 reg = <0x80 0x80>;
118 cell-index = < 122 cell-index = <1>;
119 interrupt-pare 123 interrupt-parent = <&ipic>;
120 interrupts = < 124 interrupts = <71 8>;
121 }; 125 };
122 dma-channel@100 { 126 dma-channel@100 {
123 compatible = " 127 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
124 reg = <0x100 0 128 reg = <0x100 0x80>;
125 cell-index = < 129 cell-index = <2>;
126 interrupt-pare 130 interrupt-parent = <&ipic>;
127 interrupts = < 131 interrupts = <71 8>;
128 }; 132 };
129 dma-channel@180 { 133 dma-channel@180 {
130 compatible = " 134 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
131 reg = <0x180 0 135 reg = <0x180 0x28>;
132 cell-index = < 136 cell-index = <3>;
133 interrupt-pare 137 interrupt-parent = <&ipic>;
134 interrupts = < 138 interrupts = <71 8>;
135 }; 139 };
136 }; 140 };
137 141
138 crypto@30000 { 142 crypto@30000 {
139 compatible = "fsl,sec2 143 compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
140 reg = <0x30000 0x10000 144 reg = <0x30000 0x10000>;
141 interrupts = <11 0x8>; 145 interrupts = <11 0x8>;
142 interrupt-parent = <&i 146 interrupt-parent = <&ipic>;
143 fsl,num-channels = <1> 147 fsl,num-channels = <1>;
144 fsl,channel-fifo-len = 148 fsl,channel-fifo-len = <24>;
145 fsl,exec-units-mask = 149 fsl,exec-units-mask = <0x4c>;
146 fsl,descriptor-types-m 150 fsl,descriptor-types-mask = <0x0122003f>;
147 sleep = <&pmc 0x030000 151 sleep = <&pmc 0x03000000>;
148 }; 152 };
149 153
150 ipic:pic@700 { 154 ipic:pic@700 {
151 interrupt-controller; 155 interrupt-controller;
152 #address-cells = <0>; 156 #address-cells = <0>;
153 #interrupt-cells = <2> 157 #interrupt-cells = <2>;
154 reg = <0x700 0x100>; 158 reg = <0x700 0x100>;
155 device_type = "ipic"; 159 device_type = "ipic";
156 }; 160 };
157 161
158 par_io@1400 { 162 par_io@1400 {
159 #address-cells = <1>; 163 #address-cells = <1>;
160 #size-cells = <1>; 164 #size-cells = <1>;
161 reg = <0x1400 0x100>; 165 reg = <0x1400 0x100>;
162 ranges = <3 0x1448 0x1 166 ranges = <3 0x1448 0x18>;
163 compatible = "fsl,mpc8 167 compatible = "fsl,mpc8323-qe-pario";
164 device_type = "par_io" 168 device_type = "par_io";
165 num-ports = <7>; 169 num-ports = <7>;
166 170
167 qe_pio_d: gpio-control 171 qe_pio_d: gpio-controller@1448 {
168 #gpio-cells = 172 #gpio-cells = <2>;
169 compatible = " 173 compatible = "fsl,mpc8323-qe-pario-bank";
170 reg = <3 0x18> 174 reg = <3 0x18>;
171 gpio-controlle 175 gpio-controller;
172 }; 176 };
173 177
174 ucc2pio:ucc_pin@2 { 178 ucc2pio:ucc_pin@2 {
175 pio-map = < 179 pio-map = <
176 /* port pin dir ope 180 /* port pin dir open_drain assignment has_irq */
177 3 4 181 3 4 3 0 2 0 /* MDIO */
178 3 5 182 3 5 1 0 2 0 /* MDC */
179 3 21 183 3 21 2 0 1 0 /* RX_CLK (CLK16) */
180 3 23 184 3 23 2 0 1 0 /* TX_CLK (CLK3) */
181 0 18 185 0 18 1 0 1 0 /* TxD0 */
182 0 19 186 0 19 1 0 1 0 /* TxD1 */
183 0 20 187 0 20 1 0 1 0 /* TxD2 */
184 0 21 188 0 21 1 0 1 0 /* TxD3 */
185 0 22 189 0 22 2 0 1 0 /* RxD0 */
186 0 23 190 0 23 2 0 1 0 /* RxD1 */
187 0 24 191 0 24 2 0 1 0 /* RxD2 */
188 0 25 192 0 25 2 0 1 0 /* RxD3 */
189 0 26 193 0 26 2 0 1 0 /* RX_ER */
190 0 27 194 0 27 1 0 1 0 /* TX_ER */
191 0 28 195 0 28 2 0 1 0 /* RX_DV */
192 0 29 196 0 29 2 0 1 0 /* COL */
193 0 30 197 0 30 1 0 1 0 /* TX_EN */
194 0 31 198 0 31 2 0 1 0>; /* CRS */
195 }; 199 };
196 ucc3pio:ucc_pin@3 { 200 ucc3pio:ucc_pin@3 {
197 pio-map = < 201 pio-map = <
198 /* port pin dir ope 202 /* port pin dir open_drain assignment has_irq */
199 0 13 203 0 13 2 0 1 0 /* RX_CLK (CLK9) */
200 3 24 204 3 24 2 0 1 0 /* TX_CLK (CLK10) */
201 1 0 205 1 0 1 0 1 0 /* TxD0 */
202 1 1 206 1 1 1 0 1 0 /* TxD1 */
203 1 2 207 1 2 1 0 1 0 /* TxD2 */
204 1 3 208 1 3 1 0 1 0 /* TxD3 */
205 1 4 209 1 4 2 0 1 0 /* RxD0 */
206 1 5 210 1 5 2 0 1 0 /* RxD1 */
207 1 6 211 1 6 2 0 1 0 /* RxD2 */
208 1 7 212 1 7 2 0 1 0 /* RxD3 */
209 1 8 213 1 8 2 0 1 0 /* RX_ER */
210 1 9 214 1 9 1 0 1 0 /* TX_ER */
211 1 10 215 1 10 2 0 1 0 /* RX_DV */
212 1 11 216 1 11 2 0 1 0 /* COL */
213 1 12 217 1 12 1 0 1 0 /* TX_EN */
214 1 13 218 1 13 2 0 1 0>; /* CRS */
215 }; 219 };
216 }; 220 };
217 }; 221 };
218 222
219 qe@e0100000 { 223 qe@e0100000 {
220 #address-cells = <1>; 224 #address-cells = <1>;
221 #size-cells = <1>; 225 #size-cells = <1>;
222 device_type = "qe"; 226 device_type = "qe";
223 compatible = "fsl,qe"; 227 compatible = "fsl,qe";
224 ranges = <0x0 0xe0100000 0x001 228 ranges = <0x0 0xe0100000 0x00100000>;
225 reg = <0xe0100000 0x480>; 229 reg = <0xe0100000 0x480>;
226 brg-frequency = <0>; 230 brg-frequency = <0>;
227 bus-frequency = <198000000>; 231 bus-frequency = <198000000>;
228 fsl,qe-num-riscs = <1>; 232 fsl,qe-num-riscs = <1>;
229 fsl,qe-num-snums = <28>; 233 fsl,qe-num-snums = <28>;
230 234
231 muram@10000 { 235 muram@10000 {
232 #address-cells = <1>; 236 #address-cells = <1>;
233 #size-cells = <1>; 237 #size-cells = <1>;
234 compatible = "fsl,qe-m 238 compatible = "fsl,qe-muram", "fsl,cpm-muram";
235 ranges = <0x0 0x000100 239 ranges = <0x0 0x00010000 0x00004000>;
236 240
237 data-only@0 { 241 data-only@0 {
238 compatible = " 242 compatible = "fsl,qe-muram-data",
239 " 243 "fsl,cpm-muram-data";
240 reg = <0x0 0x4 244 reg = <0x0 0x4000>;
241 }; 245 };
242 }; 246 };
243 247
244 spi@4c0 { 248 spi@4c0 {
245 #address-cells = <1>; 249 #address-cells = <1>;
246 #size-cells = <0>; 250 #size-cells = <0>;
247 cell-index = <0>; 251 cell-index = <0>;
248 compatible = "fsl,spi" 252 compatible = "fsl,spi";
249 reg = <0x4c0 0x40>; 253 reg = <0x4c0 0x40>;
250 interrupts = <2>; 254 interrupts = <2>;
251 interrupt-parent = <&q 255 interrupt-parent = <&qeic>;
252 cs-gpios = <&qe_pio_d !! 256 gpios = <&qe_pio_d 13 0>;
253 mode = "cpu-qe"; 257 mode = "cpu-qe";
254 258
255 mmc-slot@0 { 259 mmc-slot@0 {
256 compatible = " 260 compatible = "fsl,mpc8323rdb-mmc-slot",
257 " 261 "mmc-spi-slot";
258 reg = <0>; 262 reg = <0>;
259 gpios = <&qe_p 263 gpios = <&qe_pio_d 14 1
260 &qe_p 264 &qe_pio_d 15 0>;
261 voltage-ranges 265 voltage-ranges = <3300 3300>;
262 spi-max-freque 266 spi-max-frequency = <50000000>;
263 }; 267 };
264 }; 268 };
265 269
266 spi@500 { 270 spi@500 {
267 cell-index = <1>; 271 cell-index = <1>;
268 compatible = "fsl,spi" 272 compatible = "fsl,spi";
269 reg = <0x500 0x40>; 273 reg = <0x500 0x40>;
270 interrupts = <1>; 274 interrupts = <1>;
271 interrupt-parent = <&q 275 interrupt-parent = <&qeic>;
272 mode = "cpu"; 276 mode = "cpu";
273 }; 277 };
274 278
275 enet0: ucc@3000 { 279 enet0: ucc@3000 {
276 device_type = "network 280 device_type = "network";
277 compatible = "ucc_geth 281 compatible = "ucc_geth";
278 cell-index = <2>; 282 cell-index = <2>;
279 reg = <0x3000 0x200>; 283 reg = <0x3000 0x200>;
280 interrupts = <33>; 284 interrupts = <33>;
281 interrupt-parent = <&q 285 interrupt-parent = <&qeic>;
282 local-mac-address = [ 286 local-mac-address = [ 00 00 00 00 00 00 ];
283 rx-clock-name = "clk16 287 rx-clock-name = "clk16";
284 tx-clock-name = "clk3" 288 tx-clock-name = "clk3";
285 phy-handle = <&phy00>; 289 phy-handle = <&phy00>;
286 pio-handle = <&ucc2pio 290 pio-handle = <&ucc2pio>;
287 }; 291 };
288 292
289 enet1: ucc@2200 { 293 enet1: ucc@2200 {
290 device_type = "network 294 device_type = "network";
291 compatible = "ucc_geth 295 compatible = "ucc_geth";
292 cell-index = <3>; 296 cell-index = <3>;
293 reg = <0x2200 0x200>; 297 reg = <0x2200 0x200>;
294 interrupts = <34>; 298 interrupts = <34>;
295 interrupt-parent = <&q 299 interrupt-parent = <&qeic>;
296 local-mac-address = [ 300 local-mac-address = [ 00 00 00 00 00 00 ];
297 rx-clock-name = "clk9" 301 rx-clock-name = "clk9";
298 tx-clock-name = "clk10 302 tx-clock-name = "clk10";
299 phy-handle = <&phy04>; 303 phy-handle = <&phy04>;
300 pio-handle = <&ucc3pio 304 pio-handle = <&ucc3pio>;
301 }; 305 };
302 306
303 mdio@3120 { 307 mdio@3120 {
304 #address-cells = <1>; 308 #address-cells = <1>;
305 #size-cells = <0>; 309 #size-cells = <0>;
306 reg = <0x3120 0x18>; 310 reg = <0x3120 0x18>;
307 compatible = "fsl,ucc- 311 compatible = "fsl,ucc-mdio";
308 312
309 phy00:ethernet-phy@0 { 313 phy00:ethernet-phy@0 {
>> 314 interrupt-parent = <&ipic>;
>> 315 interrupts = <0>;
310 reg = <0x0>; 316 reg = <0x0>;
311 }; 317 };
312 phy04:ethernet-phy@4 { 318 phy04:ethernet-phy@4 {
>> 319 interrupt-parent = <&ipic>;
>> 320 interrupts = <0>;
313 reg = <0x4>; 321 reg = <0x4>;
314 }; 322 };
315 }; 323 };
316 324
317 qeic:interrupt-controller@80 { 325 qeic:interrupt-controller@80 {
318 interrupt-controller; 326 interrupt-controller;
319 compatible = "fsl,qe-i 327 compatible = "fsl,qe-ic";
320 #address-cells = <0>; 328 #address-cells = <0>;
321 #interrupt-cells = <1> 329 #interrupt-cells = <1>;
322 reg = <0x80 0x80>; 330 reg = <0x80 0x80>;
323 big-endian; 331 big-endian;
324 interrupts = <32 0x8 3 332 interrupts = <32 0x8 33 0x8>; //high:32 low:33
325 interrupt-parent = <&i 333 interrupt-parent = <&ipic>;
326 }; 334 };
327 }; 335 };
328 336
329 pci0: pci@e0008500 { 337 pci0: pci@e0008500 {
330 interrupt-map-mask = <0xf800 0 338 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
331 interrupt-map = < 339 interrupt-map = <
332 /* IDSEL 0x10 340 /* IDSEL 0x10 AD16 (USB) */
333 0x8000 0x0 0x 341 0x8000 0x0 0x0 0x1 &ipic 17 0x8
334 342
335 /* IDSEL 0x11 343 /* IDSEL 0x11 AD17 (Mini1)*/
336 0x8800 0x0 0x 344 0x8800 0x0 0x0 0x1 &ipic 18 0x8
337 0x8800 0x0 0x 345 0x8800 0x0 0x0 0x2 &ipic 19 0x8
338 0x8800 0x0 0x 346 0x8800 0x0 0x0 0x3 &ipic 20 0x8
339 0x8800 0x0 0x 347 0x8800 0x0 0x0 0x4 &ipic 48 0x8
340 348
341 /* IDSEL 0x12 349 /* IDSEL 0x12 AD18 (PCI/Mini2) */
342 0x9000 0x0 0x 350 0x9000 0x0 0x0 0x1 &ipic 19 0x8
343 0x9000 0x0 0x 351 0x9000 0x0 0x0 0x2 &ipic 20 0x8
344 0x9000 0x0 0x 352 0x9000 0x0 0x0 0x3 &ipic 48 0x8
345 0x9000 0x0 0x 353 0x9000 0x0 0x0 0x4 &ipic 17 0x8>;
346 354
347 interrupt-parent = <&ipic>; 355 interrupt-parent = <&ipic>;
348 interrupts = <66 0x8>; 356 interrupts = <66 0x8>;
349 bus-range = <0x0 0x0>; 357 bus-range = <0x0 0x0>;
350 ranges = <0x42000000 0x0 0x800 358 ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
351 0x02000000 0x0 0x900 359 0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
352 0x01000000 0x0 0xd00 360 0x01000000 0x0 0xd0000000 0xd0000000 0x0 0x04000000>;
353 clock-frequency = <0>; 361 clock-frequency = <0>;
354 #interrupt-cells = <1>; 362 #interrupt-cells = <1>;
355 #size-cells = <2>; 363 #size-cells = <2>;
356 #address-cells = <3>; 364 #address-cells = <3>;
357 reg = <0xe0008500 0x100 365 reg = <0xe0008500 0x100 /* internal registers */
358 0xe0008300 0x8>; 366 0xe0008300 0x8>; /* config space access registers */
359 compatible = "fsl,mpc8349-pci" 367 compatible = "fsl,mpc8349-pci";
360 device_type = "pci"; 368 device_type = "pci";
361 sleep = <&pmc 0x00010000>; 369 sleep = <&pmc 0x00010000>;
362 }; 370 };
363 }; 371 };
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