1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * MPC8377E RDB Device Tree Source
4 *
5 * Copyright 2007, 2008 Freescale Semiconducto
6 */
7
8 /dts-v1/;
9
10 / {
11 compatible = "fsl,mpc8377rdb";
12 #address-cells = <1>;
13 #size-cells = <1>;
14
15 aliases {
16 ethernet0 = &enet0;
17 ethernet1 = &enet1;
18 serial0 = &serial0;
19 serial1 = &serial1;
20 pci0 = &pci0;
21 pci1 = &pci1;
22 pci2 = &pci2;
23 };
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 PowerPC,8377@0 {
30 device_type = "cpu";
31 reg = <0x0>;
32 d-cache-line-size = <3
33 i-cache-line-size = <3
34 d-cache-size = <32768>
35 i-cache-size = <32768>
36 timebase-frequency = <
37 bus-frequency = <0>;
38 clock-frequency = <0>;
39 };
40 };
41
42 memory {
43 device_type = "memory";
44 reg = <0x00000000 0x10000000>;
45 };
46
47 localbus@e0005000 {
48 #address-cells = <2>;
49 #size-cells = <1>;
50 compatible = "fsl,mpc8377-elbc
51 reg = <0xe0005000 0x1000>;
52 interrupts = <77 0x8>;
53 interrupt-parent = <&ipic>;
54
55 // CS0 and CS1 are swapped whe
56 // booting from nand, but the
57 // addresses are the same.
58 ranges = <0x0 0x0 0xfe000000 0
59 0x1 0x0 0xe0600000 0
60 0x2 0x0 0xf0000000 0
61 0x3 0x0 0xfa000000 0
62
63 flash@0,0 {
64 #address-cells = <1>;
65 #size-cells = <1>;
66 compatible = "cfi-flas
67 reg = <0x0 0x0 0x80000
68 bank-width = <2>;
69 device-width = <1>;
70 };
71
72 nand@1,0 {
73 #address-cells = <1>;
74 #size-cells = <1>;
75 compatible = "fsl,mpc8
76 "fsl,elbc
77 reg = <0x1 0x0 0x8000>
78
79 u-boot@0 {
80 reg = <0x0 0x1
81 read-only;
82 };
83
84 kernel@100000 {
85 reg = <0x10000
86 };
87 fs@400000 {
88 reg = <0x40000
89 };
90 };
91 };
92
93 immr@e0000000 {
94 #address-cells = <1>;
95 #size-cells = <1>;
96 device_type = "soc";
97 compatible = "simple-bus";
98 ranges = <0x0 0xe0000000 0x001
99 reg = <0xe0000000 0x00000200>;
100 bus-frequency = <0>;
101
102 wdt@200 {
103 device_type = "watchdo
104 compatible = "mpc83xx_
105 reg = <0x200 0x100>;
106 };
107
108 gpio1: gpio-controller@c00 {
109 #gpio-cells = <2>;
110 compatible = "fsl,mpc8
111 reg = <0xc00 0x100>;
112 interrupts = <74 0x8>;
113 interrupt-parent = <&i
114 gpio-controller;
115 };
116
117 gpio2: gpio-controller@d00 {
118 #gpio-cells = <2>;
119 compatible = "fsl,mpc8
120 reg = <0xd00 0x100>;
121 interrupts = <75 0x8>;
122 interrupt-parent = <&i
123 gpio-controller;
124 };
125
126 sleep-nexus {
127 #address-cells = <1>;
128 #size-cells = <1>;
129 compatible = "simple-b
130 sleep = <&pmc 0x0c0000
131 ranges;
132
133 i2c@3000 {
134 #address-cells
135 #size-cells =
136 cell-index = <
137 compatible = "
138 reg = <0x3000
139 interrupts = <
140 interrupt-pare
141 dfsrr;
142
143 dtt@48 {
144 compat
145 reg =
146 };
147
148 at24@50 {
149 compat
150 reg =
151 };
152
153 rtc@68 {
154 compat
155 reg =
156 };
157
158 mcu_pio: mcu@a
159 #gpio-
160 compat
161
162 reg =
163 gpio-c
164 };
165 };
166
167 sdhci@2e000 {
168 compatible = "
169 reg = <0x2e000
170 interrupts = <
171 interrupt-pare
172 sdhci,wp-inver
173 /* Filled in b
174 clock-frequenc
175 };
176 };
177
178 i2c@3100 {
179 #address-cells = <1>;
180 #size-cells = <0>;
181 cell-index = <1>;
182 compatible = "fsl-i2c"
183 reg = <0x3100 0x100>;
184 interrupts = <15 0x8>;
185 interrupt-parent = <&i
186 dfsrr;
187 };
188
189 spi@7000 {
190 cell-index = <0>;
191 compatible = "fsl,spi"
192 reg = <0x7000 0x1000>;
193 interrupts = <16 0x8>;
194 interrupt-parent = <&i
195 mode = "cpu";
196 };
197
198 dma@82a8 {
199 #address-cells = <1>;
200 #size-cells = <1>;
201 compatible = "fsl,mpc8
202 reg = <0x82a8 4>;
203 ranges = <0 0x8100 0x1
204 interrupt-parent = <&i
205 interrupts = <71 8>;
206 cell-index = <0>;
207 dma-channel@0 {
208 compatible = "
209 reg = <0 0x80>
210 cell-index = <
211 interrupt-pare
212 interrupts = <
213 };
214 dma-channel@80 {
215 compatible = "
216 reg = <0x80 0x
217 cell-index = <
218 interrupt-pare
219 interrupts = <
220 };
221 dma-channel@100 {
222 compatible = "
223 reg = <0x100 0
224 cell-index = <
225 interrupt-pare
226 interrupts = <
227 };
228 dma-channel@180 {
229 compatible = "
230 reg = <0x180 0
231 cell-index = <
232 interrupt-pare
233 interrupts = <
234 };
235 };
236
237 usb@23000 {
238 compatible = "fsl-usb2
239 reg = <0x23000 0x1000>
240 #address-cells = <1>;
241 #size-cells = <0>;
242 interrupt-parent = <&i
243 interrupts = <38 0x8>;
244 phy_type = "ulpi";
245 sleep = <&pmc 0x00c000
246 };
247
248 enet0: ethernet@24000 {
249 #address-cells = <1>;
250 #size-cells = <1>;
251 cell-index = <0>;
252 device_type = "network
253 model = "eTSEC";
254 compatible = "gianfar"
255 reg = <0x24000 0x1000>
256 ranges = <0x0 0x24000
257 local-mac-address = [
258 interrupts = <32 0x8 3
259 phy-connection-type =
260 interrupt-parent = <&i
261 tbi-handle = <&tbi0>;
262 phy-handle = <&phy2>;
263 sleep = <&pmc 0xc00000
264 fsl,magic-packet;
265
266 mdio@520 {
267 #address-cells
268 #size-cells =
269 compatible = "
270 reg = <0x520 0
271
272 phy2: ethernet
273 interr
274 interr
275 reg =
276 };
277
278 tbi0: tbi-phy@
279 reg =
280 device
281 };
282 };
283 };
284
285 enet1: ethernet@25000 {
286 #address-cells = <1>;
287 #size-cells = <1>;
288 cell-index = <1>;
289 device_type = "network
290 model = "eTSEC";
291 compatible = "gianfar"
292 reg = <0x25000 0x1000>
293 ranges = <0x0 0x25000
294 local-mac-address = [
295 interrupts = <35 0x8 3
296 phy-connection-type =
297 interrupt-parent = <&i
298 fixed-link = <1 1 1000
299 tbi-handle = <&tbi1>;
300 sleep = <&pmc 0x300000
301 fsl,magic-packet;
302
303 mdio@520 {
304 #address-cells
305 #size-cells =
306 compatible = "
307 reg = <0x520 0
308
309 tbi1: tbi-phy@
310 reg =
311 device
312 };
313 };
314 };
315
316 serial0: serial@4500 {
317 cell-index = <0>;
318 device_type = "serial"
319 compatible = "fsl,ns16
320 reg = <0x4500 0x100>;
321 clock-frequency = <0>;
322 interrupts = <9 0x8>;
323 interrupt-parent = <&i
324 };
325
326 serial1: serial@4600 {
327 cell-index = <1>;
328 device_type = "serial"
329 compatible = "fsl,ns16
330 reg = <0x4600 0x100>;
331 clock-frequency = <0>;
332 interrupts = <10 0x8>;
333 interrupt-parent = <&i
334 };
335
336 crypto@30000 {
337 compatible = "fsl,sec3
338 "fsl,sec2
339 reg = <0x30000 0x10000
340 interrupts = <11 0x8>;
341 interrupt-parent = <&i
342 fsl,num-channels = <4>
343 fsl,channel-fifo-len =
344 fsl,exec-units-mask =
345 fsl,descriptor-types-m
346 sleep = <&pmc 0x030000
347 };
348
349 sata@18000 {
350 compatible = "fsl,mpc8
351 reg = <0x18000 0x1000>
352 interrupts = <44 0x8>;
353 interrupt-parent = <&i
354 sleep = <&pmc 0x000000
355 };
356
357 sata@19000 {
358 compatible = "fsl,mpc8
359 reg = <0x19000 0x1000>
360 interrupts = <45 0x8>;
361 interrupt-parent = <&i
362 sleep = <&pmc 0x000000
363 };
364
365 /* IPIC
366 * interrupts cell = <intr #,
367 * sense values match linux IO
368 * sense == 8: Level, low asse
369 * sense == 2: Edge, high-to-l
370 */
371 ipic: interrupt-controller@700
372 compatible = "fsl,ipic
373 interrupt-controller;
374 #address-cells = <0>;
375 #interrupt-cells = <2>
376 reg = <0x700 0x100>;
377 };
378
379 pmc: power@b00 {
380 compatible = "fsl,mpc8
381 reg = <0xb00 0x100 0xa
382 interrupts = <80 0x8>;
383 interrupt-parent = <&i
384 };
385 };
386
387 pci0: pci@e0008500 {
388 interrupt-map-mask = <0xf800 0
389 interrupt-map = <
390 /* IRQ5 = 21 =
391
392 /* IDSEL AD14
393 0x7000 0x0 0x
394
395 /* IDSEL AD15
396 0x7800 0x0 0x
397 0x7800 0x0 0x
398 0x7800 0x0 0x
399
400 /* IDSEL AD28
401 0xE000 0x0 0x
402 0xE000 0x0 0x
403 0xE000 0x0 0x
404 interrupt-parent = <&ipic>;
405 interrupts = <66 0x8>;
406 bus-range = <0 0>;
407 ranges = <0x02000000 0x0 0x900
408 0x42000000 0x0 0x800
409 0x01000000 0x0 0x000
410 sleep = <&pmc 0x00010000>;
411 clock-frequency = <66666666>;
412 #interrupt-cells = <1>;
413 #size-cells = <2>;
414 #address-cells = <3>;
415 reg = <0xe0008500 0x100
416 0xe0008300 0x8>;
417 compatible = "fsl,mpc8349-pci"
418 device_type = "pci";
419 };
420
421 pci1: pcie@e0009000 {
422 #address-cells = <3>;
423 #size-cells = <2>;
424 #interrupt-cells = <1>;
425 device_type = "pci";
426 compatible = "fsl,mpc8377-pcie
427 reg = <0xe0009000 0x00001000>;
428 ranges = <0x02000000 0 0xa8000
429 0x01000000 0 0x00000
430 bus-range = <0 255>;
431 interrupt-map-mask = <0xf800 0
432 interrupt-map = <0 0 0 1 &ipic
433 0 0 0 2 &ipic
434 0 0 0 3 &ipic
435 0 0 0 4 &ipic
436 sleep = <&pmc 0x00300000>;
437 clock-frequency = <0>;
438
439 pcie@0 {
440 #address-cells = <3>;
441 #size-cells = <2>;
442 device_type = "pci";
443 reg = <0 0 0 0 0>;
444 ranges = <0x02000000 0
445 0x02000000 0
446 0 0x10000000
447 0x01000000 0
448 0x01000000 0
449 0 0x00800000
450 };
451 };
452
453 pci2: pcie@e000a000 {
454 #address-cells = <3>;
455 #size-cells = <2>;
456 #interrupt-cells = <1>;
457 device_type = "pci";
458 compatible = "fsl,mpc8377-pcie
459 reg = <0xe000a000 0x00001000>;
460 ranges = <0x02000000 0 0xc8000
461 0x01000000 0 0x00000
462 bus-range = <0 255>;
463 interrupt-map-mask = <0xf800 0
464 interrupt-map = <0 0 0 1 &ipic
465 0 0 0 2 &ipic
466 0 0 0 3 &ipic
467 0 0 0 4 &ipic
468 sleep = <&pmc 0x000c0000>;
469 clock-frequency = <0>;
470
471 pcie@0 {
472 #address-cells = <3>;
473 #size-cells = <2>;
474 device_type = "pci";
475 reg = <0 0 0 0 0>;
476 ranges = <0x02000000 0
477 0x02000000 0
478 0 0x10000000
479 0x01000000 0
480 0x01000000 0
481 0 0x00800000
482 };
483 };
484
485 leds {
486 compatible = "gpio-leds";
487
488 pwr {
489 gpios = <&mcu_pio 0 0>
490 default-state = "on";
491 };
492
493 hdd {
494 gpios = <&mcu_pio 1 0>
495 linux,default-trigger
496 };
497 };
498 };
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