1 // SPDX-License-Identifier: GPL-2.0-or-later <<
2 /* 1 /*
3 * MPC8377E RDB Device Tree Source 2 * MPC8377E RDB Device Tree Source
4 * 3 *
5 * Copyright 2007, 2008 Freescale Semiconducto 4 * Copyright 2007, 2008 Freescale Semiconductor Inc.
>> 5 *
>> 6 * This program is free software; you can redistribute it and/or modify it
>> 7 * under the terms of the GNU General Public License as published by the
>> 8 * Free Software Foundation; either version 2 of the License, or (at your
>> 9 * option) any later version.
6 */ 10 */
7 11
8 /dts-v1/; 12 /dts-v1/;
9 13
10 / { 14 / {
11 compatible = "fsl,mpc8377rdb"; 15 compatible = "fsl,mpc8377rdb";
12 #address-cells = <1>; 16 #address-cells = <1>;
13 #size-cells = <1>; 17 #size-cells = <1>;
14 18
15 aliases { 19 aliases {
16 ethernet0 = &enet0; 20 ethernet0 = &enet0;
17 ethernet1 = &enet1; 21 ethernet1 = &enet1;
18 serial0 = &serial0; 22 serial0 = &serial0;
19 serial1 = &serial1; 23 serial1 = &serial1;
20 pci0 = &pci0; 24 pci0 = &pci0;
21 pci1 = &pci1; 25 pci1 = &pci1;
22 pci2 = &pci2; 26 pci2 = &pci2;
23 }; 27 };
24 28
25 cpus { 29 cpus {
26 #address-cells = <1>; 30 #address-cells = <1>;
27 #size-cells = <0>; 31 #size-cells = <0>;
28 32
29 PowerPC,8377@0 { 33 PowerPC,8377@0 {
30 device_type = "cpu"; 34 device_type = "cpu";
31 reg = <0x0>; 35 reg = <0x0>;
32 d-cache-line-size = <3 36 d-cache-line-size = <32>;
33 i-cache-line-size = <3 37 i-cache-line-size = <32>;
34 d-cache-size = <32768> 38 d-cache-size = <32768>;
35 i-cache-size = <32768> 39 i-cache-size = <32768>;
36 timebase-frequency = < 40 timebase-frequency = <0>;
37 bus-frequency = <0>; 41 bus-frequency = <0>;
38 clock-frequency = <0>; 42 clock-frequency = <0>;
39 }; 43 };
40 }; 44 };
41 45
42 memory { 46 memory {
43 device_type = "memory"; 47 device_type = "memory";
44 reg = <0x00000000 0x10000000>; 48 reg = <0x00000000 0x10000000>; // 256MB at 0
45 }; 49 };
46 50
47 localbus@e0005000 { 51 localbus@e0005000 {
48 #address-cells = <2>; 52 #address-cells = <2>;
49 #size-cells = <1>; 53 #size-cells = <1>;
50 compatible = "fsl,mpc8377-elbc 54 compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
51 reg = <0xe0005000 0x1000>; 55 reg = <0xe0005000 0x1000>;
52 interrupts = <77 0x8>; 56 interrupts = <77 0x8>;
53 interrupt-parent = <&ipic>; 57 interrupt-parent = <&ipic>;
54 58
55 // CS0 and CS1 are swapped whe 59 // CS0 and CS1 are swapped when
56 // booting from nand, but the 60 // booting from nand, but the
57 // addresses are the same. 61 // addresses are the same.
58 ranges = <0x0 0x0 0xfe000000 0 62 ranges = <0x0 0x0 0xfe000000 0x00800000
59 0x1 0x0 0xe0600000 0 63 0x1 0x0 0xe0600000 0x00008000
60 0x2 0x0 0xf0000000 0 64 0x2 0x0 0xf0000000 0x00020000
61 0x3 0x0 0xfa000000 0 65 0x3 0x0 0xfa000000 0x00008000>;
62 66
63 flash@0,0 { 67 flash@0,0 {
64 #address-cells = <1>; 68 #address-cells = <1>;
65 #size-cells = <1>; 69 #size-cells = <1>;
66 compatible = "cfi-flas 70 compatible = "cfi-flash";
67 reg = <0x0 0x0 0x80000 71 reg = <0x0 0x0 0x800000>;
68 bank-width = <2>; 72 bank-width = <2>;
69 device-width = <1>; 73 device-width = <1>;
70 }; 74 };
71 75
72 nand@1,0 { 76 nand@1,0 {
73 #address-cells = <1>; 77 #address-cells = <1>;
74 #size-cells = <1>; 78 #size-cells = <1>;
75 compatible = "fsl,mpc8 79 compatible = "fsl,mpc8377-fcm-nand",
76 "fsl,elbc 80 "fsl,elbc-fcm-nand";
77 reg = <0x1 0x0 0x8000> 81 reg = <0x1 0x0 0x8000>;
78 82
79 u-boot@0 { 83 u-boot@0 {
80 reg = <0x0 0x1 84 reg = <0x0 0x100000>;
81 read-only; 85 read-only;
82 }; 86 };
83 87
84 kernel@100000 { 88 kernel@100000 {
85 reg = <0x10000 89 reg = <0x100000 0x300000>;
86 }; 90 };
87 fs@400000 { 91 fs@400000 {
88 reg = <0x40000 92 reg = <0x400000 0x1c00000>;
89 }; 93 };
90 }; 94 };
91 }; 95 };
92 96
93 immr@e0000000 { 97 immr@e0000000 {
94 #address-cells = <1>; 98 #address-cells = <1>;
95 #size-cells = <1>; 99 #size-cells = <1>;
96 device_type = "soc"; 100 device_type = "soc";
97 compatible = "simple-bus"; 101 compatible = "simple-bus";
98 ranges = <0x0 0xe0000000 0x001 102 ranges = <0x0 0xe0000000 0x00100000>;
99 reg = <0xe0000000 0x00000200>; 103 reg = <0xe0000000 0x00000200>;
100 bus-frequency = <0>; 104 bus-frequency = <0>;
101 105
102 wdt@200 { 106 wdt@200 {
103 device_type = "watchdo 107 device_type = "watchdog";
104 compatible = "mpc83xx_ 108 compatible = "mpc83xx_wdt";
105 reg = <0x200 0x100>; 109 reg = <0x200 0x100>;
106 }; 110 };
107 111
108 gpio1: gpio-controller@c00 { 112 gpio1: gpio-controller@c00 {
109 #gpio-cells = <2>; 113 #gpio-cells = <2>;
110 compatible = "fsl,mpc8 114 compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
111 reg = <0xc00 0x100>; 115 reg = <0xc00 0x100>;
112 interrupts = <74 0x8>; 116 interrupts = <74 0x8>;
113 interrupt-parent = <&i 117 interrupt-parent = <&ipic>;
114 gpio-controller; 118 gpio-controller;
115 }; 119 };
116 120
117 gpio2: gpio-controller@d00 { 121 gpio2: gpio-controller@d00 {
118 #gpio-cells = <2>; 122 #gpio-cells = <2>;
119 compatible = "fsl,mpc8 123 compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
120 reg = <0xd00 0x100>; 124 reg = <0xd00 0x100>;
121 interrupts = <75 0x8>; 125 interrupts = <75 0x8>;
122 interrupt-parent = <&i 126 interrupt-parent = <&ipic>;
123 gpio-controller; 127 gpio-controller;
124 }; 128 };
125 129
126 sleep-nexus { 130 sleep-nexus {
127 #address-cells = <1>; 131 #address-cells = <1>;
128 #size-cells = <1>; 132 #size-cells = <1>;
129 compatible = "simple-b 133 compatible = "simple-bus";
130 sleep = <&pmc 0x0c0000 134 sleep = <&pmc 0x0c000000>;
131 ranges; 135 ranges;
132 136
133 i2c@3000 { 137 i2c@3000 {
134 #address-cells 138 #address-cells = <1>;
135 #size-cells = 139 #size-cells = <0>;
136 cell-index = < 140 cell-index = <0>;
137 compatible = " 141 compatible = "fsl-i2c";
138 reg = <0x3000 142 reg = <0x3000 0x100>;
139 interrupts = < 143 interrupts = <14 0x8>;
140 interrupt-pare 144 interrupt-parent = <&ipic>;
141 dfsrr; 145 dfsrr;
142 146
143 dtt@48 { 147 dtt@48 {
144 compat 148 compatible = "national,lm75";
145 reg = 149 reg = <0x48>;
146 }; 150 };
147 151
148 at24@50 { 152 at24@50 {
149 compat !! 153 compatible = "at24,24c256";
150 reg = 154 reg = <0x50>;
151 }; 155 };
152 156
153 rtc@68 { 157 rtc@68 {
154 compat 158 compatible = "dallas,ds1339";
155 reg = 159 reg = <0x68>;
156 }; 160 };
157 161
158 mcu_pio: mcu@a 162 mcu_pio: mcu@a {
159 #gpio- 163 #gpio-cells = <2>;
160 compat 164 compatible = "fsl,mc9s08qg8-mpc8377erdb",
161 165 "fsl,mcu-mpc8349emitx";
162 reg = 166 reg = <0x0a>;
163 gpio-c 167 gpio-controller;
164 }; 168 };
165 }; 169 };
166 170
167 sdhci@2e000 { 171 sdhci@2e000 {
168 compatible = " 172 compatible = "fsl,mpc8377-esdhc", "fsl,esdhc";
169 reg = <0x2e000 173 reg = <0x2e000 0x1000>;
170 interrupts = < 174 interrupts = <42 0x8>;
171 interrupt-pare 175 interrupt-parent = <&ipic>;
172 sdhci,wp-inver 176 sdhci,wp-inverted;
173 /* Filled in b 177 /* Filled in by U-Boot */
174 clock-frequenc 178 clock-frequency = <111111111>;
175 }; 179 };
176 }; 180 };
177 181
178 i2c@3100 { 182 i2c@3100 {
179 #address-cells = <1>; 183 #address-cells = <1>;
180 #size-cells = <0>; 184 #size-cells = <0>;
181 cell-index = <1>; 185 cell-index = <1>;
182 compatible = "fsl-i2c" 186 compatible = "fsl-i2c";
183 reg = <0x3100 0x100>; 187 reg = <0x3100 0x100>;
184 interrupts = <15 0x8>; 188 interrupts = <15 0x8>;
185 interrupt-parent = <&i 189 interrupt-parent = <&ipic>;
186 dfsrr; 190 dfsrr;
187 }; 191 };
188 192
189 spi@7000 { 193 spi@7000 {
190 cell-index = <0>; 194 cell-index = <0>;
191 compatible = "fsl,spi" 195 compatible = "fsl,spi";
192 reg = <0x7000 0x1000>; 196 reg = <0x7000 0x1000>;
193 interrupts = <16 0x8>; 197 interrupts = <16 0x8>;
194 interrupt-parent = <&i 198 interrupt-parent = <&ipic>;
195 mode = "cpu"; 199 mode = "cpu";
196 }; 200 };
197 201
198 dma@82a8 { 202 dma@82a8 {
199 #address-cells = <1>; 203 #address-cells = <1>;
200 #size-cells = <1>; 204 #size-cells = <1>;
201 compatible = "fsl,mpc8 205 compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
202 reg = <0x82a8 4>; 206 reg = <0x82a8 4>;
203 ranges = <0 0x8100 0x1 207 ranges = <0 0x8100 0x1a8>;
204 interrupt-parent = <&i 208 interrupt-parent = <&ipic>;
205 interrupts = <71 8>; 209 interrupts = <71 8>;
206 cell-index = <0>; 210 cell-index = <0>;
207 dma-channel@0 { 211 dma-channel@0 {
208 compatible = " 212 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
209 reg = <0 0x80> 213 reg = <0 0x80>;
210 cell-index = < 214 cell-index = <0>;
211 interrupt-pare 215 interrupt-parent = <&ipic>;
212 interrupts = < 216 interrupts = <71 8>;
213 }; 217 };
214 dma-channel@80 { 218 dma-channel@80 {
215 compatible = " 219 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
216 reg = <0x80 0x 220 reg = <0x80 0x80>;
217 cell-index = < 221 cell-index = <1>;
218 interrupt-pare 222 interrupt-parent = <&ipic>;
219 interrupts = < 223 interrupts = <71 8>;
220 }; 224 };
221 dma-channel@100 { 225 dma-channel@100 {
222 compatible = " 226 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
223 reg = <0x100 0 227 reg = <0x100 0x80>;
224 cell-index = < 228 cell-index = <2>;
225 interrupt-pare 229 interrupt-parent = <&ipic>;
226 interrupts = < 230 interrupts = <71 8>;
227 }; 231 };
228 dma-channel@180 { 232 dma-channel@180 {
229 compatible = " 233 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
230 reg = <0x180 0 234 reg = <0x180 0x28>;
231 cell-index = < 235 cell-index = <3>;
232 interrupt-pare 236 interrupt-parent = <&ipic>;
233 interrupts = < 237 interrupts = <71 8>;
234 }; 238 };
235 }; 239 };
236 240
237 usb@23000 { 241 usb@23000 {
238 compatible = "fsl-usb2 242 compatible = "fsl-usb2-dr";
239 reg = <0x23000 0x1000> 243 reg = <0x23000 0x1000>;
240 #address-cells = <1>; 244 #address-cells = <1>;
241 #size-cells = <0>; 245 #size-cells = <0>;
242 interrupt-parent = <&i 246 interrupt-parent = <&ipic>;
243 interrupts = <38 0x8>; 247 interrupts = <38 0x8>;
244 phy_type = "ulpi"; 248 phy_type = "ulpi";
245 sleep = <&pmc 0x00c000 249 sleep = <&pmc 0x00c00000>;
246 }; 250 };
247 251
248 enet0: ethernet@24000 { 252 enet0: ethernet@24000 {
249 #address-cells = <1>; 253 #address-cells = <1>;
250 #size-cells = <1>; 254 #size-cells = <1>;
251 cell-index = <0>; 255 cell-index = <0>;
252 device_type = "network 256 device_type = "network";
253 model = "eTSEC"; 257 model = "eTSEC";
254 compatible = "gianfar" 258 compatible = "gianfar";
255 reg = <0x24000 0x1000> 259 reg = <0x24000 0x1000>;
256 ranges = <0x0 0x24000 260 ranges = <0x0 0x24000 0x1000>;
257 local-mac-address = [ 261 local-mac-address = [ 00 00 00 00 00 00 ];
258 interrupts = <32 0x8 3 262 interrupts = <32 0x8 33 0x8 34 0x8>;
259 phy-connection-type = 263 phy-connection-type = "mii";
260 interrupt-parent = <&i 264 interrupt-parent = <&ipic>;
261 tbi-handle = <&tbi0>; 265 tbi-handle = <&tbi0>;
262 phy-handle = <&phy2>; 266 phy-handle = <&phy2>;
263 sleep = <&pmc 0xc00000 267 sleep = <&pmc 0xc0000000>;
264 fsl,magic-packet; 268 fsl,magic-packet;
265 269
266 mdio@520 { 270 mdio@520 {
267 #address-cells 271 #address-cells = <1>;
268 #size-cells = 272 #size-cells = <0>;
269 compatible = " 273 compatible = "fsl,gianfar-mdio";
270 reg = <0x520 0 274 reg = <0x520 0x20>;
271 275
272 phy2: ethernet 276 phy2: ethernet-phy@2 {
273 interr 277 interrupt-parent = <&ipic>;
274 interr 278 interrupts = <17 0x8>;
275 reg = 279 reg = <0x2>;
276 }; 280 };
277 281
278 tbi0: tbi-phy@ 282 tbi0: tbi-phy@11 {
279 reg = 283 reg = <0x11>;
280 device 284 device_type = "tbi-phy";
281 }; 285 };
282 }; 286 };
283 }; 287 };
284 288
285 enet1: ethernet@25000 { 289 enet1: ethernet@25000 {
286 #address-cells = <1>; 290 #address-cells = <1>;
287 #size-cells = <1>; 291 #size-cells = <1>;
288 cell-index = <1>; 292 cell-index = <1>;
289 device_type = "network 293 device_type = "network";
290 model = "eTSEC"; 294 model = "eTSEC";
291 compatible = "gianfar" 295 compatible = "gianfar";
292 reg = <0x25000 0x1000> 296 reg = <0x25000 0x1000>;
293 ranges = <0x0 0x25000 297 ranges = <0x0 0x25000 0x1000>;
294 local-mac-address = [ 298 local-mac-address = [ 00 00 00 00 00 00 ];
295 interrupts = <35 0x8 3 299 interrupts = <35 0x8 36 0x8 37 0x8>;
296 phy-connection-type = 300 phy-connection-type = "mii";
297 interrupt-parent = <&i 301 interrupt-parent = <&ipic>;
298 fixed-link = <1 1 1000 302 fixed-link = <1 1 1000 0 0>;
299 tbi-handle = <&tbi1>; 303 tbi-handle = <&tbi1>;
300 sleep = <&pmc 0x300000 304 sleep = <&pmc 0x30000000>;
301 fsl,magic-packet; 305 fsl,magic-packet;
302 306
303 mdio@520 { 307 mdio@520 {
304 #address-cells 308 #address-cells = <1>;
305 #size-cells = 309 #size-cells = <0>;
306 compatible = " 310 compatible = "fsl,gianfar-tbi";
307 reg = <0x520 0 311 reg = <0x520 0x20>;
308 312
309 tbi1: tbi-phy@ 313 tbi1: tbi-phy@11 {
310 reg = 314 reg = <0x11>;
311 device 315 device_type = "tbi-phy";
312 }; 316 };
313 }; 317 };
314 }; 318 };
315 319
316 serial0: serial@4500 { 320 serial0: serial@4500 {
317 cell-index = <0>; 321 cell-index = <0>;
318 device_type = "serial" 322 device_type = "serial";
319 compatible = "fsl,ns16 323 compatible = "fsl,ns16550", "ns16550";
320 reg = <0x4500 0x100>; 324 reg = <0x4500 0x100>;
321 clock-frequency = <0>; 325 clock-frequency = <0>;
322 interrupts = <9 0x8>; 326 interrupts = <9 0x8>;
323 interrupt-parent = <&i 327 interrupt-parent = <&ipic>;
324 }; 328 };
325 329
326 serial1: serial@4600 { 330 serial1: serial@4600 {
327 cell-index = <1>; 331 cell-index = <1>;
328 device_type = "serial" 332 device_type = "serial";
329 compatible = "fsl,ns16 333 compatible = "fsl,ns16550", "ns16550";
330 reg = <0x4600 0x100>; 334 reg = <0x4600 0x100>;
331 clock-frequency = <0>; 335 clock-frequency = <0>;
332 interrupts = <10 0x8>; 336 interrupts = <10 0x8>;
333 interrupt-parent = <&i 337 interrupt-parent = <&ipic>;
334 }; 338 };
335 339
336 crypto@30000 { 340 crypto@30000 {
337 compatible = "fsl,sec3 341 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
338 "fsl,sec2 342 "fsl,sec2.1", "fsl,sec2.0";
339 reg = <0x30000 0x10000 343 reg = <0x30000 0x10000>;
340 interrupts = <11 0x8>; 344 interrupts = <11 0x8>;
341 interrupt-parent = <&i 345 interrupt-parent = <&ipic>;
342 fsl,num-channels = <4> 346 fsl,num-channels = <4>;
343 fsl,channel-fifo-len = 347 fsl,channel-fifo-len = <24>;
344 fsl,exec-units-mask = 348 fsl,exec-units-mask = <0x9fe>;
345 fsl,descriptor-types-m 349 fsl,descriptor-types-mask = <0x3ab0ebf>;
346 sleep = <&pmc 0x030000 350 sleep = <&pmc 0x03000000>;
347 }; 351 };
348 352
349 sata@18000 { 353 sata@18000 {
350 compatible = "fsl,mpc8 354 compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
351 reg = <0x18000 0x1000> 355 reg = <0x18000 0x1000>;
352 interrupts = <44 0x8>; 356 interrupts = <44 0x8>;
353 interrupt-parent = <&i 357 interrupt-parent = <&ipic>;
354 sleep = <&pmc 0x000000 358 sleep = <&pmc 0x000000c0>;
355 }; 359 };
356 360
357 sata@19000 { 361 sata@19000 {
358 compatible = "fsl,mpc8 362 compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
359 reg = <0x19000 0x1000> 363 reg = <0x19000 0x1000>;
360 interrupts = <45 0x8>; 364 interrupts = <45 0x8>;
361 interrupt-parent = <&i 365 interrupt-parent = <&ipic>;
362 sleep = <&pmc 0x000000 366 sleep = <&pmc 0x00000030>;
363 }; 367 };
364 368
365 /* IPIC 369 /* IPIC
366 * interrupts cell = <intr #, 370 * interrupts cell = <intr #, sense>
367 * sense values match linux IO 371 * sense values match linux IORESOURCE_IRQ_* defines:
368 * sense == 8: Level, low asse 372 * sense == 8: Level, low assertion
369 * sense == 2: Edge, high-to-l 373 * sense == 2: Edge, high-to-low change
370 */ 374 */
371 ipic: interrupt-controller@700 375 ipic: interrupt-controller@700 {
372 compatible = "fsl,ipic 376 compatible = "fsl,ipic";
373 interrupt-controller; 377 interrupt-controller;
374 #address-cells = <0>; 378 #address-cells = <0>;
375 #interrupt-cells = <2> 379 #interrupt-cells = <2>;
376 reg = <0x700 0x100>; 380 reg = <0x700 0x100>;
377 }; 381 };
378 382
379 pmc: power@b00 { 383 pmc: power@b00 {
380 compatible = "fsl,mpc8 384 compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc";
381 reg = <0xb00 0x100 0xa 385 reg = <0xb00 0x100 0xa00 0x100>;
382 interrupts = <80 0x8>; 386 interrupts = <80 0x8>;
383 interrupt-parent = <&i 387 interrupt-parent = <&ipic>;
384 }; 388 };
385 }; 389 };
386 390
387 pci0: pci@e0008500 { 391 pci0: pci@e0008500 {
388 interrupt-map-mask = <0xf800 0 392 interrupt-map-mask = <0xf800 0 0 7>;
389 interrupt-map = < 393 interrupt-map = <
390 /* IRQ5 = 21 = 394 /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
391 395
392 /* IDSEL AD14 396 /* IDSEL AD14 IRQ6 inta */
393 0x7000 0x0 0x 397 0x7000 0x0 0x0 0x1 &ipic 22 0x8
394 398
395 /* IDSEL AD15 399 /* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
396 0x7800 0x0 0x 400 0x7800 0x0 0x0 0x1 &ipic 21 0x8
397 0x7800 0x0 0x 401 0x7800 0x0 0x0 0x2 &ipic 22 0x8
398 0x7800 0x0 0x 402 0x7800 0x0 0x0 0x4 &ipic 23 0x8
399 403
400 /* IDSEL AD28 404 /* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
401 0xE000 0x0 0x 405 0xE000 0x0 0x0 0x1 &ipic 23 0x8
402 0xE000 0x0 0x 406 0xE000 0x0 0x0 0x2 &ipic 21 0x8
403 0xE000 0x0 0x 407 0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
404 interrupt-parent = <&ipic>; 408 interrupt-parent = <&ipic>;
405 interrupts = <66 0x8>; 409 interrupts = <66 0x8>;
406 bus-range = <0 0>; 410 bus-range = <0 0>;
407 ranges = <0x02000000 0x0 0x900 411 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
408 0x42000000 0x0 0x800 412 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
409 0x01000000 0x0 0x000 413 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
410 sleep = <&pmc 0x00010000>; 414 sleep = <&pmc 0x00010000>;
411 clock-frequency = <66666666>; 415 clock-frequency = <66666666>;
412 #interrupt-cells = <1>; 416 #interrupt-cells = <1>;
413 #size-cells = <2>; 417 #size-cells = <2>;
414 #address-cells = <3>; 418 #address-cells = <3>;
415 reg = <0xe0008500 0x100 419 reg = <0xe0008500 0x100 /* internal registers */
416 0xe0008300 0x8>; 420 0xe0008300 0x8>; /* config space access registers */
417 compatible = "fsl,mpc8349-pci" 421 compatible = "fsl,mpc8349-pci";
418 device_type = "pci"; 422 device_type = "pci";
419 }; 423 };
420 424
421 pci1: pcie@e0009000 { 425 pci1: pcie@e0009000 {
422 #address-cells = <3>; 426 #address-cells = <3>;
423 #size-cells = <2>; 427 #size-cells = <2>;
424 #interrupt-cells = <1>; 428 #interrupt-cells = <1>;
425 device_type = "pci"; 429 device_type = "pci";
426 compatible = "fsl,mpc8377-pcie 430 compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
427 reg = <0xe0009000 0x00001000>; 431 reg = <0xe0009000 0x00001000>;
428 ranges = <0x02000000 0 0xa8000 432 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
429 0x01000000 0 0x00000 433 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
430 bus-range = <0 255>; 434 bus-range = <0 255>;
431 interrupt-map-mask = <0xf800 0 435 interrupt-map-mask = <0xf800 0 0 7>;
432 interrupt-map = <0 0 0 1 &ipic 436 interrupt-map = <0 0 0 1 &ipic 1 8
433 0 0 0 2 &ipic 437 0 0 0 2 &ipic 1 8
434 0 0 0 3 &ipic 438 0 0 0 3 &ipic 1 8
435 0 0 0 4 &ipic 439 0 0 0 4 &ipic 1 8>;
436 sleep = <&pmc 0x00300000>; 440 sleep = <&pmc 0x00300000>;
437 clock-frequency = <0>; 441 clock-frequency = <0>;
438 442
439 pcie@0 { 443 pcie@0 {
440 #address-cells = <3>; 444 #address-cells = <3>;
441 #size-cells = <2>; 445 #size-cells = <2>;
442 device_type = "pci"; 446 device_type = "pci";
443 reg = <0 0 0 0 0>; 447 reg = <0 0 0 0 0>;
444 ranges = <0x02000000 0 448 ranges = <0x02000000 0 0xa8000000
445 0x02000000 0 449 0x02000000 0 0xa8000000
446 0 0x10000000 450 0 0x10000000
447 0x01000000 0 451 0x01000000 0 0x00000000
448 0x01000000 0 452 0x01000000 0 0x00000000
449 0 0x00800000 453 0 0x00800000>;
450 }; 454 };
451 }; 455 };
452 456
453 pci2: pcie@e000a000 { 457 pci2: pcie@e000a000 {
454 #address-cells = <3>; 458 #address-cells = <3>;
455 #size-cells = <2>; 459 #size-cells = <2>;
456 #interrupt-cells = <1>; 460 #interrupt-cells = <1>;
457 device_type = "pci"; 461 device_type = "pci";
458 compatible = "fsl,mpc8377-pcie 462 compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
459 reg = <0xe000a000 0x00001000>; 463 reg = <0xe000a000 0x00001000>;
460 ranges = <0x02000000 0 0xc8000 464 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
461 0x01000000 0 0x00000 465 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
462 bus-range = <0 255>; 466 bus-range = <0 255>;
463 interrupt-map-mask = <0xf800 0 467 interrupt-map-mask = <0xf800 0 0 7>;
464 interrupt-map = <0 0 0 1 &ipic 468 interrupt-map = <0 0 0 1 &ipic 2 8
465 0 0 0 2 &ipic 469 0 0 0 2 &ipic 2 8
466 0 0 0 3 &ipic 470 0 0 0 3 &ipic 2 8
467 0 0 0 4 &ipic 471 0 0 0 4 &ipic 2 8>;
468 sleep = <&pmc 0x000c0000>; 472 sleep = <&pmc 0x000c0000>;
469 clock-frequency = <0>; 473 clock-frequency = <0>;
470 474
471 pcie@0 { 475 pcie@0 {
472 #address-cells = <3>; 476 #address-cells = <3>;
473 #size-cells = <2>; 477 #size-cells = <2>;
474 device_type = "pci"; 478 device_type = "pci";
475 reg = <0 0 0 0 0>; 479 reg = <0 0 0 0 0>;
476 ranges = <0x02000000 0 480 ranges = <0x02000000 0 0xc8000000
477 0x02000000 0 481 0x02000000 0 0xc8000000
478 0 0x10000000 482 0 0x10000000
479 0x01000000 0 483 0x01000000 0 0x00000000
480 0x01000000 0 484 0x01000000 0 0x00000000
481 0 0x00800000 485 0 0x00800000>;
482 }; 486 };
483 }; 487 };
484 488
485 leds { 489 leds {
486 compatible = "gpio-leds"; 490 compatible = "gpio-leds";
487 491
488 pwr { 492 pwr {
489 gpios = <&mcu_pio 0 0> 493 gpios = <&mcu_pio 0 0>;
490 default-state = "on"; 494 default-state = "on";
491 }; 495 };
492 496
493 hdd { 497 hdd {
494 gpios = <&mcu_pio 1 0> 498 gpios = <&mcu_pio 1 0>;
495 linux,default-trigger 499 linux,default-trigger = "disk-activity";
496 }; 500 };
497 }; 501 };
498 }; 502 };
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