1 // SPDX-License-Identifier: GPL-2.0-or-later <<
2 /* 1 /*
3 * MPC8377E WLAN Device Tree Source 2 * MPC8377E WLAN Device Tree Source
4 * 3 *
5 * Copyright 2007-2009 Freescale Semiconductor 4 * Copyright 2007-2009 Freescale Semiconductor Inc.
6 * Copyright 2009 MontaVista Software, Inc. 5 * Copyright 2009 MontaVista Software, Inc.
>> 6 *
>> 7 * This program is free software; you can redistribute it and/or modify it
>> 8 * under the terms of the GNU General Public License as published by the
>> 9 * Free Software Foundation; either version 2 of the License, or (at your
>> 10 * option) any later version.
7 */ 11 */
8 12
9 /dts-v1/; 13 /dts-v1/;
10 14
11 / { 15 / {
12 compatible = "fsl,mpc8377wlan"; 16 compatible = "fsl,mpc8377wlan";
13 #address-cells = <1>; 17 #address-cells = <1>;
14 #size-cells = <1>; 18 #size-cells = <1>;
15 19
16 aliases { 20 aliases {
17 ethernet0 = &enet0; 21 ethernet0 = &enet0;
18 ethernet1 = &enet1; 22 ethernet1 = &enet1;
19 serial0 = &serial0; 23 serial0 = &serial0;
20 serial1 = &serial1; 24 serial1 = &serial1;
21 pci0 = &pci0; 25 pci0 = &pci0;
22 pci1 = &pci1; 26 pci1 = &pci1;
23 pci2 = &pci2; 27 pci2 = &pci2;
24 }; 28 };
25 29
26 cpus { 30 cpus {
27 #address-cells = <1>; 31 #address-cells = <1>;
28 #size-cells = <0>; 32 #size-cells = <0>;
29 33
30 PowerPC,8377@0 { 34 PowerPC,8377@0 {
31 device_type = "cpu"; 35 device_type = "cpu";
32 reg = <0x0>; 36 reg = <0x0>;
33 d-cache-line-size = <3 37 d-cache-line-size = <32>;
34 i-cache-line-size = <3 38 i-cache-line-size = <32>;
35 d-cache-size = <32768> 39 d-cache-size = <32768>;
36 i-cache-size = <32768> 40 i-cache-size = <32768>;
37 timebase-frequency = < 41 timebase-frequency = <0>;
38 bus-frequency = <0>; 42 bus-frequency = <0>;
39 clock-frequency = <0>; 43 clock-frequency = <0>;
40 }; 44 };
41 }; 45 };
42 46
43 memory { 47 memory {
44 device_type = "memory"; 48 device_type = "memory";
45 reg = <0x00000000 0x20000000>; 49 reg = <0x00000000 0x20000000>; // 512MB at 0
46 }; 50 };
47 51
48 localbus@e0005000 { 52 localbus@e0005000 {
49 #address-cells = <2>; 53 #address-cells = <2>;
50 #size-cells = <1>; 54 #size-cells = <1>;
51 compatible = "fsl,mpc8377-elbc 55 compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
52 reg = <0xe0005000 0x1000>; 56 reg = <0xe0005000 0x1000>;
53 interrupts = <77 0x8>; 57 interrupts = <77 0x8>;
54 interrupt-parent = <&ipic>; 58 interrupt-parent = <&ipic>;
55 ranges = <0x0 0x0 0xfc000000 0 59 ranges = <0x0 0x0 0xfc000000 0x04000000>;
56 60
57 flash@0,0 { 61 flash@0,0 {
58 #address-cells = <1>; 62 #address-cells = <1>;
59 #size-cells = <1>; 63 #size-cells = <1>;
60 compatible = "cfi-flas 64 compatible = "cfi-flash";
61 reg = <0x0 0x0 0x40000 65 reg = <0x0 0x0 0x4000000>;
62 bank-width = <2>; 66 bank-width = <2>;
63 device-width = <1>; 67 device-width = <1>;
64 68
65 partition@0 { 69 partition@0 {
66 reg = <0 0x800 70 reg = <0 0x80000>;
67 label = "u-boo 71 label = "u-boot";
68 read-only; 72 read-only;
69 }; 73 };
70 74
71 partition@a0000 { 75 partition@a0000 {
72 reg = <0xa0000 76 reg = <0xa0000 0x300000>;
73 label = "kerne 77 label = "kernel";
74 }; 78 };
75 79
76 partition@3a0000 { 80 partition@3a0000 {
77 reg = <0x3a000 81 reg = <0x3a0000 0x3c60000>;
78 label = "rootf 82 label = "rootfs";
79 }; 83 };
80 }; 84 };
81 }; 85 };
82 86
83 immr@e0000000 { 87 immr@e0000000 {
84 #address-cells = <1>; 88 #address-cells = <1>;
85 #size-cells = <1>; 89 #size-cells = <1>;
86 device_type = "soc"; 90 device_type = "soc";
87 compatible = "simple-bus"; 91 compatible = "simple-bus";
88 ranges = <0x0 0xe0000000 0x001 92 ranges = <0x0 0xe0000000 0x00100000>;
89 reg = <0xe0000000 0x00000200>; 93 reg = <0xe0000000 0x00000200>;
90 bus-frequency = <0>; 94 bus-frequency = <0>;
91 95
92 wdt@200 { 96 wdt@200 {
93 device_type = "watchdo 97 device_type = "watchdog";
94 compatible = "mpc83xx_ 98 compatible = "mpc83xx_wdt";
95 reg = <0x200 0x100>; 99 reg = <0x200 0x100>;
96 }; 100 };
97 101
98 gpio1: gpio-controller@c00 { 102 gpio1: gpio-controller@c00 {
99 #gpio-cells = <2>; 103 #gpio-cells = <2>;
100 compatible = "fsl,mpc8 104 compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
101 reg = <0xc00 0x100>; 105 reg = <0xc00 0x100>;
102 interrupts = <74 0x8>; 106 interrupts = <74 0x8>;
103 interrupt-parent = <&i 107 interrupt-parent = <&ipic>;
104 gpio-controller; 108 gpio-controller;
105 }; 109 };
106 110
107 gpio2: gpio-controller@d00 { 111 gpio2: gpio-controller@d00 {
108 #gpio-cells = <2>; 112 #gpio-cells = <2>;
109 compatible = "fsl,mpc8 113 compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
110 reg = <0xd00 0x100>; 114 reg = <0xd00 0x100>;
111 interrupts = <75 0x8>; 115 interrupts = <75 0x8>;
112 interrupt-parent = <&i 116 interrupt-parent = <&ipic>;
113 gpio-controller; 117 gpio-controller;
114 }; 118 };
115 119
116 sleep-nexus { 120 sleep-nexus {
117 #address-cells = <1>; 121 #address-cells = <1>;
118 #size-cells = <1>; 122 #size-cells = <1>;
119 compatible = "simple-b 123 compatible = "simple-bus";
120 sleep = <&pmc 0x0c0000 124 sleep = <&pmc 0x0c000000>;
121 ranges; 125 ranges;
122 126
123 i2c@3000 { 127 i2c@3000 {
124 #address-cells 128 #address-cells = <1>;
125 #size-cells = 129 #size-cells = <0>;
126 cell-index = < 130 cell-index = <0>;
127 compatible = " 131 compatible = "fsl-i2c";
128 reg = <0x3000 132 reg = <0x3000 0x100>;
129 interrupts = < 133 interrupts = <14 0x8>;
130 interrupt-pare 134 interrupt-parent = <&ipic>;
131 dfsrr; 135 dfsrr;
132 136
133 at24@50 { 137 at24@50 {
134 compat 138 compatible = "atmel,24c256";
135 reg = 139 reg = <0x50>;
136 }; 140 };
137 141
138 rtc@68 { 142 rtc@68 {
139 compat 143 compatible = "dallas,ds1339";
140 reg = 144 reg = <0x68>;
141 }; 145 };
142 }; 146 };
143 147
144 sdhci@2e000 { 148 sdhci@2e000 {
145 compatible = " 149 compatible = "fsl,mpc8377-esdhc", "fsl,esdhc";
146 reg = <0x2e000 150 reg = <0x2e000 0x1000>;
147 interrupts = < 151 interrupts = <42 0x8>;
148 interrupt-pare 152 interrupt-parent = <&ipic>;
149 sdhci,wp-inver 153 sdhci,wp-inverted;
150 clock-frequenc 154 clock-frequency = <133333333>;
151 }; 155 };
152 }; 156 };
153 157
154 i2c@3100 { 158 i2c@3100 {
155 #address-cells = <1>; 159 #address-cells = <1>;
156 #size-cells = <0>; 160 #size-cells = <0>;
157 cell-index = <1>; 161 cell-index = <1>;
158 compatible = "fsl-i2c" 162 compatible = "fsl-i2c";
159 reg = <0x3100 0x100>; 163 reg = <0x3100 0x100>;
160 interrupts = <15 0x8>; 164 interrupts = <15 0x8>;
161 interrupt-parent = <&i 165 interrupt-parent = <&ipic>;
162 dfsrr; 166 dfsrr;
163 }; 167 };
164 168
165 spi@7000 { 169 spi@7000 {
166 cell-index = <0>; 170 cell-index = <0>;
167 compatible = "fsl,spi" 171 compatible = "fsl,spi";
168 reg = <0x7000 0x1000>; 172 reg = <0x7000 0x1000>;
169 interrupts = <16 0x8>; 173 interrupts = <16 0x8>;
170 interrupt-parent = <&i 174 interrupt-parent = <&ipic>;
171 mode = "cpu"; 175 mode = "cpu";
172 }; 176 };
173 177
174 dma@82a8 { 178 dma@82a8 {
175 #address-cells = <1>; 179 #address-cells = <1>;
176 #size-cells = <1>; 180 #size-cells = <1>;
177 compatible = "fsl,mpc8 181 compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
178 reg = <0x82a8 4>; 182 reg = <0x82a8 4>;
179 ranges = <0 0x8100 0x1 183 ranges = <0 0x8100 0x1a8>;
180 interrupt-parent = <&i 184 interrupt-parent = <&ipic>;
181 interrupts = <71 8>; 185 interrupts = <71 8>;
182 cell-index = <0>; 186 cell-index = <0>;
183 dma-channel@0 { 187 dma-channel@0 {
184 compatible = " 188 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
185 reg = <0 0x80> 189 reg = <0 0x80>;
186 cell-index = < 190 cell-index = <0>;
187 interrupt-pare 191 interrupt-parent = <&ipic>;
188 interrupts = < 192 interrupts = <71 8>;
189 }; 193 };
190 dma-channel@80 { 194 dma-channel@80 {
191 compatible = " 195 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
192 reg = <0x80 0x 196 reg = <0x80 0x80>;
193 cell-index = < 197 cell-index = <1>;
194 interrupt-pare 198 interrupt-parent = <&ipic>;
195 interrupts = < 199 interrupts = <71 8>;
196 }; 200 };
197 dma-channel@100 { 201 dma-channel@100 {
198 compatible = " 202 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
199 reg = <0x100 0 203 reg = <0x100 0x80>;
200 cell-index = < 204 cell-index = <2>;
201 interrupt-pare 205 interrupt-parent = <&ipic>;
202 interrupts = < 206 interrupts = <71 8>;
203 }; 207 };
204 dma-channel@180 { 208 dma-channel@180 {
205 compatible = " 209 compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
206 reg = <0x180 0 210 reg = <0x180 0x28>;
207 cell-index = < 211 cell-index = <3>;
208 interrupt-pare 212 interrupt-parent = <&ipic>;
209 interrupts = < 213 interrupts = <71 8>;
210 }; 214 };
211 }; 215 };
212 216
213 usb@23000 { 217 usb@23000 {
214 compatible = "fsl-usb2 218 compatible = "fsl-usb2-dr";
215 reg = <0x23000 0x1000> 219 reg = <0x23000 0x1000>;
216 #address-cells = <1>; 220 #address-cells = <1>;
217 #size-cells = <0>; 221 #size-cells = <0>;
218 interrupt-parent = <&i 222 interrupt-parent = <&ipic>;
219 interrupts = <38 0x8>; 223 interrupts = <38 0x8>;
220 phy_type = "ulpi"; 224 phy_type = "ulpi";
221 sleep = <&pmc 0x00c000 225 sleep = <&pmc 0x00c00000>;
222 }; 226 };
223 227
224 enet0: ethernet@24000 { 228 enet0: ethernet@24000 {
225 #address-cells = <1>; 229 #address-cells = <1>;
226 #size-cells = <1>; 230 #size-cells = <1>;
227 cell-index = <0>; 231 cell-index = <0>;
228 device_type = "network 232 device_type = "network";
229 model = "eTSEC"; 233 model = "eTSEC";
230 compatible = "gianfar" 234 compatible = "gianfar";
231 reg = <0x24000 0x1000> 235 reg = <0x24000 0x1000>;
232 ranges = <0x0 0x24000 236 ranges = <0x0 0x24000 0x1000>;
233 local-mac-address = [ 237 local-mac-address = [ 00 00 00 00 00 00 ];
234 interrupts = <32 0x8 3 238 interrupts = <32 0x8 33 0x8 34 0x8>;
235 phy-connection-type = 239 phy-connection-type = "mii";
236 interrupt-parent = <&i 240 interrupt-parent = <&ipic>;
237 tbi-handle = <&tbi0>; 241 tbi-handle = <&tbi0>;
238 phy-handle = <&phy2>; 242 phy-handle = <&phy2>;
239 sleep = <&pmc 0xc00000 243 sleep = <&pmc 0xc0000000>;
240 fsl,magic-packet; 244 fsl,magic-packet;
241 245
242 mdio@520 { 246 mdio@520 {
243 #address-cells 247 #address-cells = <1>;
244 #size-cells = 248 #size-cells = <0>;
245 compatible = " 249 compatible = "fsl,gianfar-mdio";
246 reg = <0x520 0 250 reg = <0x520 0x20>;
247 251
248 phy2: ethernet 252 phy2: ethernet-phy@2 {
249 interr 253 interrupt-parent = <&ipic>;
250 interr 254 interrupts = <17 0x8>;
251 reg = 255 reg = <0x2>;
252 }; 256 };
253 257
254 phy3: ethernet 258 phy3: ethernet-phy@3 {
255 interr 259 interrupt-parent = <&ipic>;
256 interr 260 interrupts = <18 0x8>;
257 reg = 261 reg = <0x3>;
258 }; 262 };
259 263
260 tbi0: tbi-phy@ 264 tbi0: tbi-phy@11 {
261 reg = 265 reg = <0x11>;
262 device 266 device_type = "tbi-phy";
263 }; 267 };
264 }; 268 };
265 }; 269 };
266 270
267 enet1: ethernet@25000 { 271 enet1: ethernet@25000 {
268 #address-cells = <1>; 272 #address-cells = <1>;
269 #size-cells = <1>; 273 #size-cells = <1>;
270 cell-index = <1>; 274 cell-index = <1>;
271 device_type = "network 275 device_type = "network";
272 model = "eTSEC"; 276 model = "eTSEC";
273 compatible = "gianfar" 277 compatible = "gianfar";
274 reg = <0x25000 0x1000> 278 reg = <0x25000 0x1000>;
275 ranges = <0x0 0x25000 279 ranges = <0x0 0x25000 0x1000>;
276 local-mac-address = [ 280 local-mac-address = [ 00 00 00 00 00 00 ];
277 interrupts = <35 0x8 3 281 interrupts = <35 0x8 36 0x8 37 0x8>;
278 phy-connection-type = 282 phy-connection-type = "mii";
279 interrupt-parent = <&i 283 interrupt-parent = <&ipic>;
280 phy-handle = <&phy3>; 284 phy-handle = <&phy3>;
281 tbi-handle = <&tbi1>; 285 tbi-handle = <&tbi1>;
282 sleep = <&pmc 0x300000 286 sleep = <&pmc 0x30000000>;
283 fsl,magic-packet; 287 fsl,magic-packet;
284 288
285 mdio@520 { 289 mdio@520 {
286 #address-cells 290 #address-cells = <1>;
287 #size-cells = 291 #size-cells = <0>;
288 compatible = " 292 compatible = "fsl,gianfar-tbi";
289 reg = <0x520 0 293 reg = <0x520 0x20>;
290 294
291 tbi1: tbi-phy@ 295 tbi1: tbi-phy@11 {
292 reg = 296 reg = <0x11>;
293 device 297 device_type = "tbi-phy";
294 }; 298 };
295 }; 299 };
296 }; 300 };
297 301
298 serial0: serial@4500 { 302 serial0: serial@4500 {
299 cell-index = <0>; 303 cell-index = <0>;
300 device_type = "serial" 304 device_type = "serial";
301 compatible = "fsl,ns16 305 compatible = "fsl,ns16550", "ns16550";
302 reg = <0x4500 0x100>; 306 reg = <0x4500 0x100>;
303 clock-frequency = <0>; 307 clock-frequency = <0>;
304 interrupts = <9 0x8>; 308 interrupts = <9 0x8>;
305 interrupt-parent = <&i 309 interrupt-parent = <&ipic>;
306 }; 310 };
307 311
308 serial1: serial@4600 { 312 serial1: serial@4600 {
309 cell-index = <1>; 313 cell-index = <1>;
310 device_type = "serial" 314 device_type = "serial";
311 compatible = "fsl,ns16 315 compatible = "fsl,ns16550", "ns16550";
312 reg = <0x4600 0x100>; 316 reg = <0x4600 0x100>;
313 clock-frequency = <0>; 317 clock-frequency = <0>;
314 interrupts = <10 0x8>; 318 interrupts = <10 0x8>;
315 interrupt-parent = <&i 319 interrupt-parent = <&ipic>;
316 }; 320 };
317 321
318 crypto@30000 { 322 crypto@30000 {
319 compatible = "fsl,sec3 323 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
320 "fsl,sec2 324 "fsl,sec2.1", "fsl,sec2.0";
321 reg = <0x30000 0x10000 325 reg = <0x30000 0x10000>;
322 interrupts = <11 0x8>; 326 interrupts = <11 0x8>;
323 interrupt-parent = <&i 327 interrupt-parent = <&ipic>;
324 fsl,num-channels = <4> 328 fsl,num-channels = <4>;
325 fsl,channel-fifo-len = 329 fsl,channel-fifo-len = <24>;
326 fsl,exec-units-mask = 330 fsl,exec-units-mask = <0x9fe>;
327 fsl,descriptor-types-m 331 fsl,descriptor-types-mask = <0x3ab0ebf>;
328 sleep = <&pmc 0x030000 332 sleep = <&pmc 0x03000000>;
329 }; 333 };
330 334
331 sata@18000 { 335 sata@18000 {
332 compatible = "fsl,mpc8 336 compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
333 reg = <0x18000 0x1000> 337 reg = <0x18000 0x1000>;
334 interrupts = <44 0x8>; 338 interrupts = <44 0x8>;
335 interrupt-parent = <&i 339 interrupt-parent = <&ipic>;
336 sleep = <&pmc 0x000000 340 sleep = <&pmc 0x000000c0>;
337 }; 341 };
338 342
339 sata@19000 { 343 sata@19000 {
340 compatible = "fsl,mpc8 344 compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
341 reg = <0x19000 0x1000> 345 reg = <0x19000 0x1000>;
342 interrupts = <45 0x8>; 346 interrupts = <45 0x8>;
343 interrupt-parent = <&i 347 interrupt-parent = <&ipic>;
344 sleep = <&pmc 0x000000 348 sleep = <&pmc 0x00000030>;
345 }; 349 };
346 350
347 /* IPIC 351 /* IPIC
348 * interrupts cell = <intr #, 352 * interrupts cell = <intr #, sense>
349 * sense values match linux IO 353 * sense values match linux IORESOURCE_IRQ_* defines:
350 * sense == 8: Level, low asse 354 * sense == 8: Level, low assertion
351 * sense == 2: Edge, high-to-l 355 * sense == 2: Edge, high-to-low change
352 */ 356 */
353 ipic: interrupt-controller@700 357 ipic: interrupt-controller@700 {
354 compatible = "fsl,ipic 358 compatible = "fsl,ipic";
355 interrupt-controller; 359 interrupt-controller;
356 #address-cells = <0>; 360 #address-cells = <0>;
357 #interrupt-cells = <2> 361 #interrupt-cells = <2>;
358 reg = <0x700 0x100>; 362 reg = <0x700 0x100>;
359 }; 363 };
360 364
361 pmc: power@b00 { 365 pmc: power@b00 {
362 compatible = "fsl,mpc8 366 compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc";
363 reg = <0xb00 0x100 0xa 367 reg = <0xb00 0x100 0xa00 0x100>;
364 interrupts = <80 0x8>; 368 interrupts = <80 0x8>;
365 interrupt-parent = <&i 369 interrupt-parent = <&ipic>;
366 }; 370 };
367 }; 371 };
368 372
369 pci0: pci@e0008500 { 373 pci0: pci@e0008500 {
370 interrupt-map-mask = <0xf800 0 374 interrupt-map-mask = <0xf800 0 0 7>;
371 interrupt-map = < 375 interrupt-map = <
372 /* IRQ5 = 21 = 376 /* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
373 377
374 /* IDSEL AD14 378 /* IDSEL AD14 IRQ6 inta */
375 0x7000 0x0 0x 379 0x7000 0x0 0x0 0x1 &ipic 22 0x8
376 380
377 /* IDSEL AD15 381 /* IDSEL AD15 IRQ5 inta */
378 0x7800 0x0 0x 382 0x7800 0x0 0x0 0x1 &ipic 21 0x8>;
379 interrupt-parent = <&ipic>; 383 interrupt-parent = <&ipic>;
380 interrupts = <66 0x8>; 384 interrupts = <66 0x8>;
381 bus-range = <0 0>; 385 bus-range = <0 0>;
382 ranges = <0x02000000 0x0 0x900 386 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
383 0x42000000 0x0 0x800 387 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
384 0x01000000 0x0 0x000 388 0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
385 sleep = <&pmc 0x00010000>; 389 sleep = <&pmc 0x00010000>;
386 clock-frequency = <66666666>; 390 clock-frequency = <66666666>;
387 #interrupt-cells = <1>; 391 #interrupt-cells = <1>;
388 #size-cells = <2>; 392 #size-cells = <2>;
389 #address-cells = <3>; 393 #address-cells = <3>;
390 reg = <0xe0008500 0x100 394 reg = <0xe0008500 0x100 /* internal registers */
391 0xe0008300 0x8>; 395 0xe0008300 0x8>; /* config space access registers */
392 compatible = "fsl,mpc8349-pci" 396 compatible = "fsl,mpc8349-pci";
393 device_type = "pci"; 397 device_type = "pci";
394 }; 398 };
395 399
396 pci1: pcie@e0009000 { 400 pci1: pcie@e0009000 {
397 #address-cells = <3>; 401 #address-cells = <3>;
398 #size-cells = <2>; 402 #size-cells = <2>;
399 #interrupt-cells = <1>; 403 #interrupt-cells = <1>;
400 device_type = "pci"; 404 device_type = "pci";
401 compatible = "fsl,mpc8377-pcie 405 compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
402 reg = <0xe0009000 0x00001000>; 406 reg = <0xe0009000 0x00001000>;
403 ranges = <0x02000000 0 0xa8000 407 ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
404 0x01000000 0 0x00000 408 0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
405 bus-range = <0 255>; 409 bus-range = <0 255>;
406 interrupt-map-mask = <0xf800 0 410 interrupt-map-mask = <0xf800 0 0 7>;
407 interrupt-map = <0 0 0 1 &ipic 411 interrupt-map = <0 0 0 1 &ipic 1 8
408 0 0 0 2 &ipic 412 0 0 0 2 &ipic 1 8
409 0 0 0 3 &ipic 413 0 0 0 3 &ipic 1 8
410 0 0 0 4 &ipic 414 0 0 0 4 &ipic 1 8>;
411 sleep = <&pmc 0x00300000>; 415 sleep = <&pmc 0x00300000>;
412 clock-frequency = <0>; 416 clock-frequency = <0>;
413 417
414 pcie@0 { 418 pcie@0 {
415 #address-cells = <3>; 419 #address-cells = <3>;
416 #size-cells = <2>; 420 #size-cells = <2>;
417 device_type = "pci"; 421 device_type = "pci";
418 reg = <0 0 0 0 0>; 422 reg = <0 0 0 0 0>;
419 ranges = <0x02000000 0 423 ranges = <0x02000000 0 0xa8000000
420 0x02000000 0 424 0x02000000 0 0xa8000000
421 0 0x10000000 425 0 0x10000000
422 0x01000000 0 426 0x01000000 0 0x00000000
423 0x01000000 0 427 0x01000000 0 0x00000000
424 0 0x00800000 428 0 0x00800000>;
425 }; 429 };
426 }; 430 };
427 431
428 pci2: pcie@e000a000 { 432 pci2: pcie@e000a000 {
429 #address-cells = <3>; 433 #address-cells = <3>;
430 #size-cells = <2>; 434 #size-cells = <2>;
431 #interrupt-cells = <1>; 435 #interrupt-cells = <1>;
432 device_type = "pci"; 436 device_type = "pci";
433 compatible = "fsl,mpc8377-pcie 437 compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
434 reg = <0xe000a000 0x00001000>; 438 reg = <0xe000a000 0x00001000>;
435 ranges = <0x02000000 0 0xc8000 439 ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
436 0x01000000 0 0x00000 440 0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
437 bus-range = <0 255>; 441 bus-range = <0 255>;
438 interrupt-map-mask = <0xf800 0 442 interrupt-map-mask = <0xf800 0 0 7>;
439 interrupt-map = <0 0 0 1 &ipic 443 interrupt-map = <0 0 0 1 &ipic 2 8
440 0 0 0 2 &ipic 444 0 0 0 2 &ipic 2 8
441 0 0 0 3 &ipic 445 0 0 0 3 &ipic 2 8
442 0 0 0 4 &ipic 446 0 0 0 4 &ipic 2 8>;
443 sleep = <&pmc 0x000c0000>; 447 sleep = <&pmc 0x000c0000>;
444 clock-frequency = <0>; 448 clock-frequency = <0>;
445 449
446 pcie@0 { 450 pcie@0 {
447 #address-cells = <3>; 451 #address-cells = <3>;
448 #size-cells = <2>; 452 #size-cells = <2>;
449 device_type = "pci"; 453 device_type = "pci";
450 reg = <0 0 0 0 0>; 454 reg = <0 0 0 0 0>;
451 ranges = <0x02000000 0 455 ranges = <0x02000000 0 0xc8000000
452 0x02000000 0 456 0x02000000 0 0xc8000000
453 0 0x10000000 457 0 0x10000000
454 0x01000000 0 458 0x01000000 0 0x00000000
455 0x01000000 0 459 0x01000000 0 0x00000000
456 0 0x00800000 460 0 0x00800000>;
457 }; 461 };
458 }; 462 };
459 }; 463 };
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