1 // SPDX-License-Identifier: GPL-2.0-or-later 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* 2 /*
3 * phyCORE-MPC5200B-IO (pcm032) board Device T 3 * phyCORE-MPC5200B-IO (pcm032) board Device Tree Source
4 * 4 *
5 * Copyright (C) 2006-2009 Pengutronix 5 * Copyright (C) 2006-2009 Pengutronix
6 * Sascha Hauer, Juergen Beisert, Wolfram Sang< !! 6 * Sascha Hauer <s.hauer@pengutronix.de>
>> 7 * Juergen Beisert <j.beisert@pengutronix.de>
>> 8 * Wolfram Sang <w.sang@pengutronix.de>
7 */ 9 */
8 10
9 /include/ "mpc5200b.dtsi" 11 /include/ "mpc5200b.dtsi"
10 12
11 &gpt0 { fsl,has-wdt; }; 13 &gpt0 { fsl,has-wdt; };
12 &gpt2 { gpio-controller; }; 14 &gpt2 { gpio-controller; };
13 &gpt3 { gpio-controller; }; 15 &gpt3 { gpio-controller; };
14 &gpt4 { gpio-controller; }; 16 &gpt4 { gpio-controller; };
15 &gpt5 { gpio-controller; }; 17 &gpt5 { gpio-controller; };
16 &gpt6 { gpio-controller; }; 18 &gpt6 { gpio-controller; };
17 &gpt7 { gpio-controller; }; 19 &gpt7 { gpio-controller; };
18 20
19 / { 21 / {
20 model = "phytec,pcm032"; 22 model = "phytec,pcm032";
21 compatible = "phytec,pcm032"; 23 compatible = "phytec,pcm032";
22 24
23 memory@0 { !! 25 memory {
24 reg = <0x00000000 0x08000000>; 26 reg = <0x00000000 0x08000000>; // 128MB
25 }; 27 };
26 28
27 soc5200@f0000000 { 29 soc5200@f0000000 {
28 psc@2000 { /* PSC1 is ac9 30 psc@2000 { /* PSC1 is ac97 */
29 compatible = "fsl,mpc5 31 compatible = "fsl,mpc5200b-psc-ac97","fsl,mpc5200-psc-ac97";
30 cell-index = <0>; 32 cell-index = <0>;
31 }; 33 };
32 34
33 /* PSC2 port is used by CAN1/2 35 /* PSC2 port is used by CAN1/2 */
34 psc@2200 { 36 psc@2200 {
35 status = "disabled"; 37 status = "disabled";
36 }; 38 };
37 39
38 psc@2400 { /* PSC3 in UART mod 40 psc@2400 { /* PSC3 in UART mode */
39 compatible = "fsl,mpc5 41 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
40 }; 42 };
41 43
42 /* PSC4 is ??? */ 44 /* PSC4 is ??? */
43 psc@2600 { 45 psc@2600 {
44 status = "disabled"; 46 status = "disabled";
45 }; 47 };
46 48
47 /* PSC5 is ??? */ 49 /* PSC5 is ??? */
48 psc@2800 { 50 psc@2800 {
49 status = "disabled"; 51 status = "disabled";
50 }; 52 };
51 53
52 psc@2c00 { /* PSC6 in UART mod 54 psc@2c00 { /* PSC6 in UART mode */
53 compatible = "fsl,mpc5 55 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
54 }; 56 };
55 57
56 ethernet@3000 { 58 ethernet@3000 {
57 phy-handle = <&phy0>; 59 phy-handle = <&phy0>;
58 }; 60 };
59 61
60 mdio@3000 { 62 mdio@3000 {
61 phy0: ethernet-phy@0 { 63 phy0: ethernet-phy@0 {
62 reg = <0>; 64 reg = <0>;
63 }; 65 };
64 }; 66 };
65 67
66 i2c@3d40 { 68 i2c@3d40 {
67 rtc@51 { 69 rtc@51 {
68 compatible = " 70 compatible = "nxp,pcf8563";
69 reg = <0x51>; 71 reg = <0x51>;
70 }; 72 };
71 eeprom@52 { 73 eeprom@52 {
72 compatible = " 74 compatible = "catalyst,24c32", "atmel,24c32";
73 reg = <0x52>; 75 reg = <0x52>;
74 pagesize = <32 76 pagesize = <32>;
75 }; 77 };
76 }; 78 };
77 }; 79 };
78 80
79 pci@f0000d00 { 81 pci@f0000d00 {
80 interrupt-map-mask = <0xf800 0 82 interrupt-map-mask = <0xf800 0 0 7>;
81 interrupt-map = <0xc000 0 0 1 83 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
82 0xc000 0 0 2 84 0xc000 0 0 2 &mpc5200_pic 1 1 3
83 0xc000 0 0 3 85 0xc000 0 0 3 &mpc5200_pic 1 2 3
84 0xc000 0 0 4 86 0xc000 0 0 4 &mpc5200_pic 1 3 3
85 87
86 0xc800 0 0 1 88 0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
87 0xc800 0 0 2 89 0xc800 0 0 2 &mpc5200_pic 1 2 3
88 0xc800 0 0 3 90 0xc800 0 0 3 &mpc5200_pic 1 3 3
89 0xc800 0 0 4 91 0xc800 0 0 4 &mpc5200_pic 0 0 3>;
90 ranges = <0x42000000 0 0x80000 !! 92 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
91 <0x02000000 0 0xa0000 !! 93 0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
92 <0x01000000 0 0x00000 !! 94 0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
93 }; 95 };
94 96
95 localbus { 97 localbus {
96 ranges = <0 0 0xfe000000 0x020 98 ranges = <0 0 0xfe000000 0x02000000
97 1 0 0xfc000000 0x020 99 1 0 0xfc000000 0x02000000
98 2 0 0xfbe00000 0x002 100 2 0 0xfbe00000 0x00200000
99 3 0 0xf9e00000 0x020 101 3 0 0xf9e00000 0x02000000
100 4 0 0xf7e00000 0x020 102 4 0 0xf7e00000 0x02000000
101 5 0 0xe6000000 0x020 103 5 0 0xe6000000 0x02000000
102 6 0 0xe8000000 0x020 104 6 0 0xe8000000 0x02000000
103 7 0 0xea000000 0x020 105 7 0 0xea000000 0x02000000>;
104 106
105 flash@0,0 { 107 flash@0,0 {
106 compatible = "cfi-flas 108 compatible = "cfi-flash";
107 reg = <0 0 0x02000000> 109 reg = <0 0 0x02000000>;
108 bank-width = <4>; 110 bank-width = <4>;
109 #size-cells = <1>; 111 #size-cells = <1>;
110 #address-cells = <1>; 112 #address-cells = <1>;
111 113
112 partition@0 { 114 partition@0 {
113 label = "uboot 115 label = "ubootl";
114 reg = <0x00000 116 reg = <0x00000000 0x00040000>;
115 }; 117 };
116 partition@40000 { 118 partition@40000 {
117 label = "kerne 119 label = "kernel";
118 reg = <0x00040 120 reg = <0x00040000 0x001c0000>;
119 }; 121 };
120 partition@200000 { 122 partition@200000 {
121 label = "jffs2 123 label = "jffs2";
122 reg = <0x00200 124 reg = <0x00200000 0x01d00000>;
123 }; 125 };
124 partition@1f00000 { 126 partition@1f00000 {
125 label = "uboot 127 label = "uboot";
126 reg = <0x01f00 128 reg = <0x01f00000 0x00040000>;
127 }; 129 };
128 partition@1f40000 { 130 partition@1f40000 {
129 label = "env"; 131 label = "env";
130 reg = <0x01f40 132 reg = <0x01f40000 0x00040000>;
131 }; 133 };
132 partition@1f80000 { 134 partition@1f80000 {
133 label = "oftre 135 label = "oftree";
134 reg = <0x01f80 136 reg = <0x01f80000 0x00040000>;
135 }; 137 };
136 partition@1fc0000 { 138 partition@1fc0000 {
137 label = "space 139 label = "space";
138 reg = <0x01fc0 140 reg = <0x01fc0000 0x00040000>;
139 }; 141 };
140 }; 142 };
141 143
142 sram@2,0 { 144 sram@2,0 {
143 compatible = "mtd-ram" 145 compatible = "mtd-ram";
144 reg = <2 0 0x00200000> 146 reg = <2 0 0x00200000>;
145 bank-width = <2>; 147 bank-width = <2>;
146 }; 148 };
147 149
148 /* 150 /*
149 * example snippets for FPGA 151 * example snippets for FPGA
150 * 152 *
151 * fpga@3,0 { 153 * fpga@3,0 {
152 * compatible = "fpga_dr 154 * compatible = "fpga_driver";
153 * reg = <3 0 0x02000000 155 * reg = <3 0 0x02000000>;
154 * bank-width = <4>; 156 * bank-width = <4>;
155 * }; 157 * };
156 * 158 *
157 * fpga@4,0 { 159 * fpga@4,0 {
158 * compatible = "fpga_dr 160 * compatible = "fpga_driver";
159 * reg = <4 0 0x02000000 161 * reg = <4 0 0x02000000>;
160 * bank-width = <4>; 162 * bank-width = <4>;
161 * }; 163 * };
162 */ 164 */
163 165
164 /* 166 /*
165 * example snippets for free c 167 * example snippets for free chipselects
166 * 168 *
167 * device@5,0 { 169 * device@5,0 {
168 * compatible = "custom_ 170 * compatible = "custom_driver";
169 * reg = <5 0 0x02000000 171 * reg = <5 0 0x02000000>;
170 * }; 172 * };
171 * 173 *
172 * device@6,0 { 174 * device@6,0 {
173 * compatible = "custom_ 175 * compatible = "custom_driver";
174 * reg = <6 0 0x02000000 176 * reg = <6 0 0x02000000>;
175 * }; 177 * };
176 * 178 *
177 * device@7,0 { 179 * device@7,0 {
178 * compatible = "custom_ 180 * compatible = "custom_driver";
179 * reg = <7 0 0x02000000 181 * reg = <7 0 0x02000000>;
180 * }; 182 * };
181 */ 183 */
182 }; 184 };
183 }; 185 };
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