1 // SPDX-License-Identifier: GPL-2.0-only << 2 /* 1 /* 3 * PS3 Game Console device tree. 2 * PS3 Game Console device tree. 4 * 3 * 5 * Copyright (C) 2007 Sony Computer Entertain 4 * Copyright (C) 2007 Sony Computer Entertainment Inc. 6 * Copyright 2007 Sony Corp. 5 * Copyright 2007 Sony Corp. >> 6 * >> 7 * This program is free software; you can redistribute it and/or modify >> 8 * it under the terms of the GNU General Public License as published by >> 9 * the Free Software Foundation; version 2 of the License. >> 10 * >> 11 * This program is distributed in the hope that it will be useful, >> 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of >> 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> 14 * GNU General Public License for more details. >> 15 * >> 16 * You should have received a copy of the GNU General Public License >> 17 * along with this program; if not, write to the Free Software >> 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 7 */ 19 */ 8 20 9 /dts-v1/; 21 /dts-v1/; 10 22 11 / { 23 / { 12 model = "SonyPS3"; 24 model = "SonyPS3"; 13 compatible = "sony,ps3"; 25 compatible = "sony,ps3"; 14 #size-cells = <2>; 26 #size-cells = <2>; 15 #address-cells = <2>; 27 #address-cells = <2>; 16 28 17 chosen { 29 chosen { 18 }; 30 }; 19 31 20 /* 32 /* 21 * We'll get the size of the bootmem b 33 * We'll get the size of the bootmem block from lv1 after startup, 22 * so we'll put a null entry here. 34 * so we'll put a null entry here. 23 */ 35 */ 24 36 25 memory { 37 memory { 26 device_type = "memory"; 38 device_type = "memory"; 27 reg = <0x00000000 0x00000000 0 39 reg = <0x00000000 0x00000000 0x00000000 0x00000000>; 28 }; 40 }; 29 41 30 /* 42 /* 31 * The boot cpu is always zero for PS3 43 * The boot cpu is always zero for PS3. 32 * 44 * 33 * dtc expects a clock-frequency and t 45 * dtc expects a clock-frequency and timebase-frequency entries, so 34 * we'll put a null entries here. The 46 * we'll put a null entries here. These will be initialized after 35 * startup with data from lv1. 47 * startup with data from lv1. 36 * 48 * 37 * Seems the only way currently to ind 49 * Seems the only way currently to indicate a processor has multiple 38 * threads is with an ibm,ppc-interrup 50 * threads is with an ibm,ppc-interrupt-server#s entry. We'll put one 39 * here so we can bring up both of our 51 * here so we can bring up both of ours. See smp_setup_cpu_maps(). 40 */ 52 */ 41 53 42 cpus { 54 cpus { 43 #size-cells = <0>; 55 #size-cells = <0>; 44 #address-cells = <1>; 56 #address-cells = <1>; 45 57 46 cpu@0 { 58 cpu@0 { 47 device_type = "cpu"; 59 device_type = "cpu"; 48 reg = <0x00000000>; 60 reg = <0x00000000>; 49 ibm,ppc-interrupt-serv 61 ibm,ppc-interrupt-server#s = <0x0 0x1>; 50 clock-frequency = <0>; 62 clock-frequency = <0>; 51 timebase-frequency = < 63 timebase-frequency = <0>; 52 i-cache-size = <32768> 64 i-cache-size = <32768>; 53 d-cache-size = <32768> 65 d-cache-size = <32768>; 54 i-cache-line-size = <1 66 i-cache-line-size = <128>; 55 d-cache-line-size = <1 67 d-cache-line-size = <128>; 56 }; 68 }; 57 }; 69 }; 58 }; 70 };
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