1 // SPDX-License-Identifier: GPL-2.0-or-later <<
2 /* 1 /*
3 * Device Tree Source for the Socrates board ( 2 * Device Tree Source for the Socrates board (MPC8544).
4 * 3 *
5 * Copyright (c) 2008 Emcraft Systems. 4 * Copyright (c) 2008 Emcraft Systems.
6 * Sergei Poselenov, <sposelenov@emcraft.com> 5 * Sergei Poselenov, <sposelenov@emcraft.com>
>> 6 *
>> 7 * This program is free software; you can redistribute it and/or modify it
>> 8 * under the terms of the GNU General Public License as published by the
>> 9 * Free Software Foundation; either version 2 of the License, or (at your
>> 10 * option) any later version.
7 */ 11 */
8 12
9 /dts-v1/; 13 /dts-v1/;
10 14
11 / { 15 / {
12 model = "abb,socrates"; 16 model = "abb,socrates";
13 compatible = "abb,socrates"; 17 compatible = "abb,socrates";
14 #address-cells = <1>; 18 #address-cells = <1>;
15 #size-cells = <1>; 19 #size-cells = <1>;
16 20
17 aliases { 21 aliases {
18 ethernet0 = &enet0; 22 ethernet0 = &enet0;
19 ethernet1 = &enet1; 23 ethernet1 = &enet1;
20 serial0 = &serial0; 24 serial0 = &serial0;
21 serial1 = &serial1; 25 serial1 = &serial1;
22 pci0 = &pci0; 26 pci0 = &pci0;
23 }; 27 };
24 28
25 cpus { 29 cpus {
26 #address-cells = <1>; 30 #address-cells = <1>;
27 #size-cells = <0>; 31 #size-cells = <0>;
28 32
29 PowerPC,8544@0 { 33 PowerPC,8544@0 {
30 device_type = "cpu"; 34 device_type = "cpu";
31 reg = <0>; 35 reg = <0>;
32 d-cache-line-size = <3 36 d-cache-line-size = <32>;
33 i-cache-line-size = <3 37 i-cache-line-size = <32>;
34 d-cache-size = <0x8000 38 d-cache-size = <0x8000>; // L1, 32K
35 i-cache-size = <0x8000 39 i-cache-size = <0x8000>; // L1, 32K
36 timebase-frequency = < 40 timebase-frequency = <0>;
37 bus-frequency = <0>; 41 bus-frequency = <0>;
38 clock-frequency = <0>; 42 clock-frequency = <0>;
39 next-level-cache = <&L 43 next-level-cache = <&L2>;
40 }; 44 };
41 }; 45 };
42 46
43 memory { 47 memory {
44 device_type = "memory"; 48 device_type = "memory";
45 reg = <0x00000000 0x00000000>; 49 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
46 }; 50 };
47 51
48 soc8544@e0000000 { 52 soc8544@e0000000 {
49 #address-cells = <1>; 53 #address-cells = <1>;
50 #size-cells = <1>; 54 #size-cells = <1>;
51 device_type = "soc"; 55 device_type = "soc";
52 56
53 ranges = <0x00000000 0xe000000 57 ranges = <0x00000000 0xe0000000 0x00100000>;
54 bus-frequency = <0>; 58 bus-frequency = <0>; // Filled in by U-Boot
55 compatible = "fsl,mpc8544-immr 59 compatible = "fsl,mpc8544-immr", "simple-bus";
56 60
57 ecm-law@0 { 61 ecm-law@0 {
58 compatible = "fsl,ecm- 62 compatible = "fsl,ecm-law";
59 reg = <0x0 0x1000>; 63 reg = <0x0 0x1000>;
60 fsl,num-laws = <10>; 64 fsl,num-laws = <10>;
61 }; 65 };
62 66
63 ecm@1000 { 67 ecm@1000 {
64 compatible = "fsl,mpc8 68 compatible = "fsl,mpc8544-ecm", "fsl,ecm";
65 reg = <0x1000 0x1000>; 69 reg = <0x1000 0x1000>;
66 interrupts = <17 2>; 70 interrupts = <17 2>;
67 interrupt-parent = <&m 71 interrupt-parent = <&mpic>;
68 }; 72 };
69 73
70 memory-controller@2000 { 74 memory-controller@2000 {
71 compatible = "fsl,mpc8 75 compatible = "fsl,mpc8544-memory-controller";
72 reg = <0x2000 0x1000>; 76 reg = <0x2000 0x1000>;
73 interrupt-parent = <&m 77 interrupt-parent = <&mpic>;
74 interrupts = <18 2>; 78 interrupts = <18 2>;
75 }; 79 };
76 80
77 L2: l2-cache-controller@20000 81 L2: l2-cache-controller@20000 {
78 compatible = "fsl,mpc8 82 compatible = "fsl,mpc8544-l2-cache-controller";
79 reg = <0x20000 0x1000> 83 reg = <0x20000 0x1000>;
80 cache-line-size = <32> 84 cache-line-size = <32>;
81 cache-size = <0x40000> 85 cache-size = <0x40000>; // L2, 256K
82 interrupt-parent = <&m 86 interrupt-parent = <&mpic>;
83 interrupts = <16 2>; 87 interrupts = <16 2>;
84 }; 88 };
85 89
86 i2c@3000 { 90 i2c@3000 {
87 #address-cells = <1>; 91 #address-cells = <1>;
88 #size-cells = <0>; 92 #size-cells = <0>;
89 cell-index = <0>; 93 cell-index = <0>;
90 compatible = "fsl,mpc8 94 compatible = "fsl,mpc8544-i2c", "fsl-i2c";
91 reg = <0x3000 0x100>; 95 reg = <0x3000 0x100>;
92 interrupts = <43 2>; 96 interrupts = <43 2>;
93 interrupt-parent = <&m 97 interrupt-parent = <&mpic>;
94 fsl,preserve-clocking; 98 fsl,preserve-clocking;
95 99
96 dtt@28 { 100 dtt@28 {
97 compatible = " 101 compatible = "winbond,w83782d";
98 reg = <0x28>; 102 reg = <0x28>;
99 }; 103 };
100 rtc@32 { 104 rtc@32 {
101 compatible = " 105 compatible = "epson,rx8025";
102 reg = <0x32>; 106 reg = <0x32>;
103 interrupts = < 107 interrupts = <7 1>;
104 interrupt-pare 108 interrupt-parent = <&mpic>;
105 }; 109 };
106 dtt@4c { 110 dtt@4c {
107 compatible = " 111 compatible = "dallas,ds75";
108 reg = <0x4c>; 112 reg = <0x4c>;
109 }; 113 };
110 ts@4a { 114 ts@4a {
111 compatible = " 115 compatible = "ti,tsc2003";
112 reg = <0x4a>; 116 reg = <0x4a>;
113 interrupt-pare 117 interrupt-parent = <&mpic>;
114 interrupts = < 118 interrupts = <8 1>;
115 }; 119 };
116 }; 120 };
117 121
118 i2c@3100 { 122 i2c@3100 {
119 #address-cells = <1>; 123 #address-cells = <1>;
120 #size-cells = <0>; 124 #size-cells = <0>;
121 cell-index = <1>; 125 cell-index = <1>;
122 compatible = "fsl,mpc8 126 compatible = "fsl,mpc8544-i2c", "fsl-i2c";
123 reg = <0x3100 0x100>; 127 reg = <0x3100 0x100>;
124 interrupts = <43 2>; 128 interrupts = <43 2>;
125 interrupt-parent = <&m 129 interrupt-parent = <&mpic>;
126 fsl,preserve-clocking; 130 fsl,preserve-clocking;
127 }; 131 };
128 132
129 enet0: ethernet@24000 { 133 enet0: ethernet@24000 {
130 #address-cells = <1>; 134 #address-cells = <1>;
131 #size-cells = <1>; 135 #size-cells = <1>;
132 cell-index = <0>; 136 cell-index = <0>;
133 device_type = "network 137 device_type = "network";
134 model = "eTSEC"; 138 model = "eTSEC";
135 compatible = "gianfar" 139 compatible = "gianfar";
136 reg = <0x24000 0x1000> 140 reg = <0x24000 0x1000>;
137 ranges = <0x0 0x24000 141 ranges = <0x0 0x24000 0x1000>;
138 local-mac-address = [ 142 local-mac-address = [ 00 00 00 00 00 00 ];
139 interrupts = <29 2 30 143 interrupts = <29 2 30 2 34 2>;
140 interrupt-parent = <&m 144 interrupt-parent = <&mpic>;
141 phy-handle = <&phy0>; 145 phy-handle = <&phy0>;
142 tbi-handle = <&tbi0>; 146 tbi-handle = <&tbi0>;
143 phy-connection-type = 147 phy-connection-type = "rgmii-id";
144 148
145 mdio@520 { 149 mdio@520 {
146 #address-cells 150 #address-cells = <1>;
147 #size-cells = 151 #size-cells = <0>;
148 compatible = " 152 compatible = "fsl,gianfar-mdio";
149 reg = <0x520 0 153 reg = <0x520 0x20>;
150 154
151 phy0: ethernet 155 phy0: ethernet-phy@0 {
152 interr 156 interrupt-parent = <&mpic>;
153 interr 157 interrupts = <0 1>;
154 reg = 158 reg = <0>;
155 }; 159 };
156 phy1: ethernet 160 phy1: ethernet-phy@1 {
157 interr 161 interrupt-parent = <&mpic>;
158 interr 162 interrupts = <0 1>;
159 reg = 163 reg = <1>;
160 }; 164 };
161 tbi0: tbi-phy@ 165 tbi0: tbi-phy@11 {
162 reg = 166 reg = <0x11>;
163 }; 167 };
164 }; 168 };
165 }; 169 };
166 170
167 enet1: ethernet@26000 { 171 enet1: ethernet@26000 {
168 #address-cells = <1>; 172 #address-cells = <1>;
169 #size-cells = <1>; 173 #size-cells = <1>;
170 cell-index = <1>; 174 cell-index = <1>;
171 device_type = "network 175 device_type = "network";
172 model = "eTSEC"; 176 model = "eTSEC";
173 compatible = "gianfar" 177 compatible = "gianfar";
174 reg = <0x26000 0x1000> 178 reg = <0x26000 0x1000>;
175 ranges = <0x0 0x26000 179 ranges = <0x0 0x26000 0x1000>;
176 local-mac-address = [ 180 local-mac-address = [ 00 00 00 00 00 00 ];
177 interrupts = <31 2 32 181 interrupts = <31 2 32 2 33 2>;
178 interrupt-parent = <&m 182 interrupt-parent = <&mpic>;
179 phy-handle = <&phy1>; 183 phy-handle = <&phy1>;
180 tbi-handle = <&tbi1>; 184 tbi-handle = <&tbi1>;
181 phy-connection-type = 185 phy-connection-type = "rgmii-id";
182 186
183 mdio@520 { 187 mdio@520 {
184 #address-cells 188 #address-cells = <1>;
185 #size-cells = 189 #size-cells = <0>;
186 compatible = " 190 compatible = "fsl,gianfar-tbi";
187 reg = <0x520 0 191 reg = <0x520 0x20>;
188 192
189 tbi1: tbi-phy@ 193 tbi1: tbi-phy@11 {
190 reg = 194 reg = <0x11>;
191 }; 195 };
192 }; 196 };
193 }; 197 };
194 198
195 serial0: serial@4500 { 199 serial0: serial@4500 {
196 cell-index = <0>; 200 cell-index = <0>;
197 device_type = "serial" 201 device_type = "serial";
198 compatible = "fsl,ns16 202 compatible = "fsl,ns16550", "ns16550";
199 reg = <0x4500 0x100>; 203 reg = <0x4500 0x100>;
200 clock-frequency = <0>; 204 clock-frequency = <0>;
201 interrupts = <42 2>; 205 interrupts = <42 2>;
202 interrupt-parent = <&m 206 interrupt-parent = <&mpic>;
203 }; 207 };
204 208
205 serial1: serial@4600 { 209 serial1: serial@4600 {
206 cell-index = <1>; 210 cell-index = <1>;
207 device_type = "serial" 211 device_type = "serial";
208 compatible = "fsl,ns16 212 compatible = "fsl,ns16550", "ns16550";
209 reg = <0x4600 0x100>; 213 reg = <0x4600 0x100>;
210 clock-frequency = <0>; 214 clock-frequency = <0>;
211 interrupts = <42 2>; 215 interrupts = <42 2>;
212 interrupt-parent = <&m 216 interrupt-parent = <&mpic>;
213 }; 217 };
214 218
215 global-utilities@e0000 { 219 global-utilities@e0000 { //global utilities block
216 compatible = "fsl,mpc8 220 compatible = "fsl,mpc8548-guts";
217 reg = <0xe0000 0x1000> 221 reg = <0xe0000 0x1000>;
218 fsl,has-rstcr; 222 fsl,has-rstcr;
219 }; 223 };
220 224
221 mpic: pic@40000 { 225 mpic: pic@40000 {
222 interrupt-controller; 226 interrupt-controller;
223 #address-cells = <0>; 227 #address-cells = <0>;
224 #interrupt-cells = <2> 228 #interrupt-cells = <2>;
225 reg = <0x40000 0x40000 229 reg = <0x40000 0x40000>;
226 compatible = "chrp,ope 230 compatible = "chrp,open-pic";
227 device_type = "open-pi 231 device_type = "open-pic";
228 }; 232 };
229 }; 233 };
230 234
231 235
232 localbus { 236 localbus {
233 compatible = "fsl,mpc8544-loca 237 compatible = "fsl,mpc8544-localbus",
234 "fsl,pq3-localbus 238 "fsl,pq3-localbus",
235 "simple-bus"; 239 "simple-bus";
236 #address-cells = <2>; 240 #address-cells = <2>;
237 #size-cells = <1>; 241 #size-cells = <1>;
238 reg = <0xe0005000 0x40>; 242 reg = <0xe0005000 0x40>;
239 interrupt-parent = <&mpic>; 243 interrupt-parent = <&mpic>;
240 interrupts = <19 2>; 244 interrupts = <19 2>;
241 245
242 ranges = <0 0 0xfc000000 0x040 246 ranges = <0 0 0xfc000000 0x04000000
243 2 0 0xc8000000 0x040 247 2 0 0xc8000000 0x04000000
244 3 0 0xc0000000 0x001 248 3 0 0xc0000000 0x00100000
245 >; /* Overwritten by U 249 >; /* Overwritten by U-Boot */
246 250
247 nor_flash@0,0 { 251 nor_flash@0,0 {
248 compatible = "amd,s29g 252 compatible = "amd,s29gl256n", "cfi-flash";
249 bank-width = <2>; 253 bank-width = <2>;
250 reg = <0x0 0x000000 0x 254 reg = <0x0 0x000000 0x4000000>;
251 #address-cells = <1>; 255 #address-cells = <1>;
252 #size-cells = <1>; 256 #size-cells = <1>;
253 partition@0 { 257 partition@0 {
254 label = "kerne 258 label = "kernel";
255 reg = <0x0 0x1 259 reg = <0x0 0x1e0000>;
256 read-only; 260 read-only;
257 }; 261 };
258 partition@1e0000 { 262 partition@1e0000 {
259 label = "dtb"; 263 label = "dtb";
260 reg = <0x1e000 264 reg = <0x1e0000 0x20000>;
261 }; 265 };
262 partition@200000 { 266 partition@200000 {
263 label = "root" 267 label = "root";
264 reg = <0x20000 268 reg = <0x200000 0x200000>;
265 }; 269 };
266 partition@400000 { 270 partition@400000 {
267 label = "user" 271 label = "user";
268 reg = <0x40000 272 reg = <0x400000 0x3b80000>;
269 }; 273 };
270 partition@3f80000 { 274 partition@3f80000 {
271 label = "env"; 275 label = "env";
272 reg = <0x3f800 276 reg = <0x3f80000 0x40000>;
273 read-only; 277 read-only;
274 }; 278 };
275 partition@3fc0000 { 279 partition@3fc0000 {
276 label = "u-boo 280 label = "u-boot";
277 reg = <0x3fc00 281 reg = <0x3fc0000 0x40000>;
278 read-only; 282 read-only;
279 }; 283 };
280 }; 284 };
281 285
282 display@2,0 { 286 display@2,0 {
283 compatible = "fujitsu, 287 compatible = "fujitsu,lime";
284 reg = <2 0x0 0x4000000 288 reg = <2 0x0 0x4000000>;
285 interrupt-parent = <&m 289 interrupt-parent = <&mpic>;
286 interrupts = <6 1>; 290 interrupts = <6 1>;
287 }; 291 };
288 292
289 fpga_pic: fpga-pic@3,10 { 293 fpga_pic: fpga-pic@3,10 {
290 compatible = "abb,socr 294 compatible = "abb,socrates-fpga-pic";
291 reg = <3 0x10 0x10>; 295 reg = <3 0x10 0x10>;
292 interrupt-controller; 296 interrupt-controller;
293 /* IRQs 2, 10, 11, act 297 /* IRQs 2, 10, 11, active low, level-sensitive */
294 interrupts = <2 1 10 1 298 interrupts = <2 1 10 1 11 1>;
295 interrupt-parent = <&m 299 interrupt-parent = <&mpic>;
296 #interrupt-cells = <3> 300 #interrupt-cells = <3>;
297 }; 301 };
298 302
299 spi@3,60 { 303 spi@3,60 {
300 compatible = "abb,socr 304 compatible = "abb,socrates-spi";
301 reg = <3 0x60 0x10>; 305 reg = <3 0x60 0x10>;
302 interrupts = <8 4 0>; 306 interrupts = <8 4 0>; // number, type, routing
303 interrupt-parent = <&f 307 interrupt-parent = <&fpga_pic>;
304 }; 308 };
305 309
306 nand@3,70 { 310 nand@3,70 {
307 compatible = "abb,socr 311 compatible = "abb,socrates-nand";
308 reg = <3 0x70 0x04>; 312 reg = <3 0x70 0x04>;
309 bank-width = <1>; 313 bank-width = <1>;
310 #address-cells = <1>; 314 #address-cells = <1>;
311 #size-cells = <1>; 315 #size-cells = <1>;
312 data@0 { 316 data@0 {
313 label = "data" 317 label = "data";
314 reg = <0x0 0x4 318 reg = <0x0 0x40000000>;
315 }; 319 };
316 }; 320 };
317 321
318 can@3,100 { 322 can@3,100 {
319 compatible = "philips, 323 compatible = "philips,sja1000";
320 reg = <3 0x100 0x80>; 324 reg = <3 0x100 0x80>;
321 interrupts = <2 8 1>; 325 interrupts = <2 8 1>; // number, type, routing
322 interrupt-parent = <&f 326 interrupt-parent = <&fpga_pic>;
323 }; 327 };
324 }; 328 };
325 329
326 pci0: pci@e0008000 { 330 pci0: pci@e0008000 {
327 #interrupt-cells = <1>; 331 #interrupt-cells = <1>;
328 #size-cells = <2>; 332 #size-cells = <2>;
329 #address-cells = <3>; 333 #address-cells = <3>;
330 compatible = "fsl,mpc8540-pci" 334 compatible = "fsl,mpc8540-pci";
331 device_type = "pci"; 335 device_type = "pci";
332 reg = <0xe0008000 0x1000>; 336 reg = <0xe0008000 0x1000>;
333 clock-frequency = <66666666>; 337 clock-frequency = <66666666>;
334 338
335 interrupt-map-mask = <0xf800 0 339 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
336 interrupt-map = < 340 interrupt-map = <
337 /* IDSEL 0x11 341 /* IDSEL 0x11 */
338 0x8800 0x0 0x 342 0x8800 0x0 0x0 1 &mpic 5 1
339 /* IDSEL 0x12 343 /* IDSEL 0x12 */
340 0x9000 0x0 0x 344 0x9000 0x0 0x0 1 &mpic 4 1>;
341 interrupt-parent = <&mpic>; 345 interrupt-parent = <&mpic>;
342 interrupts = <24 2>; 346 interrupts = <24 2>;
343 bus-range = <0x0 0x0>; 347 bus-range = <0x0 0x0>;
344 ranges = <0x02000000 0x0 0x800 348 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
345 0x01000000 0x0 0x000 349 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x01000000>;
346 }; 350 };
347 351
348 }; 352 };
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