1 // SPDX-License-Identifier: GPL-2.0-or-later 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* 2 /*
3 * TQM5200 board Device Tree Source 3 * TQM5200 board Device Tree Source
4 * 4 *
5 * Copyright (C) 2007 Semihalf 5 * Copyright (C) 2007 Semihalf
6 * Marian Balakowicz <m8@semihalf.com> 6 * Marian Balakowicz <m8@semihalf.com>
7 */ 7 */
8 8
9 /dts-v1/; 9 /dts-v1/;
10 10
11 / { 11 / {
12 model = "tqc,tqm5200"; 12 model = "tqc,tqm5200";
13 compatible = "tqc,tqm5200"; 13 compatible = "tqc,tqm5200";
14 #address-cells = <1>; 14 #address-cells = <1>;
15 #size-cells = <1>; 15 #size-cells = <1>;
16 interrupt-parent = <&mpc5200_pic>; 16 interrupt-parent = <&mpc5200_pic>;
17 17
18 cpus { 18 cpus {
19 #address-cells = <1>; 19 #address-cells = <1>;
20 #size-cells = <0>; 20 #size-cells = <0>;
21 21
22 PowerPC,5200@0 { 22 PowerPC,5200@0 {
23 device_type = "cpu"; 23 device_type = "cpu";
24 reg = <0>; 24 reg = <0>;
25 d-cache-line-size = <3 25 d-cache-line-size = <32>;
26 i-cache-line-size = <3 26 i-cache-line-size = <32>;
27 d-cache-size = <0x4000 27 d-cache-size = <0x4000>; // L1, 16K
28 i-cache-size = <0x4000 28 i-cache-size = <0x4000>; // L1, 16K
29 timebase-frequency = < 29 timebase-frequency = <0>; // from bootloader
30 bus-frequency = <0>; 30 bus-frequency = <0>; // from bootloader
31 clock-frequency = <0>; 31 clock-frequency = <0>; // from bootloader
32 }; 32 };
33 }; 33 };
34 34
35 memory@0 { 35 memory@0 {
36 device_type = "memory"; 36 device_type = "memory";
37 reg = <0x00000000 0x04000000>; 37 reg = <0x00000000 0x04000000>; // 64MB
38 }; 38 };
39 39
40 soc5200@f0000000 { 40 soc5200@f0000000 {
41 #address-cells = <1>; 41 #address-cells = <1>;
42 #size-cells = <1>; 42 #size-cells = <1>;
43 compatible = "fsl,mpc5200-immr 43 compatible = "fsl,mpc5200-immr";
44 ranges = <0 0xf0000000 0x0000c 44 ranges = <0 0xf0000000 0x0000c000>;
45 reg = <0xf0000000 0x00000100>; 45 reg = <0xf0000000 0x00000100>;
46 bus-frequency = <0>; 46 bus-frequency = <0>; // from bootloader
47 system-frequency = <0>; 47 system-frequency = <0>; // from bootloader
48 48
49 cdm@200 { 49 cdm@200 {
50 compatible = "fsl,mpc5 50 compatible = "fsl,mpc5200-cdm";
51 reg = <0x200 0x38>; 51 reg = <0x200 0x38>;
52 }; 52 };
53 53
54 mpc5200_pic: interrupt-control 54 mpc5200_pic: interrupt-controller@500 {
55 // 5200 interrupts are 55 // 5200 interrupts are encoded into two levels;
56 interrupt-controller; 56 interrupt-controller;
57 #interrupt-cells = <3> 57 #interrupt-cells = <3>;
58 compatible = "fsl,mpc5 58 compatible = "fsl,mpc5200-pic";
59 reg = <0x500 0x80>; 59 reg = <0x500 0x80>;
60 }; 60 };
61 61
62 timer@600 { // General Pur 62 timer@600 { // General Purpose Timer
63 compatible = "fsl,mpc5 63 compatible = "fsl,mpc5200-gpt";
64 reg = <0x600 0x10>; 64 reg = <0x600 0x10>;
65 interrupts = <1 9 0>; 65 interrupts = <1 9 0>;
66 fsl,has-wdt; 66 fsl,has-wdt;
67 }; 67 };
68 68
69 can@900 { 69 can@900 {
70 compatible = "fsl,mpc5 70 compatible = "fsl,mpc5200-mscan";
71 interrupts = <2 17 0>; 71 interrupts = <2 17 0>;
72 reg = <0x900 0x80>; 72 reg = <0x900 0x80>;
73 }; 73 };
74 74
75 can@980 { 75 can@980 {
76 compatible = "fsl,mpc5 76 compatible = "fsl,mpc5200-mscan";
77 interrupts = <2 18 0>; 77 interrupts = <2 18 0>;
78 reg = <0x980 0x80>; 78 reg = <0x980 0x80>;
79 }; 79 };
80 80
81 gpio_simple: gpio@b00 { 81 gpio_simple: gpio@b00 {
82 compatible = "fsl,mpc5 82 compatible = "fsl,mpc5200-gpio";
83 reg = <0xb00 0x40>; 83 reg = <0xb00 0x40>;
84 interrupts = <1 7 0>; 84 interrupts = <1 7 0>;
85 gpio-controller; 85 gpio-controller;
86 #gpio-cells = <2>; 86 #gpio-cells = <2>;
87 }; 87 };
88 88
89 usb@1000 { 89 usb@1000 {
90 compatible = "fsl,mpc5 90 compatible = "fsl,mpc5200-ohci","ohci-be";
91 reg = <0x1000 0xff>; 91 reg = <0x1000 0xff>;
92 interrupts = <2 6 0>; 92 interrupts = <2 6 0>;
93 }; 93 };
94 94
95 dma-controller@1200 { 95 dma-controller@1200 {
96 compatible = "fsl,mpc5 96 compatible = "fsl,mpc5200-bestcomm";
97 reg = <0x1200 0x80>; 97 reg = <0x1200 0x80>;
98 interrupts = <3 0 0 3 98 interrupts = <3 0 0 3 1 0 3 2 0 3 3 0
99 3 4 0 3 99 3 4 0 3 5 0 3 6 0 3 7 0
100 3 8 0 3 100 3 8 0 3 9 0 3 10 0 3 11 0
101 3 12 0 101 3 12 0 3 13 0 3 14 0 3 15 0>;
102 }; 102 };
103 103
104 xlb@1f00 { 104 xlb@1f00 {
105 compatible = "fsl,mpc5 105 compatible = "fsl,mpc5200-xlb";
106 reg = <0x1f00 0x100>; 106 reg = <0x1f00 0x100>;
107 }; 107 };
108 108
109 serial@2000 { // PSC 109 serial@2000 { // PSC1
110 compatible = "fsl,mpc5 110 compatible = "fsl,mpc5200-psc-uart";
111 reg = <0x2000 0x100>; 111 reg = <0x2000 0x100>;
112 interrupts = <2 1 0>; 112 interrupts = <2 1 0>;
113 }; 113 };
114 114
115 serial@2200 { // PSC 115 serial@2200 { // PSC2
116 compatible = "fsl,mpc5 116 compatible = "fsl,mpc5200-psc-uart";
117 reg = <0x2200 0x100>; 117 reg = <0x2200 0x100>;
118 interrupts = <2 2 0>; 118 interrupts = <2 2 0>;
119 }; 119 };
120 120
121 serial@2400 { // PSC 121 serial@2400 { // PSC3
122 compatible = "fsl,mpc5 122 compatible = "fsl,mpc5200-psc-uart";
123 reg = <0x2400 0x100>; 123 reg = <0x2400 0x100>;
124 interrupts = <2 3 0>; 124 interrupts = <2 3 0>;
125 }; 125 };
126 126
127 ethernet@3000 { 127 ethernet@3000 {
128 compatible = "fsl,mpc5 128 compatible = "fsl,mpc5200-fec";
129 reg = <0x3000 0x400>; 129 reg = <0x3000 0x400>;
130 local-mac-address = [ 130 local-mac-address = [ 00 00 00 00 00 00 ];
131 interrupts = <2 5 0>; 131 interrupts = <2 5 0>;
132 phy-handle = <&phy0>; 132 phy-handle = <&phy0>;
133 }; 133 };
134 134
135 mdio@3000 { 135 mdio@3000 {
136 #address-cells = <1>; 136 #address-cells = <1>;
137 #size-cells = <0>; 137 #size-cells = <0>;
138 compatible = "fsl,mpc5 138 compatible = "fsl,mpc5200-mdio";
139 reg = <0x3000 0x400>; 139 reg = <0x3000 0x400>; // fec range, since we need to setup fec interrupts
140 interrupts = <2 5 0>; 140 interrupts = <2 5 0>; // these are for "mii command finished", not link changes & co.
141 141
142 phy0: ethernet-phy@0 { 142 phy0: ethernet-phy@0 {
143 reg = <0>; 143 reg = <0>;
144 }; 144 };
145 }; 145 };
146 146
147 ata@3a00 { 147 ata@3a00 {
148 compatible = "fsl,mpc5 148 compatible = "fsl,mpc5200-ata";
149 reg = <0x3a00 0x100>; 149 reg = <0x3a00 0x100>;
150 interrupts = <2 7 0>; 150 interrupts = <2 7 0>;
151 }; 151 };
152 152
153 i2c@3d40 { 153 i2c@3d40 {
154 #address-cells = <1>; 154 #address-cells = <1>;
155 #size-cells = <0>; 155 #size-cells = <0>;
156 compatible = "fsl,mpc5 156 compatible = "fsl,mpc5200-i2c","fsl-i2c";
157 reg = <0x3d40 0x40>; 157 reg = <0x3d40 0x40>;
158 interrupts = <2 16 0>; 158 interrupts = <2 16 0>;
159 159
160 rtc@68 { 160 rtc@68 {
161 compatible = " 161 compatible = "dallas,ds1307";
162 reg = <0x68>; 162 reg = <0x68>;
163 }; 163 };
164 }; 164 };
165 165
166 sram@8000 { 166 sram@8000 {
167 compatible = "fsl,mpc5 167 compatible = "fsl,mpc5200-sram";
168 reg = <0x8000 0x4000>; 168 reg = <0x8000 0x4000>;
169 }; 169 };
170 }; 170 };
171 171
172 localbus { 172 localbus {
173 compatible = "fsl,mpc5200-lpb" 173 compatible = "fsl,mpc5200-lpb","simple-bus";
174 #address-cells = <2>; 174 #address-cells = <2>;
175 #size-cells = <1>; 175 #size-cells = <1>;
176 ranges = <0 0 0xfc000000 0x020 176 ranges = <0 0 0xfc000000 0x02000000>;
177 177
178 flash@0,0 { 178 flash@0,0 {
179 compatible = "cfi-flas 179 compatible = "cfi-flash";
180 reg = <0 0 0x02000000> 180 reg = <0 0 0x02000000>;
181 bank-width = <4>; 181 bank-width = <4>;
182 device-width = <2>; 182 device-width = <2>;
183 #size-cells = <1>; 183 #size-cells = <1>;
184 #address-cells = <1>; 184 #address-cells = <1>;
185 }; 185 };
186 }; 186 };
187 187
188 pci@f0000d00 { 188 pci@f0000d00 {
189 #interrupt-cells = <1>; 189 #interrupt-cells = <1>;
190 #size-cells = <2>; 190 #size-cells = <2>;
191 #address-cells = <3>; 191 #address-cells = <3>;
192 device_type = "pci"; 192 device_type = "pci";
193 compatible = "fsl,mpc5200-pci" 193 compatible = "fsl,mpc5200-pci";
194 reg = <0xf0000d00 0x100>; 194 reg = <0xf0000d00 0x100>;
195 interrupt-map-mask = <0xf800 0 195 interrupt-map-mask = <0xf800 0 0 7>;
196 interrupt-map = <0xc000 0 0 1 196 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3
197 0xc000 0 0 2 197 0xc000 0 0 2 &mpc5200_pic 0 0 3
198 0xc000 0 0 3 198 0xc000 0 0 3 &mpc5200_pic 0 0 3
199 0xc000 0 0 4 199 0xc000 0 0 4 &mpc5200_pic 0 0 3>;
200 clock-frequency = <0>; // From 200 clock-frequency = <0>; // From boot loader
201 interrupts = <2 8 0 2 9 0 2 10 201 interrupts = <2 8 0 2 9 0 2 10 0>;
202 bus-range = <0 0>; 202 bus-range = <0 0>;
203 ranges = <0x42000000 0 0x80000 203 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x10000000>,
204 <0x02000000 0 0x90000 204 <0x02000000 0 0x90000000 0x90000000 0 0x10000000>,
205 <0x01000000 0 0x00000 205 <0x01000000 0 0x00000000 0xa0000000 0 0x01000000>;
206 }; 206 };
207 }; 207 };
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