1 // SPDX-License-Identifier: GPL-2.0-or-later <<
2 /* 1 /*
3 * TQM 8541 Device Tree Source 2 * TQM 8541 Device Tree Source
4 * 3 *
5 * Copyright 2008 Freescale Semiconductor Inc. 4 * Copyright 2008 Freescale Semiconductor Inc.
>> 5 *
>> 6 * This program is free software; you can redistribute it and/or modify it
>> 7 * under the terms of the GNU General Public License as published by the
>> 8 * Free Software Foundation; either version 2 of the License, or (at your
>> 9 * option) any later version.
6 */ 10 */
7 11
8 /dts-v1/; 12 /dts-v1/;
9 <<
10 /include/ "fsl/e500v1_power_isa.dtsi" <<
11 13
12 / { 14 / {
13 model = "tqc,tqm8541"; 15 model = "tqc,tqm8541";
14 compatible = "tqc,tqm8541"; 16 compatible = "tqc,tqm8541";
15 #address-cells = <1>; 17 #address-cells = <1>;
16 #size-cells = <1>; 18 #size-cells = <1>;
17 19
18 aliases { 20 aliases {
19 ethernet0 = &enet0; 21 ethernet0 = &enet0;
20 ethernet1 = &enet1; 22 ethernet1 = &enet1;
21 serial0 = &serial0; 23 serial0 = &serial0;
22 serial1 = &serial1; 24 serial1 = &serial1;
23 pci0 = &pci0; 25 pci0 = &pci0;
24 }; 26 };
25 27
26 cpus { 28 cpus {
27 #address-cells = <1>; 29 #address-cells = <1>;
28 #size-cells = <0>; 30 #size-cells = <0>;
29 31
30 PowerPC,8541@0 { 32 PowerPC,8541@0 {
31 device_type = "cpu"; 33 device_type = "cpu";
32 reg = <0>; 34 reg = <0>;
33 d-cache-line-size = <3 35 d-cache-line-size = <32>;
34 i-cache-line-size = <3 36 i-cache-line-size = <32>;
35 d-cache-size = <32768> 37 d-cache-size = <32768>;
36 i-cache-size = <32768> 38 i-cache-size = <32768>;
37 timebase-frequency = < 39 timebase-frequency = <0>;
38 bus-frequency = <0>; 40 bus-frequency = <0>;
39 clock-frequency = <0>; 41 clock-frequency = <0>;
40 next-level-cache = <&L 42 next-level-cache = <&L2>;
41 }; 43 };
42 }; 44 };
43 45
44 memory { 46 memory {
45 device_type = "memory"; 47 device_type = "memory";
46 reg = <0x00000000 0x10000000>; 48 reg = <0x00000000 0x10000000>;
47 }; 49 };
48 50
49 soc@e0000000 { 51 soc@e0000000 {
50 #address-cells = <1>; 52 #address-cells = <1>;
51 #size-cells = <1>; 53 #size-cells = <1>;
52 device_type = "soc"; 54 device_type = "soc";
53 ranges = <0x0 0xe0000000 0x100 55 ranges = <0x0 0xe0000000 0x100000>;
54 bus-frequency = <0>; 56 bus-frequency = <0>;
55 compatible = "fsl,mpc8541-immr 57 compatible = "fsl,mpc8541-immr", "simple-bus";
56 58
57 ecm-law@0 { 59 ecm-law@0 {
58 compatible = "fsl,ecm- 60 compatible = "fsl,ecm-law";
59 reg = <0x0 0x1000>; 61 reg = <0x0 0x1000>;
60 fsl,num-laws = <8>; 62 fsl,num-laws = <8>;
61 }; 63 };
62 64
63 ecm@1000 { 65 ecm@1000 {
64 compatible = "fsl,mpc8 66 compatible = "fsl,mpc8541-ecm", "fsl,ecm";
65 reg = <0x1000 0x1000>; 67 reg = <0x1000 0x1000>;
66 interrupts = <17 2>; 68 interrupts = <17 2>;
67 interrupt-parent = <&m 69 interrupt-parent = <&mpic>;
68 }; 70 };
69 71
70 memory-controller@2000 { 72 memory-controller@2000 {
71 compatible = "fsl,mpc8 73 compatible = "fsl,mpc8540-memory-controller";
72 reg = <0x2000 0x1000>; 74 reg = <0x2000 0x1000>;
73 interrupt-parent = <&m 75 interrupt-parent = <&mpic>;
74 interrupts = <18 2>; 76 interrupts = <18 2>;
75 }; 77 };
76 78
77 L2: l2-cache-controller@20000 79 L2: l2-cache-controller@20000 {
78 compatible = "fsl,mpc8 80 compatible = "fsl,mpc8540-l2-cache-controller";
79 reg = <0x20000 0x1000> 81 reg = <0x20000 0x1000>;
80 cache-line-size = <32> 82 cache-line-size = <32>;
81 cache-size = <0x40000> 83 cache-size = <0x40000>; // L2, 256K
82 interrupt-parent = <&m 84 interrupt-parent = <&mpic>;
83 interrupts = <16 2>; 85 interrupts = <16 2>;
84 }; 86 };
85 87
86 i2c@3000 { 88 i2c@3000 {
87 #address-cells = <1>; 89 #address-cells = <1>;
88 #size-cells = <0>; 90 #size-cells = <0>;
89 cell-index = <0>; 91 cell-index = <0>;
90 compatible = "fsl-i2c" 92 compatible = "fsl-i2c";
91 reg = <0x3000 0x100>; 93 reg = <0x3000 0x100>;
92 interrupts = <43 2>; 94 interrupts = <43 2>;
93 interrupt-parent = <&m 95 interrupt-parent = <&mpic>;
94 dfsrr; 96 dfsrr;
95 97
96 dtt@48 { 98 dtt@48 {
97 compatible = " 99 compatible = "national,lm75";
98 reg = <0x48>; 100 reg = <0x48>;
99 }; 101 };
100 102
101 rtc@68 { 103 rtc@68 {
102 compatible = " 104 compatible = "dallas,ds1337";
103 reg = <0x68>; 105 reg = <0x68>;
104 }; 106 };
105 }; 107 };
106 108
107 dma@21300 { 109 dma@21300 {
108 #address-cells = <1>; 110 #address-cells = <1>;
109 #size-cells = <1>; 111 #size-cells = <1>;
110 compatible = "fsl,mpc8 112 compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma";
111 reg = <0x21300 0x4>; 113 reg = <0x21300 0x4>;
112 ranges = <0x0 0x21100 114 ranges = <0x0 0x21100 0x200>;
113 cell-index = <0>; 115 cell-index = <0>;
114 dma-channel@0 { 116 dma-channel@0 {
115 compatible = " 117 compatible = "fsl,mpc8541-dma-channel",
116 118 "fsl,eloplus-dma-channel";
117 reg = <0x0 0x8 119 reg = <0x0 0x80>;
118 cell-index = < 120 cell-index = <0>;
119 interrupt-pare 121 interrupt-parent = <&mpic>;
120 interrupts = < 122 interrupts = <20 2>;
121 }; 123 };
122 dma-channel@80 { 124 dma-channel@80 {
123 compatible = " 125 compatible = "fsl,mpc8541-dma-channel",
124 126 "fsl,eloplus-dma-channel";
125 reg = <0x80 0x 127 reg = <0x80 0x80>;
126 cell-index = < 128 cell-index = <1>;
127 interrupt-pare 129 interrupt-parent = <&mpic>;
128 interrupts = < 130 interrupts = <21 2>;
129 }; 131 };
130 dma-channel@100 { 132 dma-channel@100 {
131 compatible = " 133 compatible = "fsl,mpc8541-dma-channel",
132 134 "fsl,eloplus-dma-channel";
133 reg = <0x100 0 135 reg = <0x100 0x80>;
134 cell-index = < 136 cell-index = <2>;
135 interrupt-pare 137 interrupt-parent = <&mpic>;
136 interrupts = < 138 interrupts = <22 2>;
137 }; 139 };
138 dma-channel@180 { 140 dma-channel@180 {
139 compatible = " 141 compatible = "fsl,mpc8541-dma-channel",
140 142 "fsl,eloplus-dma-channel";
141 reg = <0x180 0 143 reg = <0x180 0x80>;
142 cell-index = < 144 cell-index = <3>;
143 interrupt-pare 145 interrupt-parent = <&mpic>;
144 interrupts = < 146 interrupts = <23 2>;
145 }; 147 };
146 }; 148 };
147 149
148 enet0: ethernet@24000 { 150 enet0: ethernet@24000 {
149 #address-cells = <1>; 151 #address-cells = <1>;
150 #size-cells = <1>; 152 #size-cells = <1>;
151 cell-index = <0>; 153 cell-index = <0>;
152 device_type = "network 154 device_type = "network";
153 model = "TSEC"; 155 model = "TSEC";
154 compatible = "gianfar" 156 compatible = "gianfar";
155 reg = <0x24000 0x1000> 157 reg = <0x24000 0x1000>;
156 ranges = <0x0 0x24000 158 ranges = <0x0 0x24000 0x1000>;
157 local-mac-address = [ 159 local-mac-address = [ 00 00 00 00 00 00 ];
158 interrupts = <29 2 30 160 interrupts = <29 2 30 2 34 2>;
159 interrupt-parent = <&m 161 interrupt-parent = <&mpic>;
160 tbi-handle = <&tbi0>; 162 tbi-handle = <&tbi0>;
161 phy-handle = <&phy2>; 163 phy-handle = <&phy2>;
162 164
163 mdio@520 { 165 mdio@520 {
164 #address-cells 166 #address-cells = <1>;
165 #size-cells = 167 #size-cells = <0>;
166 compatible = " 168 compatible = "fsl,gianfar-mdio";
167 reg = <0x520 0 169 reg = <0x520 0x20>;
168 170
169 phy1: ethernet 171 phy1: ethernet-phy@1 {
170 interr 172 interrupt-parent = <&mpic>;
171 interr 173 interrupts = <8 1>;
172 reg = 174 reg = <1>;
173 }; 175 };
174 phy2: ethernet 176 phy2: ethernet-phy@2 {
175 interr 177 interrupt-parent = <&mpic>;
176 interr 178 interrupts = <8 1>;
177 reg = 179 reg = <2>;
178 }; 180 };
179 phy3: ethernet 181 phy3: ethernet-phy@3 {
180 interr 182 interrupt-parent = <&mpic>;
181 interr 183 interrupts = <8 1>;
182 reg = 184 reg = <3>;
183 }; 185 };
184 tbi0: tbi-phy@ 186 tbi0: tbi-phy@11 {
185 reg = 187 reg = <0x11>;
186 device 188 device_type = "tbi-phy";
187 }; 189 };
188 }; 190 };
189 }; 191 };
190 192
191 enet1: ethernet@25000 { 193 enet1: ethernet@25000 {
192 #address-cells = <1>; 194 #address-cells = <1>;
193 #size-cells = <1>; 195 #size-cells = <1>;
194 cell-index = <1>; 196 cell-index = <1>;
195 device_type = "network 197 device_type = "network";
196 model = "TSEC"; 198 model = "TSEC";
197 compatible = "gianfar" 199 compatible = "gianfar";
198 reg = <0x25000 0x1000> 200 reg = <0x25000 0x1000>;
199 ranges = <0x0 0x25000 201 ranges = <0x0 0x25000 0x1000>;
200 local-mac-address = [ 202 local-mac-address = [ 00 00 00 00 00 00 ];
201 interrupts = <35 2 36 203 interrupts = <35 2 36 2 40 2>;
202 interrupt-parent = <&m 204 interrupt-parent = <&mpic>;
203 tbi-handle = <&tbi1>; 205 tbi-handle = <&tbi1>;
204 phy-handle = <&phy1>; 206 phy-handle = <&phy1>;
205 207
206 mdio@520 { 208 mdio@520 {
207 #address-cells 209 #address-cells = <1>;
208 #size-cells = 210 #size-cells = <0>;
209 compatible = " 211 compatible = "fsl,gianfar-tbi";
210 reg = <0x520 0 212 reg = <0x520 0x20>;
211 213
212 tbi1: tbi-phy@ 214 tbi1: tbi-phy@11 {
213 reg = 215 reg = <0x11>;
214 device 216 device_type = "tbi-phy";
215 }; 217 };
216 }; 218 };
217 }; 219 };
218 220
219 serial0: serial@4500 { 221 serial0: serial@4500 {
220 cell-index = <0>; 222 cell-index = <0>;
221 device_type = "serial" 223 device_type = "serial";
222 compatible = "fsl,ns16 224 compatible = "fsl,ns16550", "ns16550";
223 reg = <0x4500 0x100>; 225 reg = <0x4500 0x100>; // reg base, size
224 clock-frequency = <0>; 226 clock-frequency = <0>; // should we fill in in uboot?
225 interrupts = <42 2>; 227 interrupts = <42 2>;
226 interrupt-parent = <&m 228 interrupt-parent = <&mpic>;
227 }; 229 };
228 230
229 serial1: serial@4600 { 231 serial1: serial@4600 {
230 cell-index = <1>; 232 cell-index = <1>;
231 device_type = "serial" 233 device_type = "serial";
232 compatible = "fsl,ns16 234 compatible = "fsl,ns16550", "ns16550";
233 reg = <0x4600 0x100>; 235 reg = <0x4600 0x100>; // reg base, size
234 clock-frequency = <0>; 236 clock-frequency = <0>; // should we fill in in uboot?
235 interrupts = <42 2>; 237 interrupts = <42 2>;
236 interrupt-parent = <&m 238 interrupt-parent = <&mpic>;
237 }; 239 };
238 240
239 crypto@30000 { 241 crypto@30000 {
240 compatible = "fsl,sec2 242 compatible = "fsl,sec2.0";
241 reg = <0x30000 0x10000 243 reg = <0x30000 0x10000>;
242 interrupts = <45 2>; 244 interrupts = <45 2>;
243 interrupt-parent = <&m 245 interrupt-parent = <&mpic>;
244 fsl,num-channels = <4> 246 fsl,num-channels = <4>;
245 fsl,channel-fifo-len = 247 fsl,channel-fifo-len = <24>;
246 fsl,exec-units-mask = 248 fsl,exec-units-mask = <0x7e>;
247 fsl,descriptor-types-m 249 fsl,descriptor-types-mask = <0x01010ebf>;
248 }; 250 };
249 251
250 mpic: pic@40000 { 252 mpic: pic@40000 {
251 interrupt-controller; 253 interrupt-controller;
252 #address-cells = <0>; 254 #address-cells = <0>;
253 #interrupt-cells = <2> 255 #interrupt-cells = <2>;
254 reg = <0x40000 0x40000 256 reg = <0x40000 0x40000>;
255 device_type = "open-pi 257 device_type = "open-pic";
256 compatible = "chrp,ope 258 compatible = "chrp,open-pic";
257 }; 259 };
258 260
259 cpm@919c0 { 261 cpm@919c0 {
260 #address-cells = <1>; 262 #address-cells = <1>;
261 #size-cells = <1>; 263 #size-cells = <1>;
262 compatible = "fsl,mpc8 264 compatible = "fsl,mpc8541-cpm", "fsl,cpm2", "simple-bus";
263 reg = <0x919c0 0x30>; 265 reg = <0x919c0 0x30>;
264 ranges; 266 ranges;
265 267
266 muram@80000 { 268 muram@80000 {
267 #address-cells 269 #address-cells = <1>;
268 #size-cells = 270 #size-cells = <1>;
269 ranges = <0 0x 271 ranges = <0 0x80000 0x10000>;
270 272
271 data@0 { 273 data@0 {
272 compat 274 compatible = "fsl,cpm-muram-data";
273 reg = 275 reg = <0 0x2000 0x9000 0x1000>;
274 }; 276 };
275 }; 277 };
276 278
277 brg@919f0 { 279 brg@919f0 {
278 compatible = " 280 compatible = "fsl,mpc8541-brg",
279 " 281 "fsl,cpm2-brg",
280 " 282 "fsl,cpm-brg";
281 reg = <0x919f0 283 reg = <0x919f0 0x10 0x915f0 0x10>;
282 clock-frequenc 284 clock-frequency = <0>;
283 }; 285 };
284 286
285 cpmpic: pic@90c00 { 287 cpmpic: pic@90c00 {
286 interrupt-cont 288 interrupt-controller;
287 #address-cells 289 #address-cells = <0>;
288 #interrupt-cel 290 #interrupt-cells = <2>;
289 interrupts = < 291 interrupts = <46 2>;
290 interrupt-pare 292 interrupt-parent = <&mpic>;
291 reg = <0x90c00 293 reg = <0x90c00 0x80>;
292 compatible = " 294 compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic";
293 }; 295 };
294 }; 296 };
295 }; 297 };
296 298
297 pci0: pci@e0008000 { 299 pci0: pci@e0008000 {
298 #interrupt-cells = <1>; 300 #interrupt-cells = <1>;
299 #size-cells = <2>; 301 #size-cells = <2>;
300 #address-cells = <3>; 302 #address-cells = <3>;
301 compatible = "fsl,mpc8540-pcix 303 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
302 device_type = "pci"; 304 device_type = "pci";
303 reg = <0xe0008000 0x1000>; 305 reg = <0xe0008000 0x1000>;
304 clock-frequency = <66666666>; 306 clock-frequency = <66666666>;
305 interrupt-map-mask = <0xf800 0 307 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
306 interrupt-map = < 308 interrupt-map = <
307 /* IDSEL 28 */ 309 /* IDSEL 28 */
308 0xe000 0 0 1 310 0xe000 0 0 1 &mpic 2 1
309 0xe000 0 0 2 311 0xe000 0 0 2 &mpic 3 1
310 0xe000 0 0 3 312 0xe000 0 0 3 &mpic 6 1
311 0xe000 0 0 4 313 0xe000 0 0 4 &mpic 5 1
312 314
313 /* IDSEL 11 */ 315 /* IDSEL 11 */
314 0x5800 0 0 1 316 0x5800 0 0 1 &mpic 6 1
315 0x5800 0 0 2 317 0x5800 0 0 2 &mpic 5 1
316 >; 318 >;
317 319
318 interrupt-parent = <&mpic>; 320 interrupt-parent = <&mpic>;
319 interrupts = <24 2>; 321 interrupts = <24 2>;
320 bus-range = <0 0>; 322 bus-range = <0 0>;
321 ranges = <0x02000000 0 0x80000 323 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
322 0x01000000 0 0x00000 324 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
323 }; 325 };
324 }; 326 };
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