1 // SPDX-License-Identifier: GPL-2.0-or-later 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* 2 /*
3 * TQM 8541 Device Tree Source 3 * TQM 8541 Device Tree Source
4 * 4 *
5 * Copyright 2008 Freescale Semiconductor Inc. 5 * Copyright 2008 Freescale Semiconductor Inc.
6 */ 6 */
7 7
8 /dts-v1/; 8 /dts-v1/;
9 9
10 /include/ "fsl/e500v1_power_isa.dtsi" <<
11 <<
12 / { 10 / {
13 model = "tqc,tqm8541"; 11 model = "tqc,tqm8541";
14 compatible = "tqc,tqm8541"; 12 compatible = "tqc,tqm8541";
15 #address-cells = <1>; 13 #address-cells = <1>;
16 #size-cells = <1>; 14 #size-cells = <1>;
17 15
18 aliases { 16 aliases {
19 ethernet0 = &enet0; 17 ethernet0 = &enet0;
20 ethernet1 = &enet1; 18 ethernet1 = &enet1;
21 serial0 = &serial0; 19 serial0 = &serial0;
22 serial1 = &serial1; 20 serial1 = &serial1;
23 pci0 = &pci0; 21 pci0 = &pci0;
24 }; 22 };
25 23
26 cpus { 24 cpus {
27 #address-cells = <1>; 25 #address-cells = <1>;
28 #size-cells = <0>; 26 #size-cells = <0>;
29 27
30 PowerPC,8541@0 { 28 PowerPC,8541@0 {
31 device_type = "cpu"; 29 device_type = "cpu";
32 reg = <0>; 30 reg = <0>;
33 d-cache-line-size = <3 31 d-cache-line-size = <32>;
34 i-cache-line-size = <3 32 i-cache-line-size = <32>;
35 d-cache-size = <32768> 33 d-cache-size = <32768>;
36 i-cache-size = <32768> 34 i-cache-size = <32768>;
37 timebase-frequency = < 35 timebase-frequency = <0>;
38 bus-frequency = <0>; 36 bus-frequency = <0>;
39 clock-frequency = <0>; 37 clock-frequency = <0>;
40 next-level-cache = <&L 38 next-level-cache = <&L2>;
41 }; 39 };
42 }; 40 };
43 41
44 memory { 42 memory {
45 device_type = "memory"; 43 device_type = "memory";
46 reg = <0x00000000 0x10000000>; 44 reg = <0x00000000 0x10000000>;
47 }; 45 };
48 46
49 soc@e0000000 { 47 soc@e0000000 {
50 #address-cells = <1>; 48 #address-cells = <1>;
51 #size-cells = <1>; 49 #size-cells = <1>;
52 device_type = "soc"; 50 device_type = "soc";
53 ranges = <0x0 0xe0000000 0x100 51 ranges = <0x0 0xe0000000 0x100000>;
54 bus-frequency = <0>; 52 bus-frequency = <0>;
55 compatible = "fsl,mpc8541-immr 53 compatible = "fsl,mpc8541-immr", "simple-bus";
56 54
57 ecm-law@0 { 55 ecm-law@0 {
58 compatible = "fsl,ecm- 56 compatible = "fsl,ecm-law";
59 reg = <0x0 0x1000>; 57 reg = <0x0 0x1000>;
60 fsl,num-laws = <8>; 58 fsl,num-laws = <8>;
61 }; 59 };
62 60
63 ecm@1000 { 61 ecm@1000 {
64 compatible = "fsl,mpc8 62 compatible = "fsl,mpc8541-ecm", "fsl,ecm";
65 reg = <0x1000 0x1000>; 63 reg = <0x1000 0x1000>;
66 interrupts = <17 2>; 64 interrupts = <17 2>;
67 interrupt-parent = <&m 65 interrupt-parent = <&mpic>;
68 }; 66 };
69 67
70 memory-controller@2000 { 68 memory-controller@2000 {
71 compatible = "fsl,mpc8 69 compatible = "fsl,mpc8540-memory-controller";
72 reg = <0x2000 0x1000>; 70 reg = <0x2000 0x1000>;
73 interrupt-parent = <&m 71 interrupt-parent = <&mpic>;
74 interrupts = <18 2>; 72 interrupts = <18 2>;
75 }; 73 };
76 74
77 L2: l2-cache-controller@20000 75 L2: l2-cache-controller@20000 {
78 compatible = "fsl,mpc8 76 compatible = "fsl,mpc8540-l2-cache-controller";
79 reg = <0x20000 0x1000> 77 reg = <0x20000 0x1000>;
80 cache-line-size = <32> 78 cache-line-size = <32>;
81 cache-size = <0x40000> 79 cache-size = <0x40000>; // L2, 256K
82 interrupt-parent = <&m 80 interrupt-parent = <&mpic>;
83 interrupts = <16 2>; 81 interrupts = <16 2>;
84 }; 82 };
85 83
86 i2c@3000 { 84 i2c@3000 {
87 #address-cells = <1>; 85 #address-cells = <1>;
88 #size-cells = <0>; 86 #size-cells = <0>;
89 cell-index = <0>; 87 cell-index = <0>;
90 compatible = "fsl-i2c" 88 compatible = "fsl-i2c";
91 reg = <0x3000 0x100>; 89 reg = <0x3000 0x100>;
92 interrupts = <43 2>; 90 interrupts = <43 2>;
93 interrupt-parent = <&m 91 interrupt-parent = <&mpic>;
94 dfsrr; 92 dfsrr;
95 93
96 dtt@48 { 94 dtt@48 {
97 compatible = " 95 compatible = "national,lm75";
98 reg = <0x48>; 96 reg = <0x48>;
99 }; 97 };
100 98
101 rtc@68 { 99 rtc@68 {
102 compatible = " 100 compatible = "dallas,ds1337";
103 reg = <0x68>; 101 reg = <0x68>;
104 }; 102 };
105 }; 103 };
106 104
107 dma@21300 { 105 dma@21300 {
108 #address-cells = <1>; 106 #address-cells = <1>;
109 #size-cells = <1>; 107 #size-cells = <1>;
110 compatible = "fsl,mpc8 108 compatible = "fsl,mpc8541-dma", "fsl,eloplus-dma";
111 reg = <0x21300 0x4>; 109 reg = <0x21300 0x4>;
112 ranges = <0x0 0x21100 110 ranges = <0x0 0x21100 0x200>;
113 cell-index = <0>; 111 cell-index = <0>;
114 dma-channel@0 { 112 dma-channel@0 {
115 compatible = " 113 compatible = "fsl,mpc8541-dma-channel",
116 114 "fsl,eloplus-dma-channel";
117 reg = <0x0 0x8 115 reg = <0x0 0x80>;
118 cell-index = < 116 cell-index = <0>;
119 interrupt-pare 117 interrupt-parent = <&mpic>;
120 interrupts = < 118 interrupts = <20 2>;
121 }; 119 };
122 dma-channel@80 { 120 dma-channel@80 {
123 compatible = " 121 compatible = "fsl,mpc8541-dma-channel",
124 122 "fsl,eloplus-dma-channel";
125 reg = <0x80 0x 123 reg = <0x80 0x80>;
126 cell-index = < 124 cell-index = <1>;
127 interrupt-pare 125 interrupt-parent = <&mpic>;
128 interrupts = < 126 interrupts = <21 2>;
129 }; 127 };
130 dma-channel@100 { 128 dma-channel@100 {
131 compatible = " 129 compatible = "fsl,mpc8541-dma-channel",
132 130 "fsl,eloplus-dma-channel";
133 reg = <0x100 0 131 reg = <0x100 0x80>;
134 cell-index = < 132 cell-index = <2>;
135 interrupt-pare 133 interrupt-parent = <&mpic>;
136 interrupts = < 134 interrupts = <22 2>;
137 }; 135 };
138 dma-channel@180 { 136 dma-channel@180 {
139 compatible = " 137 compatible = "fsl,mpc8541-dma-channel",
140 138 "fsl,eloplus-dma-channel";
141 reg = <0x180 0 139 reg = <0x180 0x80>;
142 cell-index = < 140 cell-index = <3>;
143 interrupt-pare 141 interrupt-parent = <&mpic>;
144 interrupts = < 142 interrupts = <23 2>;
145 }; 143 };
146 }; 144 };
147 145
148 enet0: ethernet@24000 { 146 enet0: ethernet@24000 {
149 #address-cells = <1>; 147 #address-cells = <1>;
150 #size-cells = <1>; 148 #size-cells = <1>;
151 cell-index = <0>; 149 cell-index = <0>;
152 device_type = "network 150 device_type = "network";
153 model = "TSEC"; 151 model = "TSEC";
154 compatible = "gianfar" 152 compatible = "gianfar";
155 reg = <0x24000 0x1000> 153 reg = <0x24000 0x1000>;
156 ranges = <0x0 0x24000 154 ranges = <0x0 0x24000 0x1000>;
157 local-mac-address = [ 155 local-mac-address = [ 00 00 00 00 00 00 ];
158 interrupts = <29 2 30 156 interrupts = <29 2 30 2 34 2>;
159 interrupt-parent = <&m 157 interrupt-parent = <&mpic>;
160 tbi-handle = <&tbi0>; 158 tbi-handle = <&tbi0>;
161 phy-handle = <&phy2>; 159 phy-handle = <&phy2>;
162 160
163 mdio@520 { 161 mdio@520 {
164 #address-cells 162 #address-cells = <1>;
165 #size-cells = 163 #size-cells = <0>;
166 compatible = " 164 compatible = "fsl,gianfar-mdio";
167 reg = <0x520 0 165 reg = <0x520 0x20>;
168 166
169 phy1: ethernet 167 phy1: ethernet-phy@1 {
170 interr 168 interrupt-parent = <&mpic>;
171 interr 169 interrupts = <8 1>;
172 reg = 170 reg = <1>;
173 }; 171 };
174 phy2: ethernet 172 phy2: ethernet-phy@2 {
175 interr 173 interrupt-parent = <&mpic>;
176 interr 174 interrupts = <8 1>;
177 reg = 175 reg = <2>;
178 }; 176 };
179 phy3: ethernet 177 phy3: ethernet-phy@3 {
180 interr 178 interrupt-parent = <&mpic>;
181 interr 179 interrupts = <8 1>;
182 reg = 180 reg = <3>;
183 }; 181 };
184 tbi0: tbi-phy@ 182 tbi0: tbi-phy@11 {
185 reg = 183 reg = <0x11>;
186 device 184 device_type = "tbi-phy";
187 }; 185 };
188 }; 186 };
189 }; 187 };
190 188
191 enet1: ethernet@25000 { 189 enet1: ethernet@25000 {
192 #address-cells = <1>; 190 #address-cells = <1>;
193 #size-cells = <1>; 191 #size-cells = <1>;
194 cell-index = <1>; 192 cell-index = <1>;
195 device_type = "network 193 device_type = "network";
196 model = "TSEC"; 194 model = "TSEC";
197 compatible = "gianfar" 195 compatible = "gianfar";
198 reg = <0x25000 0x1000> 196 reg = <0x25000 0x1000>;
199 ranges = <0x0 0x25000 197 ranges = <0x0 0x25000 0x1000>;
200 local-mac-address = [ 198 local-mac-address = [ 00 00 00 00 00 00 ];
201 interrupts = <35 2 36 199 interrupts = <35 2 36 2 40 2>;
202 interrupt-parent = <&m 200 interrupt-parent = <&mpic>;
203 tbi-handle = <&tbi1>; 201 tbi-handle = <&tbi1>;
204 phy-handle = <&phy1>; 202 phy-handle = <&phy1>;
205 203
206 mdio@520 { 204 mdio@520 {
207 #address-cells 205 #address-cells = <1>;
208 #size-cells = 206 #size-cells = <0>;
209 compatible = " 207 compatible = "fsl,gianfar-tbi";
210 reg = <0x520 0 208 reg = <0x520 0x20>;
211 209
212 tbi1: tbi-phy@ 210 tbi1: tbi-phy@11 {
213 reg = 211 reg = <0x11>;
214 device 212 device_type = "tbi-phy";
215 }; 213 };
216 }; 214 };
217 }; 215 };
218 216
219 serial0: serial@4500 { 217 serial0: serial@4500 {
220 cell-index = <0>; 218 cell-index = <0>;
221 device_type = "serial" 219 device_type = "serial";
222 compatible = "fsl,ns16 220 compatible = "fsl,ns16550", "ns16550";
223 reg = <0x4500 0x100>; 221 reg = <0x4500 0x100>; // reg base, size
224 clock-frequency = <0>; 222 clock-frequency = <0>; // should we fill in in uboot?
225 interrupts = <42 2>; 223 interrupts = <42 2>;
226 interrupt-parent = <&m 224 interrupt-parent = <&mpic>;
227 }; 225 };
228 226
229 serial1: serial@4600 { 227 serial1: serial@4600 {
230 cell-index = <1>; 228 cell-index = <1>;
231 device_type = "serial" 229 device_type = "serial";
232 compatible = "fsl,ns16 230 compatible = "fsl,ns16550", "ns16550";
233 reg = <0x4600 0x100>; 231 reg = <0x4600 0x100>; // reg base, size
234 clock-frequency = <0>; 232 clock-frequency = <0>; // should we fill in in uboot?
235 interrupts = <42 2>; 233 interrupts = <42 2>;
236 interrupt-parent = <&m 234 interrupt-parent = <&mpic>;
237 }; 235 };
238 236
239 crypto@30000 { 237 crypto@30000 {
240 compatible = "fsl,sec2 238 compatible = "fsl,sec2.0";
241 reg = <0x30000 0x10000 239 reg = <0x30000 0x10000>;
242 interrupts = <45 2>; 240 interrupts = <45 2>;
243 interrupt-parent = <&m 241 interrupt-parent = <&mpic>;
244 fsl,num-channels = <4> 242 fsl,num-channels = <4>;
245 fsl,channel-fifo-len = 243 fsl,channel-fifo-len = <24>;
246 fsl,exec-units-mask = 244 fsl,exec-units-mask = <0x7e>;
247 fsl,descriptor-types-m 245 fsl,descriptor-types-mask = <0x01010ebf>;
248 }; 246 };
249 247
250 mpic: pic@40000 { 248 mpic: pic@40000 {
251 interrupt-controller; 249 interrupt-controller;
252 #address-cells = <0>; 250 #address-cells = <0>;
253 #interrupt-cells = <2> 251 #interrupt-cells = <2>;
254 reg = <0x40000 0x40000 252 reg = <0x40000 0x40000>;
255 device_type = "open-pi 253 device_type = "open-pic";
256 compatible = "chrp,ope 254 compatible = "chrp,open-pic";
257 }; 255 };
258 256
259 cpm@919c0 { 257 cpm@919c0 {
260 #address-cells = <1>; 258 #address-cells = <1>;
261 #size-cells = <1>; 259 #size-cells = <1>;
262 compatible = "fsl,mpc8 260 compatible = "fsl,mpc8541-cpm", "fsl,cpm2", "simple-bus";
263 reg = <0x919c0 0x30>; 261 reg = <0x919c0 0x30>;
264 ranges; 262 ranges;
265 263
266 muram@80000 { 264 muram@80000 {
267 #address-cells 265 #address-cells = <1>;
268 #size-cells = 266 #size-cells = <1>;
269 ranges = <0 0x 267 ranges = <0 0x80000 0x10000>;
270 268
271 data@0 { 269 data@0 {
272 compat 270 compatible = "fsl,cpm-muram-data";
273 reg = 271 reg = <0 0x2000 0x9000 0x1000>;
274 }; 272 };
275 }; 273 };
276 274
277 brg@919f0 { 275 brg@919f0 {
278 compatible = " 276 compatible = "fsl,mpc8541-brg",
279 " 277 "fsl,cpm2-brg",
280 " 278 "fsl,cpm-brg";
281 reg = <0x919f0 279 reg = <0x919f0 0x10 0x915f0 0x10>;
282 clock-frequenc 280 clock-frequency = <0>;
283 }; 281 };
284 282
285 cpmpic: pic@90c00 { 283 cpmpic: pic@90c00 {
286 interrupt-cont 284 interrupt-controller;
287 #address-cells 285 #address-cells = <0>;
288 #interrupt-cel 286 #interrupt-cells = <2>;
289 interrupts = < 287 interrupts = <46 2>;
290 interrupt-pare 288 interrupt-parent = <&mpic>;
291 reg = <0x90c00 289 reg = <0x90c00 0x80>;
292 compatible = " 290 compatible = "fsl,mpc8541-cpm-pic", "fsl,cpm2-pic";
293 }; 291 };
294 }; 292 };
295 }; 293 };
296 294
297 pci0: pci@e0008000 { 295 pci0: pci@e0008000 {
298 #interrupt-cells = <1>; 296 #interrupt-cells = <1>;
299 #size-cells = <2>; 297 #size-cells = <2>;
300 #address-cells = <3>; 298 #address-cells = <3>;
301 compatible = "fsl,mpc8540-pcix 299 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
302 device_type = "pci"; 300 device_type = "pci";
303 reg = <0xe0008000 0x1000>; 301 reg = <0xe0008000 0x1000>;
304 clock-frequency = <66666666>; 302 clock-frequency = <66666666>;
305 interrupt-map-mask = <0xf800 0 303 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
306 interrupt-map = < 304 interrupt-map = <
307 /* IDSEL 28 */ 305 /* IDSEL 28 */
308 0xe000 0 0 1 306 0xe000 0 0 1 &mpic 2 1
309 0xe000 0 0 2 307 0xe000 0 0 2 &mpic 3 1
310 0xe000 0 0 3 308 0xe000 0 0 3 &mpic 6 1
311 0xe000 0 0 4 309 0xe000 0 0 4 &mpic 5 1
312 310
313 /* IDSEL 11 */ 311 /* IDSEL 11 */
314 0x5800 0 0 1 312 0x5800 0 0 1 &mpic 6 1
315 0x5800 0 0 2 313 0x5800 0 0 2 &mpic 5 1
316 >; 314 >;
317 315
318 interrupt-parent = <&mpic>; 316 interrupt-parent = <&mpic>;
319 interrupts = <24 2>; 317 interrupts = <24 2>;
320 bus-range = <0 0>; 318 bus-range = <0 0>;
321 ranges = <0x02000000 0 0x80000 319 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
322 0x01000000 0 0x00000 320 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
323 }; 321 };
324 }; 322 };
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