1 // SPDX-License-Identifier: GPL-2.0-or-later <<
2 /* 1 /*
3 * TQM8548 Device Tree Source 2 * TQM8548 Device Tree Source
4 * 3 *
5 * Copyright 2006 Freescale Semiconductor Inc. 4 * Copyright 2006 Freescale Semiconductor Inc.
6 * Copyright 2008 Wolfgang Grandegger <wg@denx. 5 * Copyright 2008 Wolfgang Grandegger <wg@denx.de>
>> 6 *
>> 7 * This program is free software; you can redistribute it and/or modify it
>> 8 * under the terms of the GNU General Public License as published by the
>> 9 * Free Software Foundation; either version 2 of the License, or (at your
>> 10 * option) any later version.
7 */ 11 */
8 12
9 /dts-v1/; 13 /dts-v1/;
10 14
11 / { 15 / {
12 model = "tqc,tqm8548"; 16 model = "tqc,tqm8548";
13 compatible = "tqc,tqm8548"; 17 compatible = "tqc,tqm8548";
14 #address-cells = <1>; 18 #address-cells = <1>;
15 #size-cells = <1>; 19 #size-cells = <1>;
16 20
17 aliases { 21 aliases {
18 ethernet0 = &enet0; 22 ethernet0 = &enet0;
19 ethernet1 = &enet1; 23 ethernet1 = &enet1;
20 ethernet2 = &enet2; 24 ethernet2 = &enet2;
21 ethernet3 = &enet3; 25 ethernet3 = &enet3;
22 26
23 serial0 = &serial0; 27 serial0 = &serial0;
24 serial1 = &serial1; 28 serial1 = &serial1;
25 pci0 = &pci0; 29 pci0 = &pci0;
26 pci1 = &pci1; 30 pci1 = &pci1;
27 }; 31 };
28 32
29 cpus { 33 cpus {
30 #address-cells = <1>; 34 #address-cells = <1>;
31 #size-cells = <0>; 35 #size-cells = <0>;
32 36
33 PowerPC,8548@0 { 37 PowerPC,8548@0 {
34 device_type = "cpu"; 38 device_type = "cpu";
35 reg = <0>; 39 reg = <0>;
36 d-cache-line-size = <3 40 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <3 41 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <0x8000 42 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000 43 i-cache-size = <0x8000>; // L1, 32K
40 next-level-cache = <&L 44 next-level-cache = <&L2>;
41 }; 45 };
42 }; 46 };
43 47
44 memory { 48 memory {
45 device_type = "memory"; 49 device_type = "memory";
46 reg = <0x00000000 0x00000000>; 50 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
47 }; 51 };
48 52
49 soc@a0000000 { 53 soc@a0000000 {
50 #address-cells = <1>; 54 #address-cells = <1>;
51 #size-cells = <1>; 55 #size-cells = <1>;
52 device_type = "soc"; 56 device_type = "soc";
53 ranges = <0x0 0xa0000000 0x100 57 ranges = <0x0 0xa0000000 0x100000>;
54 bus-frequency = <0>; 58 bus-frequency = <0>;
55 compatible = "fsl,mpc8548-immr 59 compatible = "fsl,mpc8548-immr", "simple-bus";
56 60
57 ecm-law@0 { 61 ecm-law@0 {
58 compatible = "fsl,ecm- 62 compatible = "fsl,ecm-law";
59 reg = <0x0 0x1000>; 63 reg = <0x0 0x1000>;
60 fsl,num-laws = <10>; 64 fsl,num-laws = <10>;
61 }; 65 };
62 66
63 ecm@1000 { 67 ecm@1000 {
64 compatible = "fsl,mpc8 68 compatible = "fsl,mpc8548-ecm", "fsl,ecm";
65 reg = <0x1000 0x1000>; 69 reg = <0x1000 0x1000>;
66 interrupts = <17 2>; 70 interrupts = <17 2>;
67 interrupt-parent = <&m 71 interrupt-parent = <&mpic>;
68 }; 72 };
69 73
70 memory-controller@2000 { 74 memory-controller@2000 {
71 compatible = "fsl,mpc8 75 compatible = "fsl,mpc8548-memory-controller";
72 reg = <0x2000 0x1000>; 76 reg = <0x2000 0x1000>;
73 interrupt-parent = <&m 77 interrupt-parent = <&mpic>;
74 interrupts = <18 2>; 78 interrupts = <18 2>;
75 }; 79 };
76 80
77 L2: l2-cache-controller@20000 81 L2: l2-cache-controller@20000 {
78 compatible = "fsl,mpc8 82 compatible = "fsl,mpc8548-l2-cache-controller";
79 reg = <0x20000 0x1000> 83 reg = <0x20000 0x1000>;
80 cache-line-size = <32> 84 cache-line-size = <32>; // 32 bytes
81 cache-size = <0x80000> 85 cache-size = <0x80000>; // L2, 512K
82 interrupt-parent = <&m 86 interrupt-parent = <&mpic>;
83 interrupts = <16 2>; 87 interrupts = <16 2>;
84 }; 88 };
85 89
86 i2c@3000 { 90 i2c@3000 {
87 #address-cells = <1>; 91 #address-cells = <1>;
88 #size-cells = <0>; 92 #size-cells = <0>;
89 cell-index = <0>; 93 cell-index = <0>;
90 compatible = "fsl-i2c" 94 compatible = "fsl-i2c";
91 reg = <0x3000 0x100>; 95 reg = <0x3000 0x100>;
92 interrupts = <43 2>; 96 interrupts = <43 2>;
93 interrupt-parent = <&m 97 interrupt-parent = <&mpic>;
94 dfsrr; 98 dfsrr;
95 99
96 dtt@48 { 100 dtt@48 {
97 compatible = " 101 compatible = "national,lm75";
98 reg = <0x48>; 102 reg = <0x48>;
99 }; 103 };
100 104
101 rtc@68 { 105 rtc@68 {
102 compatible = " 106 compatible = "dallas,ds1337";
103 reg = <0x68>; 107 reg = <0x68>;
104 }; 108 };
105 }; 109 };
106 110
107 i2c@3100 { 111 i2c@3100 {
108 #address-cells = <1>; 112 #address-cells = <1>;
109 #size-cells = <0>; 113 #size-cells = <0>;
110 cell-index = <1>; 114 cell-index = <1>;
111 compatible = "fsl-i2c" 115 compatible = "fsl-i2c";
112 reg = <0x3100 0x100>; 116 reg = <0x3100 0x100>;
113 interrupts = <43 2>; 117 interrupts = <43 2>;
114 interrupt-parent = <&m 118 interrupt-parent = <&mpic>;
115 dfsrr; 119 dfsrr;
116 }; 120 };
117 121
118 dma@21300 { 122 dma@21300 {
119 #address-cells = <1>; 123 #address-cells = <1>;
120 #size-cells = <1>; 124 #size-cells = <1>;
121 compatible = "fsl,mpc8 125 compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
122 reg = <0x21300 0x4>; 126 reg = <0x21300 0x4>;
123 ranges = <0x0 0x21100 127 ranges = <0x0 0x21100 0x200>;
124 cell-index = <0>; 128 cell-index = <0>;
125 dma-channel@0 { 129 dma-channel@0 {
126 compatible = " 130 compatible = "fsl,mpc8548-dma-channel",
127 131 "fsl,eloplus-dma-channel";
128 reg = <0x0 0x8 132 reg = <0x0 0x80>;
129 cell-index = < 133 cell-index = <0>;
130 interrupt-pare 134 interrupt-parent = <&mpic>;
131 interrupts = < 135 interrupts = <20 2>;
132 }; 136 };
133 dma-channel@80 { 137 dma-channel@80 {
134 compatible = " 138 compatible = "fsl,mpc8548-dma-channel",
135 139 "fsl,eloplus-dma-channel";
136 reg = <0x80 0x 140 reg = <0x80 0x80>;
137 cell-index = < 141 cell-index = <1>;
138 interrupt-pare 142 interrupt-parent = <&mpic>;
139 interrupts = < 143 interrupts = <21 2>;
140 }; 144 };
141 dma-channel@100 { 145 dma-channel@100 {
142 compatible = " 146 compatible = "fsl,mpc8548-dma-channel",
143 147 "fsl,eloplus-dma-channel";
144 reg = <0x100 0 148 reg = <0x100 0x80>;
145 cell-index = < 149 cell-index = <2>;
146 interrupt-pare 150 interrupt-parent = <&mpic>;
147 interrupts = < 151 interrupts = <22 2>;
148 }; 152 };
149 dma-channel@180 { 153 dma-channel@180 {
150 compatible = " 154 compatible = "fsl,mpc8548-dma-channel",
151 155 "fsl,eloplus-dma-channel";
152 reg = <0x180 0 156 reg = <0x180 0x80>;
153 cell-index = < 157 cell-index = <3>;
154 interrupt-pare 158 interrupt-parent = <&mpic>;
155 interrupts = < 159 interrupts = <23 2>;
156 }; 160 };
157 }; 161 };
158 162
159 enet0: ethernet@24000 { 163 enet0: ethernet@24000 {
160 #address-cells = <1>; 164 #address-cells = <1>;
161 #size-cells = <1>; 165 #size-cells = <1>;
162 cell-index = <0>; 166 cell-index = <0>;
163 device_type = "network 167 device_type = "network";
164 model = "eTSEC"; 168 model = "eTSEC";
165 compatible = "gianfar" 169 compatible = "gianfar";
166 reg = <0x24000 0x1000> 170 reg = <0x24000 0x1000>;
167 ranges = <0x0 0x24000 171 ranges = <0x0 0x24000 0x1000>;
168 local-mac-address = [ 172 local-mac-address = [ 00 00 00 00 00 00 ];
169 interrupts = <29 2 30 173 interrupts = <29 2 30 2 34 2>;
170 interrupt-parent = <&m 174 interrupt-parent = <&mpic>;
171 tbi-handle = <&tbi0>; 175 tbi-handle = <&tbi0>;
172 phy-handle = <&phy2>; 176 phy-handle = <&phy2>;
173 177
174 mdio@520 { 178 mdio@520 {
175 #address-cells 179 #address-cells = <1>;
176 #size-cells = 180 #size-cells = <0>;
177 compatible = " 181 compatible = "fsl,gianfar-mdio";
178 reg = <0x520 0 182 reg = <0x520 0x20>;
179 183
180 phy1: ethernet 184 phy1: ethernet-phy@0 {
181 interr 185 interrupt-parent = <&mpic>;
182 interr 186 interrupts = <8 1>;
183 reg = 187 reg = <1>;
184 }; 188 };
185 phy2: ethernet 189 phy2: ethernet-phy@1 {
186 interr 190 interrupt-parent = <&mpic>;
187 interr 191 interrupts = <8 1>;
188 reg = 192 reg = <2>;
189 }; 193 };
190 phy3: ethernet 194 phy3: ethernet-phy@3 {
191 interr 195 interrupt-parent = <&mpic>;
192 interr 196 interrupts = <8 1>;
193 reg = 197 reg = <3>;
194 }; 198 };
195 phy4: ethernet 199 phy4: ethernet-phy@4 {
196 interr 200 interrupt-parent = <&mpic>;
197 interr 201 interrupts = <8 1>;
198 reg = 202 reg = <4>;
199 }; 203 };
200 phy5: ethernet 204 phy5: ethernet-phy@5 {
201 interr 205 interrupt-parent = <&mpic>;
202 interr 206 interrupts = <8 1>;
203 reg = 207 reg = <5>;
204 }; 208 };
205 tbi0: tbi-phy@ 209 tbi0: tbi-phy@11 {
206 reg = 210 reg = <0x11>;
207 device 211 device_type = "tbi-phy";
208 }; 212 };
209 }; 213 };
210 }; 214 };
211 215
212 enet1: ethernet@25000 { 216 enet1: ethernet@25000 {
213 #address-cells = <1>; 217 #address-cells = <1>;
214 #size-cells = <1>; 218 #size-cells = <1>;
215 cell-index = <1>; 219 cell-index = <1>;
216 device_type = "network 220 device_type = "network";
217 model = "eTSEC"; 221 model = "eTSEC";
218 compatible = "gianfar" 222 compatible = "gianfar";
219 reg = <0x25000 0x1000> 223 reg = <0x25000 0x1000>;
220 ranges = <0x0 0x25000 224 ranges = <0x0 0x25000 0x1000>;
221 local-mac-address = [ 225 local-mac-address = [ 00 00 00 00 00 00 ];
222 interrupts = <35 2 36 226 interrupts = <35 2 36 2 40 2>;
223 interrupt-parent = <&m 227 interrupt-parent = <&mpic>;
224 tbi-handle = <&tbi1>; 228 tbi-handle = <&tbi1>;
225 phy-handle = <&phy1>; 229 phy-handle = <&phy1>;
226 230
227 mdio@520 { 231 mdio@520 {
228 #address-cells 232 #address-cells = <1>;
229 #size-cells = 233 #size-cells = <0>;
230 compatible = " 234 compatible = "fsl,gianfar-tbi";
231 reg = <0x520 0 235 reg = <0x520 0x20>;
232 236
233 tbi1: tbi-phy@ 237 tbi1: tbi-phy@11 {
234 reg = 238 reg = <0x11>;
235 device 239 device_type = "tbi-phy";
236 }; 240 };
237 }; 241 };
238 }; 242 };
239 243
240 enet2: ethernet@26000 { 244 enet2: ethernet@26000 {
241 #address-cells = <1>; 245 #address-cells = <1>;
242 #size-cells = <1>; 246 #size-cells = <1>;
243 cell-index = <2>; 247 cell-index = <2>;
244 device_type = "network 248 device_type = "network";
245 model = "eTSEC"; 249 model = "eTSEC";
246 compatible = "gianfar" 250 compatible = "gianfar";
247 reg = <0x26000 0x1000> 251 reg = <0x26000 0x1000>;
248 ranges = <0x0 0x26000 252 ranges = <0x0 0x26000 0x1000>;
249 local-mac-address = [ 253 local-mac-address = [ 00 00 00 00 00 00 ];
250 interrupts = <31 2 32 254 interrupts = <31 2 32 2 33 2>;
251 interrupt-parent = <&m 255 interrupt-parent = <&mpic>;
252 tbi-handle = <&tbi2>; 256 tbi-handle = <&tbi2>;
253 phy-handle = <&phy4>; 257 phy-handle = <&phy4>;
254 258
255 mdio@520 { 259 mdio@520 {
256 #address-cells 260 #address-cells = <1>;
257 #size-cells = 261 #size-cells = <0>;
258 compatible = " 262 compatible = "fsl,gianfar-tbi";
259 reg = <0x520 0 263 reg = <0x520 0x20>;
260 264
261 tbi2: tbi-phy@ 265 tbi2: tbi-phy@11 {
262 reg = 266 reg = <0x11>;
263 device 267 device_type = "tbi-phy";
264 }; 268 };
265 }; 269 };
266 }; 270 };
267 271
268 enet3: ethernet@27000 { 272 enet3: ethernet@27000 {
269 #address-cells = <1>; 273 #address-cells = <1>;
270 #size-cells = <1>; 274 #size-cells = <1>;
271 cell-index = <3>; 275 cell-index = <3>;
272 device_type = "network 276 device_type = "network";
273 model = "eTSEC"; 277 model = "eTSEC";
274 compatible = "gianfar" 278 compatible = "gianfar";
275 reg = <0x27000 0x1000> 279 reg = <0x27000 0x1000>;
276 ranges = <0x0 0x27000 280 ranges = <0x0 0x27000 0x1000>;
277 local-mac-address = [ 281 local-mac-address = [ 00 00 00 00 00 00 ];
278 interrupts = <37 2 38 282 interrupts = <37 2 38 2 39 2>;
279 interrupt-parent = <&m 283 interrupt-parent = <&mpic>;
280 tbi-handle = <&tbi3>; 284 tbi-handle = <&tbi3>;
281 phy-handle = <&phy5>; 285 phy-handle = <&phy5>;
282 286
283 mdio@520 { 287 mdio@520 {
284 #address-cells 288 #address-cells = <1>;
285 #size-cells = 289 #size-cells = <0>;
286 compatible = " 290 compatible = "fsl,gianfar-tbi";
287 reg = <0x520 0 291 reg = <0x520 0x20>;
288 292
289 tbi3: tbi-phy@ 293 tbi3: tbi-phy@11 {
290 reg = 294 reg = <0x11>;
291 device 295 device_type = "tbi-phy";
292 }; 296 };
293 }; 297 };
294 }; 298 };
295 299
296 serial0: serial@4500 { 300 serial0: serial@4500 {
297 cell-index = <0>; 301 cell-index = <0>;
298 device_type = "serial" 302 device_type = "serial";
299 compatible = "fsl,ns16 303 compatible = "fsl,ns16550", "ns16550";
300 reg = <0x4500 0x100>; 304 reg = <0x4500 0x100>; // reg base, size
301 clock-frequency = <0>; 305 clock-frequency = <0>; // should we fill in in uboot?
302 current-speed = <11520 306 current-speed = <115200>;
303 interrupts = <42 2>; 307 interrupts = <42 2>;
304 interrupt-parent = <&m 308 interrupt-parent = <&mpic>;
305 }; 309 };
306 310
307 serial1: serial@4600 { 311 serial1: serial@4600 {
308 cell-index = <1>; 312 cell-index = <1>;
309 device_type = "serial" 313 device_type = "serial";
310 compatible = "fsl,ns16 314 compatible = "fsl,ns16550", "ns16550";
311 reg = <0x4600 0x100>; 315 reg = <0x4600 0x100>; // reg base, size
312 clock-frequency = <0>; 316 clock-frequency = <0>; // should we fill in in uboot?
313 current-speed = <11520 317 current-speed = <115200>;
314 interrupts = <42 2>; 318 interrupts = <42 2>;
315 interrupt-parent = <&m 319 interrupt-parent = <&mpic>;
316 }; 320 };
317 321
318 global-utilities@e0000 { 322 global-utilities@e0000 { // global utilities reg
319 compatible = "fsl,mpc8 323 compatible = "fsl,mpc8548-guts";
320 reg = <0xe0000 0x1000> 324 reg = <0xe0000 0x1000>;
321 fsl,has-rstcr; 325 fsl,has-rstcr;
322 }; 326 };
323 327
324 mpic: pic@40000 { 328 mpic: pic@40000 {
325 interrupt-controller; 329 interrupt-controller;
326 #address-cells = <0>; 330 #address-cells = <0>;
327 #interrupt-cells = <2> 331 #interrupt-cells = <2>;
328 reg = <0x40000 0x40000 332 reg = <0x40000 0x40000>;
329 compatible = "chrp,ope 333 compatible = "chrp,open-pic";
330 device_type = "open-pi 334 device_type = "open-pic";
331 }; 335 };
332 }; 336 };
333 337
334 localbus@a0005000 { 338 localbus@a0005000 {
335 compatible = "fsl,mpc8548-loca 339 compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
336 "simple-bus"; 340 "simple-bus";
337 #address-cells = <2>; 341 #address-cells = <2>;
338 #size-cells = <1>; 342 #size-cells = <1>;
339 reg = <0xa0005000 0x100>; 343 reg = <0xa0005000 0x100>; // BRx, ORx, etc.
340 interrupt-parent = <&mpic>; 344 interrupt-parent = <&mpic>;
341 interrupts = <19 2>; 345 interrupts = <19 2>;
342 346
343 ranges = < 347 ranges = <
344 0 0x0 0xfc000000 0x040 348 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
345 1 0x0 0xf8000000 0x080 349 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0
346 2 0x0 0xa3000000 0x000 350 2 0x0 0xa3000000 0x00008000 // CAN (2 x CC770)
347 3 0x0 0xa3010000 0x000 351 3 0x0 0xa3010000 0x00008000 // NAND FLASH
348 352
349 >; 353 >;
350 354
351 flash@1,0 { 355 flash@1,0 {
352 #address-cells = <1>; 356 #address-cells = <1>;
353 #size-cells = <1>; 357 #size-cells = <1>;
354 compatible = "cfi-flas 358 compatible = "cfi-flash";
355 reg = <1 0x0 0x8000000 359 reg = <1 0x0 0x8000000>;
356 bank-width = <4>; 360 bank-width = <4>;
357 device-width = <1>; 361 device-width = <1>;
358 362
359 partition@0 { 363 partition@0 {
360 label = "kerne 364 label = "kernel";
361 reg = <0x00000 365 reg = <0x00000000 0x00200000>;
362 }; 366 };
363 partition@200000 { 367 partition@200000 {
364 label = "root" 368 label = "root";
365 reg = <0x00200 369 reg = <0x00200000 0x00300000>;
366 }; 370 };
367 partition@500000 { 371 partition@500000 {
368 label = "user" 372 label = "user";
369 reg = <0x00500 373 reg = <0x00500000 0x07a00000>;
370 }; 374 };
371 partition@7f00000 { 375 partition@7f00000 {
372 label = "env1" 376 label = "env1";
373 reg = <0x07f00 377 reg = <0x07f00000 0x00040000>;
374 }; 378 };
375 partition@7f40000 { 379 partition@7f40000 {
376 label = "env2" 380 label = "env2";
377 reg = <0x07f40 381 reg = <0x07f40000 0x00040000>;
378 }; 382 };
379 partition@7f80000 { 383 partition@7f80000 {
380 label = "u-boo 384 label = "u-boot";
381 reg = <0x07f80 385 reg = <0x07f80000 0x00080000>;
382 read-only; 386 read-only;
383 }; 387 };
384 }; 388 };
385 389
386 /* Note: CAN support needs be 390 /* Note: CAN support needs be enabled in U-Boot */
387 can@2,0 { 391 can@2,0 {
388 compatible = "bosch,cc 392 compatible = "bosch,cc770"; // Bosch CC770
389 reg = <2 0x0 0x100>; 393 reg = <2 0x0 0x100>;
390 interrupts = <4 1>; 394 interrupts = <4 1>;
391 interrupt-parent = <&m 395 interrupt-parent = <&mpic>;
392 bosch,external-clock-f 396 bosch,external-clock-frequency = <16000000>;
393 bosch,disconnect-rx1-i 397 bosch,disconnect-rx1-input;
394 bosch,disconnect-tx1-o 398 bosch,disconnect-tx1-output;
395 bosch,iso-low-speed-mu 399 bosch,iso-low-speed-mux;
396 bosch,clock-out-freque 400 bosch,clock-out-frequency = <16000000>;
397 }; 401 };
398 402
399 can@2,100 { 403 can@2,100 {
400 compatible = "bosch,cc 404 compatible = "bosch,cc770"; // Bosch CC770
401 reg = <2 0x100 0x100>; 405 reg = <2 0x100 0x100>;
402 interrupts = <4 1>; 406 interrupts = <4 1>;
403 interrupt-parent = <&m 407 interrupt-parent = <&mpic>;
404 bosch,external-clock-f 408 bosch,external-clock-frequency = <16000000>;
405 bosch,disconnect-rx1-i 409 bosch,disconnect-rx1-input;
406 bosch,disconnect-tx1-o 410 bosch,disconnect-tx1-output;
407 bosch,iso-low-speed-mu 411 bosch,iso-low-speed-mux;
408 }; 412 };
409 413
410 /* Note: NAND support needs to 414 /* Note: NAND support needs to be enabled in U-Boot */
411 upm@3,0 { 415 upm@3,0 {
412 #address-cells = <0>; 416 #address-cells = <0>;
413 #size-cells = <0>; 417 #size-cells = <0>;
414 compatible = "tqc,tqm8 418 compatible = "tqc,tqm8548-upm-nand", "fsl,upm-nand";
415 reg = <3 0x0 0x800>; 419 reg = <3 0x0 0x800>;
416 fsl,upm-addr-offset = 420 fsl,upm-addr-offset = <0x10>;
417 fsl,upm-cmd-offset = < 421 fsl,upm-cmd-offset = <0x08>;
418 /* Micron MT29F8G08FAB 422 /* Micron MT29F8G08FAB multi-chip device */
419 fsl,upm-addr-line-cs-o 423 fsl,upm-addr-line-cs-offsets = <0x0 0x200>;
420 fsl,upm-wait-flags = < 424 fsl,upm-wait-flags = <0x5>;
421 chip-delay = <25>; // 425 chip-delay = <25>; // in micro-seconds
422 426
423 nand@0 { 427 nand@0 {
424 #address-cells 428 #address-cells = <1>;
425 #size-cells = 429 #size-cells = <1>;
426 430
427 partition@0 { 431 partition@0 {
428 la 432 label = "fs";
429 re 433 reg = <0x00000000 0x10000000>;
430 }; 434 };
431 }; 435 };
432 }; 436 };
433 }; 437 };
434 438
435 pci0: pci@a0008000 { 439 pci0: pci@a0008000 {
436 #interrupt-cells = <1>; 440 #interrupt-cells = <1>;
437 #size-cells = <2>; 441 #size-cells = <2>;
438 #address-cells = <3>; 442 #address-cells = <3>;
439 compatible = "fsl,mpc8540-pcix 443 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
440 device_type = "pci"; 444 device_type = "pci";
441 reg = <0xa0008000 0x1000>; 445 reg = <0xa0008000 0x1000>;
442 clock-frequency = <33333333>; 446 clock-frequency = <33333333>;
443 interrupt-map-mask = <0xf800 0 447 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
444 interrupt-map = < 448 interrupt-map = <
445 /* IDSEL 28 */ 449 /* IDSEL 28 */
446 0xe000 0 0 1 450 0xe000 0 0 1 &mpic 2 1
447 0xe000 0 0 2 451 0xe000 0 0 2 &mpic 3 1
448 0xe000 0 0 3 452 0xe000 0 0 3 &mpic 6 1
449 0xe000 0 0 4 453 0xe000 0 0 4 &mpic 5 1
450 454
451 /* IDSEL 11 */ 455 /* IDSEL 11 */
452 0x5800 0 0 1 456 0x5800 0 0 1 &mpic 6 1
453 0x5800 0 0 2 457 0x5800 0 0 2 &mpic 5 1
454 >; 458 >;
455 459
456 interrupt-parent = <&mpic>; 460 interrupt-parent = <&mpic>;
457 interrupts = <24 2>; 461 interrupts = <24 2>;
458 bus-range = <0 0>; 462 bus-range = <0 0>;
459 ranges = <0x02000000 0 0x80000 463 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
460 0x01000000 0 0x00000 464 0x01000000 0 0x00000000 0xa2000000 0 0x01000000>;
461 }; 465 };
462 466
463 pci1: pcie@a000a000 { 467 pci1: pcie@a000a000 {
464 interrupt-map-mask = <0xf800 0 468 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
465 interrupt-map = < 469 interrupt-map = <
466 /* IDSEL 0x0 (PEX) */ 470 /* IDSEL 0x0 (PEX) */
467 0x00000 0 0 1 &mpic 0 471 0x00000 0 0 1 &mpic 0 1
468 0x00000 0 0 2 &mpic 1 472 0x00000 0 0 2 &mpic 1 1
469 0x00000 0 0 3 &mpic 2 473 0x00000 0 0 3 &mpic 2 1
470 0x00000 0 0 4 &mpic 3 474 0x00000 0 0 4 &mpic 3 1>;
471 475
472 interrupt-parent = <&mpic>; 476 interrupt-parent = <&mpic>;
473 interrupts = <26 2>; 477 interrupts = <26 2>;
474 bus-range = <0 0xff>; 478 bus-range = <0 0xff>;
475 ranges = <0x02000000 0 0xb0000 479 ranges = <0x02000000 0 0xb0000000 0xb0000000 0 0x10000000
476 0x01000000 0 0x00000 480 0x01000000 0 0x00000000 0xaf000000 0 0x08000000>;
477 clock-frequency = <33333333>; 481 clock-frequency = <33333333>;
478 #interrupt-cells = <1>; 482 #interrupt-cells = <1>;
479 #size-cells = <2>; 483 #size-cells = <2>;
480 #address-cells = <3>; 484 #address-cells = <3>;
481 reg = <0xa000a000 0x1000>; 485 reg = <0xa000a000 0x1000>;
482 compatible = "fsl,mpc8548-pcie 486 compatible = "fsl,mpc8548-pcie";
483 device_type = "pci"; 487 device_type = "pci";
484 pcie@0 { 488 pcie@0 {
485 reg = <0 0 0 0 0>; 489 reg = <0 0 0 0 0>;
486 #size-cells = <2>; 490 #size-cells = <2>;
487 #address-cells = <3>; 491 #address-cells = <3>;
488 device_type = "pci"; 492 device_type = "pci";
489 ranges = <0x02000000 0 493 ranges = <0x02000000 0 0xb0000000 0x02000000 0
490 0xb0000000 0 494 0xb0000000 0 0x10000000
491 0x01000000 0 495 0x01000000 0 0x00000000 0x01000000 0
492 0x00000000 0 496 0x00000000 0 0x08000000>;
493 }; 497 };
494 }; 498 };
495 }; 499 };
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