1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * TQM8548 Device Tree Source
4 *
5 * Copyright 2006 Freescale Semiconductor Inc.
6 * Copyright 2008 Wolfgang Grandegger <wg@denx.
7 */
8
9 /dts-v1/;
10
11 / {
12 model = "tqc,tqm8548";
13 compatible = "tqc,tqm8548";
14 #address-cells = <1>;
15 #size-cells = <1>;
16
17 aliases {
18 ethernet0 = &enet0;
19 ethernet1 = &enet1;
20 ethernet2 = &enet2;
21 ethernet3 = &enet3;
22
23 serial0 = &serial0;
24 serial1 = &serial1;
25 pci0 = &pci0;
26 pci1 = &pci1;
27 };
28
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 PowerPC,8548@0 {
34 device_type = "cpu";
35 reg = <0>;
36 d-cache-line-size = <3
37 i-cache-line-size = <3
38 d-cache-size = <0x8000
39 i-cache-size = <0x8000
40 next-level-cache = <&L
41 };
42 };
43
44 memory {
45 device_type = "memory";
46 reg = <0x00000000 0x00000000>;
47 };
48
49 soc@a0000000 {
50 #address-cells = <1>;
51 #size-cells = <1>;
52 device_type = "soc";
53 ranges = <0x0 0xa0000000 0x100
54 bus-frequency = <0>;
55 compatible = "fsl,mpc8548-immr
56
57 ecm-law@0 {
58 compatible = "fsl,ecm-
59 reg = <0x0 0x1000>;
60 fsl,num-laws = <10>;
61 };
62
63 ecm@1000 {
64 compatible = "fsl,mpc8
65 reg = <0x1000 0x1000>;
66 interrupts = <17 2>;
67 interrupt-parent = <&m
68 };
69
70 memory-controller@2000 {
71 compatible = "fsl,mpc8
72 reg = <0x2000 0x1000>;
73 interrupt-parent = <&m
74 interrupts = <18 2>;
75 };
76
77 L2: l2-cache-controller@20000
78 compatible = "fsl,mpc8
79 reg = <0x20000 0x1000>
80 cache-line-size = <32>
81 cache-size = <0x80000>
82 interrupt-parent = <&m
83 interrupts = <16 2>;
84 };
85
86 i2c@3000 {
87 #address-cells = <1>;
88 #size-cells = <0>;
89 cell-index = <0>;
90 compatible = "fsl-i2c"
91 reg = <0x3000 0x100>;
92 interrupts = <43 2>;
93 interrupt-parent = <&m
94 dfsrr;
95
96 dtt@48 {
97 compatible = "
98 reg = <0x48>;
99 };
100
101 rtc@68 {
102 compatible = "
103 reg = <0x68>;
104 };
105 };
106
107 i2c@3100 {
108 #address-cells = <1>;
109 #size-cells = <0>;
110 cell-index = <1>;
111 compatible = "fsl-i2c"
112 reg = <0x3100 0x100>;
113 interrupts = <43 2>;
114 interrupt-parent = <&m
115 dfsrr;
116 };
117
118 dma@21300 {
119 #address-cells = <1>;
120 #size-cells = <1>;
121 compatible = "fsl,mpc8
122 reg = <0x21300 0x4>;
123 ranges = <0x0 0x21100
124 cell-index = <0>;
125 dma-channel@0 {
126 compatible = "
127
128 reg = <0x0 0x8
129 cell-index = <
130 interrupt-pare
131 interrupts = <
132 };
133 dma-channel@80 {
134 compatible = "
135
136 reg = <0x80 0x
137 cell-index = <
138 interrupt-pare
139 interrupts = <
140 };
141 dma-channel@100 {
142 compatible = "
143
144 reg = <0x100 0
145 cell-index = <
146 interrupt-pare
147 interrupts = <
148 };
149 dma-channel@180 {
150 compatible = "
151
152 reg = <0x180 0
153 cell-index = <
154 interrupt-pare
155 interrupts = <
156 };
157 };
158
159 enet0: ethernet@24000 {
160 #address-cells = <1>;
161 #size-cells = <1>;
162 cell-index = <0>;
163 device_type = "network
164 model = "eTSEC";
165 compatible = "gianfar"
166 reg = <0x24000 0x1000>
167 ranges = <0x0 0x24000
168 local-mac-address = [
169 interrupts = <29 2 30
170 interrupt-parent = <&m
171 tbi-handle = <&tbi0>;
172 phy-handle = <&phy2>;
173
174 mdio@520 {
175 #address-cells
176 #size-cells =
177 compatible = "
178 reg = <0x520 0
179
180 phy1: ethernet
181 interr
182 interr
183 reg =
184 };
185 phy2: ethernet
186 interr
187 interr
188 reg =
189 };
190 phy3: ethernet
191 interr
192 interr
193 reg =
194 };
195 phy4: ethernet
196 interr
197 interr
198 reg =
199 };
200 phy5: ethernet
201 interr
202 interr
203 reg =
204 };
205 tbi0: tbi-phy@
206 reg =
207 device
208 };
209 };
210 };
211
212 enet1: ethernet@25000 {
213 #address-cells = <1>;
214 #size-cells = <1>;
215 cell-index = <1>;
216 device_type = "network
217 model = "eTSEC";
218 compatible = "gianfar"
219 reg = <0x25000 0x1000>
220 ranges = <0x0 0x25000
221 local-mac-address = [
222 interrupts = <35 2 36
223 interrupt-parent = <&m
224 tbi-handle = <&tbi1>;
225 phy-handle = <&phy1>;
226
227 mdio@520 {
228 #address-cells
229 #size-cells =
230 compatible = "
231 reg = <0x520 0
232
233 tbi1: tbi-phy@
234 reg =
235 device
236 };
237 };
238 };
239
240 enet2: ethernet@26000 {
241 #address-cells = <1>;
242 #size-cells = <1>;
243 cell-index = <2>;
244 device_type = "network
245 model = "eTSEC";
246 compatible = "gianfar"
247 reg = <0x26000 0x1000>
248 ranges = <0x0 0x26000
249 local-mac-address = [
250 interrupts = <31 2 32
251 interrupt-parent = <&m
252 tbi-handle = <&tbi2>;
253 phy-handle = <&phy4>;
254
255 mdio@520 {
256 #address-cells
257 #size-cells =
258 compatible = "
259 reg = <0x520 0
260
261 tbi2: tbi-phy@
262 reg =
263 device
264 };
265 };
266 };
267
268 enet3: ethernet@27000 {
269 #address-cells = <1>;
270 #size-cells = <1>;
271 cell-index = <3>;
272 device_type = "network
273 model = "eTSEC";
274 compatible = "gianfar"
275 reg = <0x27000 0x1000>
276 ranges = <0x0 0x27000
277 local-mac-address = [
278 interrupts = <37 2 38
279 interrupt-parent = <&m
280 tbi-handle = <&tbi3>;
281 phy-handle = <&phy5>;
282
283 mdio@520 {
284 #address-cells
285 #size-cells =
286 compatible = "
287 reg = <0x520 0
288
289 tbi3: tbi-phy@
290 reg =
291 device
292 };
293 };
294 };
295
296 serial0: serial@4500 {
297 cell-index = <0>;
298 device_type = "serial"
299 compatible = "fsl,ns16
300 reg = <0x4500 0x100>;
301 clock-frequency = <0>;
302 current-speed = <11520
303 interrupts = <42 2>;
304 interrupt-parent = <&m
305 };
306
307 serial1: serial@4600 {
308 cell-index = <1>;
309 device_type = "serial"
310 compatible = "fsl,ns16
311 reg = <0x4600 0x100>;
312 clock-frequency = <0>;
313 current-speed = <11520
314 interrupts = <42 2>;
315 interrupt-parent = <&m
316 };
317
318 global-utilities@e0000 {
319 compatible = "fsl,mpc8
320 reg = <0xe0000 0x1000>
321 fsl,has-rstcr;
322 };
323
324 mpic: pic@40000 {
325 interrupt-controller;
326 #address-cells = <0>;
327 #interrupt-cells = <2>
328 reg = <0x40000 0x40000
329 compatible = "chrp,ope
330 device_type = "open-pi
331 };
332 };
333
334 localbus@a0005000 {
335 compatible = "fsl,mpc8548-loca
336 "simple-bus";
337 #address-cells = <2>;
338 #size-cells = <1>;
339 reg = <0xa0005000 0x100>;
340 interrupt-parent = <&mpic>;
341 interrupts = <19 2>;
342
343 ranges = <
344 0 0x0 0xfc000000 0x040
345 1 0x0 0xf8000000 0x080
346 2 0x0 0xa3000000 0x000
347 3 0x0 0xa3010000 0x000
348
349 >;
350
351 flash@1,0 {
352 #address-cells = <1>;
353 #size-cells = <1>;
354 compatible = "cfi-flas
355 reg = <1 0x0 0x8000000
356 bank-width = <4>;
357 device-width = <1>;
358
359 partition@0 {
360 label = "kerne
361 reg = <0x00000
362 };
363 partition@200000 {
364 label = "root"
365 reg = <0x00200
366 };
367 partition@500000 {
368 label = "user"
369 reg = <0x00500
370 };
371 partition@7f00000 {
372 label = "env1"
373 reg = <0x07f00
374 };
375 partition@7f40000 {
376 label = "env2"
377 reg = <0x07f40
378 };
379 partition@7f80000 {
380 label = "u-boo
381 reg = <0x07f80
382 read-only;
383 };
384 };
385
386 /* Note: CAN support needs be
387 can@2,0 {
388 compatible = "bosch,cc
389 reg = <2 0x0 0x100>;
390 interrupts = <4 1>;
391 interrupt-parent = <&m
392 bosch,external-clock-f
393 bosch,disconnect-rx1-i
394 bosch,disconnect-tx1-o
395 bosch,iso-low-speed-mu
396 bosch,clock-out-freque
397 };
398
399 can@2,100 {
400 compatible = "bosch,cc
401 reg = <2 0x100 0x100>;
402 interrupts = <4 1>;
403 interrupt-parent = <&m
404 bosch,external-clock-f
405 bosch,disconnect-rx1-i
406 bosch,disconnect-tx1-o
407 bosch,iso-low-speed-mu
408 };
409
410 /* Note: NAND support needs to
411 upm@3,0 {
412 #address-cells = <0>;
413 #size-cells = <0>;
414 compatible = "tqc,tqm8
415 reg = <3 0x0 0x800>;
416 fsl,upm-addr-offset =
417 fsl,upm-cmd-offset = <
418 /* Micron MT29F8G08FAB
419 fsl,upm-addr-line-cs-o
420 fsl,upm-wait-flags = <
421 chip-delay = <25>; //
422
423 nand@0 {
424 #address-cells
425 #size-cells =
426
427 partition@0 {
428 la
429 re
430 };
431 };
432 };
433 };
434
435 pci0: pci@a0008000 {
436 #interrupt-cells = <1>;
437 #size-cells = <2>;
438 #address-cells = <3>;
439 compatible = "fsl,mpc8540-pcix
440 device_type = "pci";
441 reg = <0xa0008000 0x1000>;
442 clock-frequency = <33333333>;
443 interrupt-map-mask = <0xf800 0
444 interrupt-map = <
445 /* IDSEL 28 */
446 0xe000 0 0 1
447 0xe000 0 0 2
448 0xe000 0 0 3
449 0xe000 0 0 4
450
451 /* IDSEL 11 */
452 0x5800 0 0 1
453 0x5800 0 0 2
454 >;
455
456 interrupt-parent = <&mpic>;
457 interrupts = <24 2>;
458 bus-range = <0 0>;
459 ranges = <0x02000000 0 0x80000
460 0x01000000 0 0x00000
461 };
462
463 pci1: pcie@a000a000 {
464 interrupt-map-mask = <0xf800 0
465 interrupt-map = <
466 /* IDSEL 0x0 (PEX) */
467 0x00000 0 0 1 &mpic 0
468 0x00000 0 0 2 &mpic 1
469 0x00000 0 0 3 &mpic 2
470 0x00000 0 0 4 &mpic 3
471
472 interrupt-parent = <&mpic>;
473 interrupts = <26 2>;
474 bus-range = <0 0xff>;
475 ranges = <0x02000000 0 0xb0000
476 0x01000000 0 0x00000
477 clock-frequency = <33333333>;
478 #interrupt-cells = <1>;
479 #size-cells = <2>;
480 #address-cells = <3>;
481 reg = <0xa000a000 0x1000>;
482 compatible = "fsl,mpc8548-pcie
483 device_type = "pci";
484 pcie@0 {
485 reg = <0 0 0 0 0>;
486 #size-cells = <2>;
487 #address-cells = <3>;
488 device_type = "pci";
489 ranges = <0x02000000 0
490 0xb0000000 0
491 0x01000000 0
492 0x00000000 0
493 };
494 };
495 };
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