1 // SPDX-License-Identifier: GPL-2.0-or-later 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* 2 /*
3 * TQM8548 Device Tree Source 3 * TQM8548 Device Tree Source
4 * 4 *
5 * Copyright 2006 Freescale Semiconductor Inc. 5 * Copyright 2006 Freescale Semiconductor Inc.
6 * Copyright 2008 Wolfgang Grandegger <wg@denx. 6 * Copyright 2008 Wolfgang Grandegger <wg@denx.de>
7 */ 7 */
8 8
9 /dts-v1/; 9 /dts-v1/;
10 10
11 / { 11 / {
12 model = "tqc,tqm8548"; 12 model = "tqc,tqm8548";
13 compatible = "tqc,tqm8548"; 13 compatible = "tqc,tqm8548";
14 #address-cells = <1>; 14 #address-cells = <1>;
15 #size-cells = <1>; 15 #size-cells = <1>;
16 16
17 aliases { 17 aliases {
18 ethernet0 = &enet0; 18 ethernet0 = &enet0;
19 ethernet1 = &enet1; 19 ethernet1 = &enet1;
20 ethernet2 = &enet2; 20 ethernet2 = &enet2;
21 ethernet3 = &enet3; 21 ethernet3 = &enet3;
22 22
23 serial0 = &serial0; 23 serial0 = &serial0;
24 serial1 = &serial1; 24 serial1 = &serial1;
25 pci0 = &pci0; 25 pci0 = &pci0;
26 pci1 = &pci1; 26 pci1 = &pci1;
27 }; 27 };
28 28
29 cpus { 29 cpus {
30 #address-cells = <1>; 30 #address-cells = <1>;
31 #size-cells = <0>; 31 #size-cells = <0>;
32 32
33 PowerPC,8548@0 { 33 PowerPC,8548@0 {
34 device_type = "cpu"; 34 device_type = "cpu";
35 reg = <0>; 35 reg = <0>;
36 d-cache-line-size = <3 36 d-cache-line-size = <32>; // 32 bytes
37 i-cache-line-size = <3 37 i-cache-line-size = <32>; // 32 bytes
38 d-cache-size = <0x8000 38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000 39 i-cache-size = <0x8000>; // L1, 32K
40 next-level-cache = <&L 40 next-level-cache = <&L2>;
41 }; 41 };
42 }; 42 };
43 43
44 memory { 44 memory {
45 device_type = "memory"; 45 device_type = "memory";
46 reg = <0x00000000 0x00000000>; 46 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
47 }; 47 };
48 48
49 soc@a0000000 { 49 soc@a0000000 {
50 #address-cells = <1>; 50 #address-cells = <1>;
51 #size-cells = <1>; 51 #size-cells = <1>;
52 device_type = "soc"; 52 device_type = "soc";
53 ranges = <0x0 0xa0000000 0x100 53 ranges = <0x0 0xa0000000 0x100000>;
54 bus-frequency = <0>; 54 bus-frequency = <0>;
55 compatible = "fsl,mpc8548-immr 55 compatible = "fsl,mpc8548-immr", "simple-bus";
56 56
57 ecm-law@0 { 57 ecm-law@0 {
58 compatible = "fsl,ecm- 58 compatible = "fsl,ecm-law";
59 reg = <0x0 0x1000>; 59 reg = <0x0 0x1000>;
60 fsl,num-laws = <10>; 60 fsl,num-laws = <10>;
61 }; 61 };
62 62
63 ecm@1000 { 63 ecm@1000 {
64 compatible = "fsl,mpc8 64 compatible = "fsl,mpc8548-ecm", "fsl,ecm";
65 reg = <0x1000 0x1000>; 65 reg = <0x1000 0x1000>;
66 interrupts = <17 2>; 66 interrupts = <17 2>;
67 interrupt-parent = <&m 67 interrupt-parent = <&mpic>;
68 }; 68 };
69 69
70 memory-controller@2000 { 70 memory-controller@2000 {
71 compatible = "fsl,mpc8 71 compatible = "fsl,mpc8548-memory-controller";
72 reg = <0x2000 0x1000>; 72 reg = <0x2000 0x1000>;
73 interrupt-parent = <&m 73 interrupt-parent = <&mpic>;
74 interrupts = <18 2>; 74 interrupts = <18 2>;
75 }; 75 };
76 76
77 L2: l2-cache-controller@20000 77 L2: l2-cache-controller@20000 {
78 compatible = "fsl,mpc8 78 compatible = "fsl,mpc8548-l2-cache-controller";
79 reg = <0x20000 0x1000> 79 reg = <0x20000 0x1000>;
80 cache-line-size = <32> 80 cache-line-size = <32>; // 32 bytes
81 cache-size = <0x80000> 81 cache-size = <0x80000>; // L2, 512K
82 interrupt-parent = <&m 82 interrupt-parent = <&mpic>;
83 interrupts = <16 2>; 83 interrupts = <16 2>;
84 }; 84 };
85 85
86 i2c@3000 { 86 i2c@3000 {
87 #address-cells = <1>; 87 #address-cells = <1>;
88 #size-cells = <0>; 88 #size-cells = <0>;
89 cell-index = <0>; 89 cell-index = <0>;
90 compatible = "fsl-i2c" 90 compatible = "fsl-i2c";
91 reg = <0x3000 0x100>; 91 reg = <0x3000 0x100>;
92 interrupts = <43 2>; 92 interrupts = <43 2>;
93 interrupt-parent = <&m 93 interrupt-parent = <&mpic>;
94 dfsrr; 94 dfsrr;
95 95
96 dtt@48 { 96 dtt@48 {
97 compatible = " 97 compatible = "national,lm75";
98 reg = <0x48>; 98 reg = <0x48>;
99 }; 99 };
100 100
101 rtc@68 { 101 rtc@68 {
102 compatible = " 102 compatible = "dallas,ds1337";
103 reg = <0x68>; 103 reg = <0x68>;
104 }; 104 };
105 }; 105 };
106 106
107 i2c@3100 { 107 i2c@3100 {
108 #address-cells = <1>; 108 #address-cells = <1>;
109 #size-cells = <0>; 109 #size-cells = <0>;
110 cell-index = <1>; 110 cell-index = <1>;
111 compatible = "fsl-i2c" 111 compatible = "fsl-i2c";
112 reg = <0x3100 0x100>; 112 reg = <0x3100 0x100>;
113 interrupts = <43 2>; 113 interrupts = <43 2>;
114 interrupt-parent = <&m 114 interrupt-parent = <&mpic>;
115 dfsrr; 115 dfsrr;
116 }; 116 };
117 117
118 dma@21300 { 118 dma@21300 {
119 #address-cells = <1>; 119 #address-cells = <1>;
120 #size-cells = <1>; 120 #size-cells = <1>;
121 compatible = "fsl,mpc8 121 compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
122 reg = <0x21300 0x4>; 122 reg = <0x21300 0x4>;
123 ranges = <0x0 0x21100 123 ranges = <0x0 0x21100 0x200>;
124 cell-index = <0>; 124 cell-index = <0>;
125 dma-channel@0 { 125 dma-channel@0 {
126 compatible = " 126 compatible = "fsl,mpc8548-dma-channel",
127 127 "fsl,eloplus-dma-channel";
128 reg = <0x0 0x8 128 reg = <0x0 0x80>;
129 cell-index = < 129 cell-index = <0>;
130 interrupt-pare 130 interrupt-parent = <&mpic>;
131 interrupts = < 131 interrupts = <20 2>;
132 }; 132 };
133 dma-channel@80 { 133 dma-channel@80 {
134 compatible = " 134 compatible = "fsl,mpc8548-dma-channel",
135 135 "fsl,eloplus-dma-channel";
136 reg = <0x80 0x 136 reg = <0x80 0x80>;
137 cell-index = < 137 cell-index = <1>;
138 interrupt-pare 138 interrupt-parent = <&mpic>;
139 interrupts = < 139 interrupts = <21 2>;
140 }; 140 };
141 dma-channel@100 { 141 dma-channel@100 {
142 compatible = " 142 compatible = "fsl,mpc8548-dma-channel",
143 143 "fsl,eloplus-dma-channel";
144 reg = <0x100 0 144 reg = <0x100 0x80>;
145 cell-index = < 145 cell-index = <2>;
146 interrupt-pare 146 interrupt-parent = <&mpic>;
147 interrupts = < 147 interrupts = <22 2>;
148 }; 148 };
149 dma-channel@180 { 149 dma-channel@180 {
150 compatible = " 150 compatible = "fsl,mpc8548-dma-channel",
151 151 "fsl,eloplus-dma-channel";
152 reg = <0x180 0 152 reg = <0x180 0x80>;
153 cell-index = < 153 cell-index = <3>;
154 interrupt-pare 154 interrupt-parent = <&mpic>;
155 interrupts = < 155 interrupts = <23 2>;
156 }; 156 };
157 }; 157 };
158 158
159 enet0: ethernet@24000 { 159 enet0: ethernet@24000 {
160 #address-cells = <1>; 160 #address-cells = <1>;
161 #size-cells = <1>; 161 #size-cells = <1>;
162 cell-index = <0>; 162 cell-index = <0>;
163 device_type = "network 163 device_type = "network";
164 model = "eTSEC"; 164 model = "eTSEC";
165 compatible = "gianfar" 165 compatible = "gianfar";
166 reg = <0x24000 0x1000> 166 reg = <0x24000 0x1000>;
167 ranges = <0x0 0x24000 167 ranges = <0x0 0x24000 0x1000>;
168 local-mac-address = [ 168 local-mac-address = [ 00 00 00 00 00 00 ];
169 interrupts = <29 2 30 169 interrupts = <29 2 30 2 34 2>;
170 interrupt-parent = <&m 170 interrupt-parent = <&mpic>;
171 tbi-handle = <&tbi0>; 171 tbi-handle = <&tbi0>;
172 phy-handle = <&phy2>; 172 phy-handle = <&phy2>;
173 173
174 mdio@520 { 174 mdio@520 {
175 #address-cells 175 #address-cells = <1>;
176 #size-cells = 176 #size-cells = <0>;
177 compatible = " 177 compatible = "fsl,gianfar-mdio";
178 reg = <0x520 0 178 reg = <0x520 0x20>;
179 179
180 phy1: ethernet 180 phy1: ethernet-phy@0 {
181 interr 181 interrupt-parent = <&mpic>;
182 interr 182 interrupts = <8 1>;
183 reg = 183 reg = <1>;
184 }; 184 };
185 phy2: ethernet 185 phy2: ethernet-phy@1 {
186 interr 186 interrupt-parent = <&mpic>;
187 interr 187 interrupts = <8 1>;
188 reg = 188 reg = <2>;
189 }; 189 };
190 phy3: ethernet 190 phy3: ethernet-phy@3 {
191 interr 191 interrupt-parent = <&mpic>;
192 interr 192 interrupts = <8 1>;
193 reg = 193 reg = <3>;
194 }; 194 };
195 phy4: ethernet 195 phy4: ethernet-phy@4 {
196 interr 196 interrupt-parent = <&mpic>;
197 interr 197 interrupts = <8 1>;
198 reg = 198 reg = <4>;
199 }; 199 };
200 phy5: ethernet 200 phy5: ethernet-phy@5 {
201 interr 201 interrupt-parent = <&mpic>;
202 interr 202 interrupts = <8 1>;
203 reg = 203 reg = <5>;
204 }; 204 };
205 tbi0: tbi-phy@ 205 tbi0: tbi-phy@11 {
206 reg = 206 reg = <0x11>;
207 device 207 device_type = "tbi-phy";
208 }; 208 };
209 }; 209 };
210 }; 210 };
211 211
212 enet1: ethernet@25000 { 212 enet1: ethernet@25000 {
213 #address-cells = <1>; 213 #address-cells = <1>;
214 #size-cells = <1>; 214 #size-cells = <1>;
215 cell-index = <1>; 215 cell-index = <1>;
216 device_type = "network 216 device_type = "network";
217 model = "eTSEC"; 217 model = "eTSEC";
218 compatible = "gianfar" 218 compatible = "gianfar";
219 reg = <0x25000 0x1000> 219 reg = <0x25000 0x1000>;
220 ranges = <0x0 0x25000 220 ranges = <0x0 0x25000 0x1000>;
221 local-mac-address = [ 221 local-mac-address = [ 00 00 00 00 00 00 ];
222 interrupts = <35 2 36 222 interrupts = <35 2 36 2 40 2>;
223 interrupt-parent = <&m 223 interrupt-parent = <&mpic>;
224 tbi-handle = <&tbi1>; 224 tbi-handle = <&tbi1>;
225 phy-handle = <&phy1>; 225 phy-handle = <&phy1>;
226 226
227 mdio@520 { 227 mdio@520 {
228 #address-cells 228 #address-cells = <1>;
229 #size-cells = 229 #size-cells = <0>;
230 compatible = " 230 compatible = "fsl,gianfar-tbi";
231 reg = <0x520 0 231 reg = <0x520 0x20>;
232 232
233 tbi1: tbi-phy@ 233 tbi1: tbi-phy@11 {
234 reg = 234 reg = <0x11>;
235 device 235 device_type = "tbi-phy";
236 }; 236 };
237 }; 237 };
238 }; 238 };
239 239
240 enet2: ethernet@26000 { 240 enet2: ethernet@26000 {
241 #address-cells = <1>; 241 #address-cells = <1>;
242 #size-cells = <1>; 242 #size-cells = <1>;
243 cell-index = <2>; 243 cell-index = <2>;
244 device_type = "network 244 device_type = "network";
245 model = "eTSEC"; 245 model = "eTSEC";
246 compatible = "gianfar" 246 compatible = "gianfar";
247 reg = <0x26000 0x1000> 247 reg = <0x26000 0x1000>;
248 ranges = <0x0 0x26000 248 ranges = <0x0 0x26000 0x1000>;
249 local-mac-address = [ 249 local-mac-address = [ 00 00 00 00 00 00 ];
250 interrupts = <31 2 32 250 interrupts = <31 2 32 2 33 2>;
251 interrupt-parent = <&m 251 interrupt-parent = <&mpic>;
252 tbi-handle = <&tbi2>; 252 tbi-handle = <&tbi2>;
253 phy-handle = <&phy4>; 253 phy-handle = <&phy4>;
254 254
255 mdio@520 { 255 mdio@520 {
256 #address-cells 256 #address-cells = <1>;
257 #size-cells = 257 #size-cells = <0>;
258 compatible = " 258 compatible = "fsl,gianfar-tbi";
259 reg = <0x520 0 259 reg = <0x520 0x20>;
260 260
261 tbi2: tbi-phy@ 261 tbi2: tbi-phy@11 {
262 reg = 262 reg = <0x11>;
263 device 263 device_type = "tbi-phy";
264 }; 264 };
265 }; 265 };
266 }; 266 };
267 267
268 enet3: ethernet@27000 { 268 enet3: ethernet@27000 {
269 #address-cells = <1>; 269 #address-cells = <1>;
270 #size-cells = <1>; 270 #size-cells = <1>;
271 cell-index = <3>; 271 cell-index = <3>;
272 device_type = "network 272 device_type = "network";
273 model = "eTSEC"; 273 model = "eTSEC";
274 compatible = "gianfar" 274 compatible = "gianfar";
275 reg = <0x27000 0x1000> 275 reg = <0x27000 0x1000>;
276 ranges = <0x0 0x27000 276 ranges = <0x0 0x27000 0x1000>;
277 local-mac-address = [ 277 local-mac-address = [ 00 00 00 00 00 00 ];
278 interrupts = <37 2 38 278 interrupts = <37 2 38 2 39 2>;
279 interrupt-parent = <&m 279 interrupt-parent = <&mpic>;
280 tbi-handle = <&tbi3>; 280 tbi-handle = <&tbi3>;
281 phy-handle = <&phy5>; 281 phy-handle = <&phy5>;
282 282
283 mdio@520 { 283 mdio@520 {
284 #address-cells 284 #address-cells = <1>;
285 #size-cells = 285 #size-cells = <0>;
286 compatible = " 286 compatible = "fsl,gianfar-tbi";
287 reg = <0x520 0 287 reg = <0x520 0x20>;
288 288
289 tbi3: tbi-phy@ 289 tbi3: tbi-phy@11 {
290 reg = 290 reg = <0x11>;
291 device 291 device_type = "tbi-phy";
292 }; 292 };
293 }; 293 };
294 }; 294 };
295 295
296 serial0: serial@4500 { 296 serial0: serial@4500 {
297 cell-index = <0>; 297 cell-index = <0>;
298 device_type = "serial" 298 device_type = "serial";
299 compatible = "fsl,ns16 299 compatible = "fsl,ns16550", "ns16550";
300 reg = <0x4500 0x100>; 300 reg = <0x4500 0x100>; // reg base, size
301 clock-frequency = <0>; 301 clock-frequency = <0>; // should we fill in in uboot?
302 current-speed = <11520 302 current-speed = <115200>;
303 interrupts = <42 2>; 303 interrupts = <42 2>;
304 interrupt-parent = <&m 304 interrupt-parent = <&mpic>;
305 }; 305 };
306 306
307 serial1: serial@4600 { 307 serial1: serial@4600 {
308 cell-index = <1>; 308 cell-index = <1>;
309 device_type = "serial" 309 device_type = "serial";
310 compatible = "fsl,ns16 310 compatible = "fsl,ns16550", "ns16550";
311 reg = <0x4600 0x100>; 311 reg = <0x4600 0x100>; // reg base, size
312 clock-frequency = <0>; 312 clock-frequency = <0>; // should we fill in in uboot?
313 current-speed = <11520 313 current-speed = <115200>;
314 interrupts = <42 2>; 314 interrupts = <42 2>;
315 interrupt-parent = <&m 315 interrupt-parent = <&mpic>;
316 }; 316 };
317 317
318 global-utilities@e0000 { 318 global-utilities@e0000 { // global utilities reg
319 compatible = "fsl,mpc8 319 compatible = "fsl,mpc8548-guts";
320 reg = <0xe0000 0x1000> 320 reg = <0xe0000 0x1000>;
321 fsl,has-rstcr; 321 fsl,has-rstcr;
322 }; 322 };
323 323
324 mpic: pic@40000 { 324 mpic: pic@40000 {
325 interrupt-controller; 325 interrupt-controller;
326 #address-cells = <0>; 326 #address-cells = <0>;
327 #interrupt-cells = <2> 327 #interrupt-cells = <2>;
328 reg = <0x40000 0x40000 328 reg = <0x40000 0x40000>;
329 compatible = "chrp,ope 329 compatible = "chrp,open-pic";
330 device_type = "open-pi 330 device_type = "open-pic";
331 }; 331 };
332 }; 332 };
333 333
334 localbus@a0005000 { 334 localbus@a0005000 {
335 compatible = "fsl,mpc8548-loca 335 compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
336 "simple-bus"; 336 "simple-bus";
337 #address-cells = <2>; 337 #address-cells = <2>;
338 #size-cells = <1>; 338 #size-cells = <1>;
339 reg = <0xa0005000 0x100>; 339 reg = <0xa0005000 0x100>; // BRx, ORx, etc.
340 interrupt-parent = <&mpic>; 340 interrupt-parent = <&mpic>;
341 interrupts = <19 2>; 341 interrupts = <19 2>;
342 342
343 ranges = < 343 ranges = <
344 0 0x0 0xfc000000 0x040 344 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
345 1 0x0 0xf8000000 0x080 345 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0
346 2 0x0 0xa3000000 0x000 346 2 0x0 0xa3000000 0x00008000 // CAN (2 x CC770)
347 3 0x0 0xa3010000 0x000 347 3 0x0 0xa3010000 0x00008000 // NAND FLASH
348 348
349 >; 349 >;
350 350
351 flash@1,0 { 351 flash@1,0 {
352 #address-cells = <1>; 352 #address-cells = <1>;
353 #size-cells = <1>; 353 #size-cells = <1>;
354 compatible = "cfi-flas 354 compatible = "cfi-flash";
355 reg = <1 0x0 0x8000000 355 reg = <1 0x0 0x8000000>;
356 bank-width = <4>; 356 bank-width = <4>;
357 device-width = <1>; 357 device-width = <1>;
358 358
359 partition@0 { 359 partition@0 {
360 label = "kerne 360 label = "kernel";
361 reg = <0x00000 361 reg = <0x00000000 0x00200000>;
362 }; 362 };
363 partition@200000 { 363 partition@200000 {
364 label = "root" 364 label = "root";
365 reg = <0x00200 365 reg = <0x00200000 0x00300000>;
366 }; 366 };
367 partition@500000 { 367 partition@500000 {
368 label = "user" 368 label = "user";
369 reg = <0x00500 369 reg = <0x00500000 0x07a00000>;
370 }; 370 };
371 partition@7f00000 { 371 partition@7f00000 {
372 label = "env1" 372 label = "env1";
373 reg = <0x07f00 373 reg = <0x07f00000 0x00040000>;
374 }; 374 };
375 partition@7f40000 { 375 partition@7f40000 {
376 label = "env2" 376 label = "env2";
377 reg = <0x07f40 377 reg = <0x07f40000 0x00040000>;
378 }; 378 };
379 partition@7f80000 { 379 partition@7f80000 {
380 label = "u-boo 380 label = "u-boot";
381 reg = <0x07f80 381 reg = <0x07f80000 0x00080000>;
382 read-only; 382 read-only;
383 }; 383 };
384 }; 384 };
385 385
386 /* Note: CAN support needs be 386 /* Note: CAN support needs be enabled in U-Boot */
387 can@2,0 { 387 can@2,0 {
388 compatible = "bosch,cc 388 compatible = "bosch,cc770"; // Bosch CC770
389 reg = <2 0x0 0x100>; 389 reg = <2 0x0 0x100>;
390 interrupts = <4 1>; 390 interrupts = <4 1>;
391 interrupt-parent = <&m 391 interrupt-parent = <&mpic>;
392 bosch,external-clock-f 392 bosch,external-clock-frequency = <16000000>;
393 bosch,disconnect-rx1-i 393 bosch,disconnect-rx1-input;
394 bosch,disconnect-tx1-o 394 bosch,disconnect-tx1-output;
395 bosch,iso-low-speed-mu 395 bosch,iso-low-speed-mux;
396 bosch,clock-out-freque 396 bosch,clock-out-frequency = <16000000>;
397 }; 397 };
398 398
399 can@2,100 { 399 can@2,100 {
400 compatible = "bosch,cc 400 compatible = "bosch,cc770"; // Bosch CC770
401 reg = <2 0x100 0x100>; 401 reg = <2 0x100 0x100>;
402 interrupts = <4 1>; 402 interrupts = <4 1>;
403 interrupt-parent = <&m 403 interrupt-parent = <&mpic>;
404 bosch,external-clock-f 404 bosch,external-clock-frequency = <16000000>;
405 bosch,disconnect-rx1-i 405 bosch,disconnect-rx1-input;
406 bosch,disconnect-tx1-o 406 bosch,disconnect-tx1-output;
407 bosch,iso-low-speed-mu 407 bosch,iso-low-speed-mux;
408 }; 408 };
409 409
410 /* Note: NAND support needs to 410 /* Note: NAND support needs to be enabled in U-Boot */
411 upm@3,0 { 411 upm@3,0 {
412 #address-cells = <0>; 412 #address-cells = <0>;
413 #size-cells = <0>; 413 #size-cells = <0>;
414 compatible = "tqc,tqm8 414 compatible = "tqc,tqm8548-upm-nand", "fsl,upm-nand";
415 reg = <3 0x0 0x800>; 415 reg = <3 0x0 0x800>;
416 fsl,upm-addr-offset = 416 fsl,upm-addr-offset = <0x10>;
417 fsl,upm-cmd-offset = < 417 fsl,upm-cmd-offset = <0x08>;
418 /* Micron MT29F8G08FAB 418 /* Micron MT29F8G08FAB multi-chip device */
419 fsl,upm-addr-line-cs-o 419 fsl,upm-addr-line-cs-offsets = <0x0 0x200>;
420 fsl,upm-wait-flags = < 420 fsl,upm-wait-flags = <0x5>;
421 chip-delay = <25>; // 421 chip-delay = <25>; // in micro-seconds
422 422
423 nand@0 { 423 nand@0 {
424 #address-cells 424 #address-cells = <1>;
425 #size-cells = 425 #size-cells = <1>;
426 426
427 partition@0 { 427 partition@0 {
428 la 428 label = "fs";
429 re 429 reg = <0x00000000 0x10000000>;
430 }; 430 };
431 }; 431 };
432 }; 432 };
433 }; 433 };
434 434
435 pci0: pci@a0008000 { 435 pci0: pci@a0008000 {
436 #interrupt-cells = <1>; 436 #interrupt-cells = <1>;
437 #size-cells = <2>; 437 #size-cells = <2>;
438 #address-cells = <3>; 438 #address-cells = <3>;
439 compatible = "fsl,mpc8540-pcix 439 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
440 device_type = "pci"; 440 device_type = "pci";
441 reg = <0xa0008000 0x1000>; 441 reg = <0xa0008000 0x1000>;
442 clock-frequency = <33333333>; 442 clock-frequency = <33333333>;
443 interrupt-map-mask = <0xf800 0 443 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
444 interrupt-map = < 444 interrupt-map = <
445 /* IDSEL 28 */ 445 /* IDSEL 28 */
446 0xe000 0 0 1 446 0xe000 0 0 1 &mpic 2 1
447 0xe000 0 0 2 447 0xe000 0 0 2 &mpic 3 1
448 0xe000 0 0 3 448 0xe000 0 0 3 &mpic 6 1
449 0xe000 0 0 4 449 0xe000 0 0 4 &mpic 5 1
450 450
451 /* IDSEL 11 */ 451 /* IDSEL 11 */
452 0x5800 0 0 1 452 0x5800 0 0 1 &mpic 6 1
453 0x5800 0 0 2 453 0x5800 0 0 2 &mpic 5 1
454 >; 454 >;
455 455
456 interrupt-parent = <&mpic>; 456 interrupt-parent = <&mpic>;
457 interrupts = <24 2>; 457 interrupts = <24 2>;
458 bus-range = <0 0>; 458 bus-range = <0 0>;
459 ranges = <0x02000000 0 0x80000 459 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
460 0x01000000 0 0x00000 460 0x01000000 0 0x00000000 0xa2000000 0 0x01000000>;
461 }; 461 };
462 462
463 pci1: pcie@a000a000 { 463 pci1: pcie@a000a000 {
464 interrupt-map-mask = <0xf800 0 464 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
465 interrupt-map = < 465 interrupt-map = <
466 /* IDSEL 0x0 (PEX) */ 466 /* IDSEL 0x0 (PEX) */
467 0x00000 0 0 1 &mpic 0 467 0x00000 0 0 1 &mpic 0 1
468 0x00000 0 0 2 &mpic 1 468 0x00000 0 0 2 &mpic 1 1
469 0x00000 0 0 3 &mpic 2 469 0x00000 0 0 3 &mpic 2 1
470 0x00000 0 0 4 &mpic 3 470 0x00000 0 0 4 &mpic 3 1>;
471 471
472 interrupt-parent = <&mpic>; 472 interrupt-parent = <&mpic>;
473 interrupts = <26 2>; 473 interrupts = <26 2>;
474 bus-range = <0 0xff>; 474 bus-range = <0 0xff>;
475 ranges = <0x02000000 0 0xb0000 475 ranges = <0x02000000 0 0xb0000000 0xb0000000 0 0x10000000
476 0x01000000 0 0x00000 476 0x01000000 0 0x00000000 0xaf000000 0 0x08000000>;
477 clock-frequency = <33333333>; 477 clock-frequency = <33333333>;
478 #interrupt-cells = <1>; 478 #interrupt-cells = <1>;
479 #size-cells = <2>; 479 #size-cells = <2>;
480 #address-cells = <3>; 480 #address-cells = <3>;
481 reg = <0xa000a000 0x1000>; 481 reg = <0xa000a000 0x1000>;
482 compatible = "fsl,mpc8548-pcie 482 compatible = "fsl,mpc8548-pcie";
483 device_type = "pci"; 483 device_type = "pci";
484 pcie@0 { 484 pcie@0 {
485 reg = <0 0 0 0 0>; 485 reg = <0 0 0 0 0>;
486 #size-cells = <2>; 486 #size-cells = <2>;
487 #address-cells = <3>; 487 #address-cells = <3>;
488 device_type = "pci"; 488 device_type = "pci";
489 ranges = <0x02000000 0 489 ranges = <0x02000000 0 0xb0000000 0x02000000 0
490 0xb0000000 0 490 0xb0000000 0 0x10000000
491 0x01000000 0 491 0x01000000 0 0x00000000 0x01000000 0
492 0x00000000 0 492 0x00000000 0 0x08000000>;
493 }; 493 };
494 }; 494 };
495 }; 495 };
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