1 // SPDX-License-Identifier: GPL-2.0-or-later 1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* 2 /*
3 * TQM 8560 Device Tree Source 3 * TQM 8560 Device Tree Source
4 * 4 *
5 * Copyright 2008 Freescale Semiconductor Inc. 5 * Copyright 2008 Freescale Semiconductor Inc.
6 * Copyright 2008 Wolfgang Grandegger <wg@grand 6 * Copyright 2008 Wolfgang Grandegger <wg@grandegger.com>
7 */ 7 */
8 8
9 /dts-v1/; 9 /dts-v1/;
10 10
11 /include/ "fsl/e500v1_power_isa.dtsi" 11 /include/ "fsl/e500v1_power_isa.dtsi"
12 12
13 / { 13 / {
14 model = "tqc,tqm8560"; 14 model = "tqc,tqm8560";
15 compatible = "tqc,tqm8560"; 15 compatible = "tqc,tqm8560";
16 #address-cells = <1>; 16 #address-cells = <1>;
17 #size-cells = <1>; 17 #size-cells = <1>;
18 18
19 aliases { 19 aliases {
20 ethernet0 = &enet0; 20 ethernet0 = &enet0;
21 ethernet1 = &enet1; 21 ethernet1 = &enet1;
22 ethernet2 = &enet2; 22 ethernet2 = &enet2;
23 serial0 = &serial0; 23 serial0 = &serial0;
24 serial1 = &serial1; 24 serial1 = &serial1;
25 pci0 = &pci0; 25 pci0 = &pci0;
26 }; 26 };
27 27
28 cpus { 28 cpus {
29 #address-cells = <1>; 29 #address-cells = <1>;
30 #size-cells = <0>; 30 #size-cells = <0>;
31 31
32 PowerPC,8560@0 { 32 PowerPC,8560@0 {
33 device_type = "cpu"; 33 device_type = "cpu";
34 reg = <0>; 34 reg = <0>;
35 d-cache-line-size = <3 35 d-cache-line-size = <32>;
36 i-cache-line-size = <3 36 i-cache-line-size = <32>;
37 d-cache-size = <32768> 37 d-cache-size = <32768>;
38 i-cache-size = <32768> 38 i-cache-size = <32768>;
39 timebase-frequency = < 39 timebase-frequency = <0>;
40 bus-frequency = <0>; 40 bus-frequency = <0>;
41 clock-frequency = <0>; 41 clock-frequency = <0>;
42 next-level-cache = <&L 42 next-level-cache = <&L2>;
43 }; 43 };
44 }; 44 };
45 45
46 memory { 46 memory {
47 device_type = "memory"; 47 device_type = "memory";
48 reg = <0x00000000 0x10000000>; 48 reg = <0x00000000 0x10000000>;
49 }; 49 };
50 50
51 soc@e0000000 { 51 soc@e0000000 {
52 #address-cells = <1>; 52 #address-cells = <1>;
53 #size-cells = <1>; 53 #size-cells = <1>;
54 device_type = "soc"; 54 device_type = "soc";
55 ranges = <0x0 0xe0000000 0x100 55 ranges = <0x0 0xe0000000 0x100000>;
56 bus-frequency = <0>; 56 bus-frequency = <0>;
57 compatible = "fsl,mpc8560-immr 57 compatible = "fsl,mpc8560-immr", "simple-bus";
58 58
59 ecm-law@0 { 59 ecm-law@0 {
60 compatible = "fsl,ecm- 60 compatible = "fsl,ecm-law";
61 reg = <0x0 0x1000>; 61 reg = <0x0 0x1000>;
62 fsl,num-laws = <8>; 62 fsl,num-laws = <8>;
63 }; 63 };
64 64
65 ecm@1000 { 65 ecm@1000 {
66 compatible = "fsl,mpc8 66 compatible = "fsl,mpc8560-ecm", "fsl,ecm";
67 reg = <0x1000 0x1000>; 67 reg = <0x1000 0x1000>;
68 interrupts = <17 2>; 68 interrupts = <17 2>;
69 interrupt-parent = <&m 69 interrupt-parent = <&mpic>;
70 }; 70 };
71 71
72 memory-controller@2000 { 72 memory-controller@2000 {
73 compatible = "fsl,mpc8 73 compatible = "fsl,mpc8540-memory-controller";
74 reg = <0x2000 0x1000>; 74 reg = <0x2000 0x1000>;
75 interrupt-parent = <&m 75 interrupt-parent = <&mpic>;
76 interrupts = <18 2>; 76 interrupts = <18 2>;
77 }; 77 };
78 78
79 L2: l2-cache-controller@20000 79 L2: l2-cache-controller@20000 {
80 compatible = "fsl,mpc8 80 compatible = "fsl,mpc8540-l2-cache-controller";
81 reg = <0x20000 0x1000> 81 reg = <0x20000 0x1000>;
82 cache-line-size = <32> 82 cache-line-size = <32>;
83 cache-size = <0x40000> 83 cache-size = <0x40000>; // L2, 256K
84 interrupt-parent = <&m 84 interrupt-parent = <&mpic>;
85 interrupts = <16 2>; 85 interrupts = <16 2>;
86 }; 86 };
87 87
88 i2c@3000 { 88 i2c@3000 {
89 #address-cells = <1>; 89 #address-cells = <1>;
90 #size-cells = <0>; 90 #size-cells = <0>;
91 cell-index = <0>; 91 cell-index = <0>;
92 compatible = "fsl-i2c" 92 compatible = "fsl-i2c";
93 reg = <0x3000 0x100>; 93 reg = <0x3000 0x100>;
94 interrupts = <43 2>; 94 interrupts = <43 2>;
95 interrupt-parent = <&m 95 interrupt-parent = <&mpic>;
96 dfsrr; 96 dfsrr;
97 97
98 dtt@48 { 98 dtt@48 {
99 compatible = " 99 compatible = "national,lm75";
100 reg = <0x48>; 100 reg = <0x48>;
101 }; 101 };
102 102
103 rtc@68 { 103 rtc@68 {
104 compatible = " 104 compatible = "dallas,ds1337";
105 reg = <0x68>; 105 reg = <0x68>;
106 }; 106 };
107 }; 107 };
108 108
109 dma@21300 { 109 dma@21300 {
110 #address-cells = <1>; 110 #address-cells = <1>;
111 #size-cells = <1>; 111 #size-cells = <1>;
112 compatible = "fsl,mpc8 112 compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
113 reg = <0x21300 0x4>; 113 reg = <0x21300 0x4>;
114 ranges = <0x0 0x21100 114 ranges = <0x0 0x21100 0x200>;
115 cell-index = <0>; 115 cell-index = <0>;
116 dma-channel@0 { 116 dma-channel@0 {
117 compatible = " 117 compatible = "fsl,mpc8560-dma-channel",
118 118 "fsl,eloplus-dma-channel";
119 reg = <0x0 0x8 119 reg = <0x0 0x80>;
120 cell-index = < 120 cell-index = <0>;
121 interrupt-pare 121 interrupt-parent = <&mpic>;
122 interrupts = < 122 interrupts = <20 2>;
123 }; 123 };
124 dma-channel@80 { 124 dma-channel@80 {
125 compatible = " 125 compatible = "fsl,mpc8560-dma-channel",
126 126 "fsl,eloplus-dma-channel";
127 reg = <0x80 0x 127 reg = <0x80 0x80>;
128 cell-index = < 128 cell-index = <1>;
129 interrupt-pare 129 interrupt-parent = <&mpic>;
130 interrupts = < 130 interrupts = <21 2>;
131 }; 131 };
132 dma-channel@100 { 132 dma-channel@100 {
133 compatible = " 133 compatible = "fsl,mpc8560-dma-channel",
134 134 "fsl,eloplus-dma-channel";
135 reg = <0x100 0 135 reg = <0x100 0x80>;
136 cell-index = < 136 cell-index = <2>;
137 interrupt-pare 137 interrupt-parent = <&mpic>;
138 interrupts = < 138 interrupts = <22 2>;
139 }; 139 };
140 dma-channel@180 { 140 dma-channel@180 {
141 compatible = " 141 compatible = "fsl,mpc8560-dma-channel",
142 142 "fsl,eloplus-dma-channel";
143 reg = <0x180 0 143 reg = <0x180 0x80>;
144 cell-index = < 144 cell-index = <3>;
145 interrupt-pare 145 interrupt-parent = <&mpic>;
146 interrupts = < 146 interrupts = <23 2>;
147 }; 147 };
148 }; 148 };
149 149
150 enet0: ethernet@24000 { 150 enet0: ethernet@24000 {
151 #address-cells = <1>; 151 #address-cells = <1>;
152 #size-cells = <1>; 152 #size-cells = <1>;
153 cell-index = <0>; 153 cell-index = <0>;
154 device_type = "network 154 device_type = "network";
155 model = "TSEC"; 155 model = "TSEC";
156 compatible = "gianfar" 156 compatible = "gianfar";
157 reg = <0x24000 0x1000> 157 reg = <0x24000 0x1000>;
158 ranges = <0x0 0x24000 158 ranges = <0x0 0x24000 0x1000>;
159 local-mac-address = [ 159 local-mac-address = [ 00 00 00 00 00 00 ];
160 interrupts = <29 2 30 160 interrupts = <29 2 30 2 34 2>;
161 interrupt-parent = <&m 161 interrupt-parent = <&mpic>;
162 tbi-handle = <&tbi0>; 162 tbi-handle = <&tbi0>;
163 phy-handle = <&phy2>; 163 phy-handle = <&phy2>;
164 164
165 mdio@520 { 165 mdio@520 {
166 #address-cells 166 #address-cells = <1>;
167 #size-cells = 167 #size-cells = <0>;
168 compatible = " 168 compatible = "fsl,gianfar-mdio";
169 reg = <0x520 0 169 reg = <0x520 0x20>;
170 170
171 phy1: ethernet 171 phy1: ethernet-phy@1 {
172 interr 172 interrupt-parent = <&mpic>;
173 interr 173 interrupts = <8 1>;
174 reg = 174 reg = <1>;
175 }; 175 };
176 phy2: ethernet 176 phy2: ethernet-phy@2 {
177 interr 177 interrupt-parent = <&mpic>;
178 interr 178 interrupts = <8 1>;
179 reg = 179 reg = <2>;
180 }; 180 };
181 phy3: ethernet 181 phy3: ethernet-phy@3 {
182 interr 182 interrupt-parent = <&mpic>;
183 interr 183 interrupts = <8 1>;
184 reg = 184 reg = <3>;
185 }; 185 };
186 tbi0: tbi-phy@ 186 tbi0: tbi-phy@11 {
187 reg = 187 reg = <0x11>;
188 device 188 device_type = "tbi-phy";
189 }; 189 };
190 }; 190 };
191 }; 191 };
192 192
193 enet1: ethernet@25000 { 193 enet1: ethernet@25000 {
194 #address-cells = <1>; 194 #address-cells = <1>;
195 #size-cells = <1>; 195 #size-cells = <1>;
196 cell-index = <1>; 196 cell-index = <1>;
197 device_type = "network 197 device_type = "network";
198 model = "TSEC"; 198 model = "TSEC";
199 compatible = "gianfar" 199 compatible = "gianfar";
200 reg = <0x25000 0x1000> 200 reg = <0x25000 0x1000>;
201 ranges = <0x0 0x25000 201 ranges = <0x0 0x25000 0x1000>;
202 local-mac-address = [ 202 local-mac-address = [ 00 00 00 00 00 00 ];
203 interrupts = <35 2 36 203 interrupts = <35 2 36 2 40 2>;
204 interrupt-parent = <&m 204 interrupt-parent = <&mpic>;
205 tbi-handle = <&tbi1>; 205 tbi-handle = <&tbi1>;
206 phy-handle = <&phy1>; 206 phy-handle = <&phy1>;
207 207
208 mdio@520 { 208 mdio@520 {
209 #address-cells 209 #address-cells = <1>;
210 #size-cells = 210 #size-cells = <0>;
211 compatible = " 211 compatible = "fsl,gianfar-tbi";
212 reg = <0x520 0 212 reg = <0x520 0x20>;
213 213
214 tbi1: tbi-phy@ 214 tbi1: tbi-phy@11 {
215 reg = 215 reg = <0x11>;
216 device 216 device_type = "tbi-phy";
217 }; 217 };
218 }; 218 };
219 }; 219 };
220 220
221 mpic: pic@40000 { 221 mpic: pic@40000 {
222 interrupt-controller; 222 interrupt-controller;
223 #address-cells = <0>; 223 #address-cells = <0>;
224 #interrupt-cells = <2> 224 #interrupt-cells = <2>;
225 reg = <0x40000 0x40000 225 reg = <0x40000 0x40000>;
226 device_type = "open-pi 226 device_type = "open-pic";
227 compatible = "chrp,ope 227 compatible = "chrp,open-pic";
228 }; 228 };
229 229
230 cpm@919c0 { 230 cpm@919c0 {
231 #address-cells = <1>; 231 #address-cells = <1>;
232 #size-cells = <1>; 232 #size-cells = <1>;
233 compatible = "fsl,mpc8 233 compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus";
234 reg = <0x919c0 0x30>; 234 reg = <0x919c0 0x30>;
235 ranges; 235 ranges;
236 236
237 muram@80000 { 237 muram@80000 {
238 #address-cells 238 #address-cells = <1>;
239 #size-cells = 239 #size-cells = <1>;
240 ranges = <0 0x 240 ranges = <0 0x80000 0x10000>;
241 241
242 data@0 { 242 data@0 {
243 compat 243 compatible = "fsl,cpm-muram-data";
244 reg = 244 reg = <0 0x4000 0x9000 0x2000>;
245 }; 245 };
246 }; 246 };
247 247
248 brg@919f0 { 248 brg@919f0 {
249 compatible = " 249 compatible = "fsl,mpc8560-brg",
250 " 250 "fsl,cpm2-brg",
251 " 251 "fsl,cpm-brg";
252 reg = <0x919f0 252 reg = <0x919f0 0x10 0x915f0 0x10>;
253 clock-frequenc 253 clock-frequency = <0>;
254 }; 254 };
255 255
256 cpmpic: pic@90c00 { 256 cpmpic: pic@90c00 {
257 interrupt-cont 257 interrupt-controller;
258 #address-cells 258 #address-cells = <0>;
259 #interrupt-cel 259 #interrupt-cells = <2>;
260 interrupts = < 260 interrupts = <46 2>;
261 interrupt-pare 261 interrupt-parent = <&mpic>;
262 reg = <0x90c00 262 reg = <0x90c00 0x80>;
263 compatible = " 263 compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
264 }; 264 };
265 265
266 serial0: serial@91a00 266 serial0: serial@91a00 {
267 device_type = 267 device_type = "serial";
268 compatible = " 268 compatible = "fsl,mpc8560-scc-uart",
269 " 269 "fsl,cpm2-scc-uart";
270 reg = <0x91a00 270 reg = <0x91a00 0x20 0x88000 0x100>;
271 fsl,cpm-brg = 271 fsl,cpm-brg = <1>;
272 fsl,cpm-comman 272 fsl,cpm-command = <0x800000>;
273 current-speed 273 current-speed = <115200>;
274 interrupts = < 274 interrupts = <40 8>;
275 interrupt-pare 275 interrupt-parent = <&cpmpic>;
276 }; 276 };
277 277
278 serial1: serial@91a20 278 serial1: serial@91a20 {
279 device_type = 279 device_type = "serial";
280 compatible = " 280 compatible = "fsl,mpc8560-scc-uart",
281 " 281 "fsl,cpm2-scc-uart";
282 reg = <0x91a20 282 reg = <0x91a20 0x20 0x88100 0x100>;
283 fsl,cpm-brg = 283 fsl,cpm-brg = <2>;
284 fsl,cpm-comman 284 fsl,cpm-command = <0x4a00000>;
285 current-speed 285 current-speed = <115200>;
286 interrupts = < 286 interrupts = <41 8>;
287 interrupt-pare 287 interrupt-parent = <&cpmpic>;
288 }; 288 };
289 289
290 enet2: ethernet@91340 290 enet2: ethernet@91340 {
291 device_type = 291 device_type = "network";
292 compatible = " 292 compatible = "fsl,mpc8560-fcc-enet",
293 " 293 "fsl,cpm2-fcc-enet";
294 reg = <0x91340 294 reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
295 local-mac-addr 295 local-mac-address = [ 00 00 00 00 00 00 ];
296 fsl,cpm-comman 296 fsl,cpm-command = <0x1a400300>;
297 interrupts = < 297 interrupts = <34 8>;
298 interrupt-pare 298 interrupt-parent = <&cpmpic>;
299 phy-handle = < 299 phy-handle = <&phy3>;
300 }; 300 };
301 }; 301 };
302 }; 302 };
303 303
304 localbus@e0005000 { 304 localbus@e0005000 {
305 compatible = "fsl,mpc8560-loca 305 compatible = "fsl,mpc8560-localbus", "fsl,pq3-localbus",
306 "simple-bus"; 306 "simple-bus";
307 #address-cells = <2>; 307 #address-cells = <2>;
308 #size-cells = <1>; 308 #size-cells = <1>;
309 reg = <0xe0005000 0x100>; 309 reg = <0xe0005000 0x100>; // BRx, ORx, etc.
310 interrupt-parent = <&mpic>; 310 interrupt-parent = <&mpic>;
311 interrupts = <19 2>; 311 interrupts = <19 2>;
312 312
313 ranges = < 313 ranges = <
314 0 0x0 0xfc000000 0x040 314 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
315 1 0x0 0xf8000000 0x080 315 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0
316 2 0x0 0xe3000000 0x000 316 2 0x0 0xe3000000 0x00008000 // CAN (2 x i82527)
317 >; 317 >;
318 318
319 flash@1,0 { 319 flash@1,0 {
320 #address-cells = <1>; 320 #address-cells = <1>;
321 #size-cells = <1>; 321 #size-cells = <1>;
322 compatible = "cfi-flas 322 compatible = "cfi-flash";
323 reg = <1 0x0 0x8000000 323 reg = <1 0x0 0x8000000>;
324 bank-width = <4>; 324 bank-width = <4>;
325 device-width = <1>; 325 device-width = <1>;
326 326
327 partition@0 { 327 partition@0 {
328 label = "kerne 328 label = "kernel";
329 reg = <0x00000 329 reg = <0x00000000 0x00200000>;
330 }; 330 };
331 partition@200000 { 331 partition@200000 {
332 label = "root" 332 label = "root";
333 reg = <0x00200 333 reg = <0x00200000 0x00300000>;
334 }; 334 };
335 partition@500000 { 335 partition@500000 {
336 label = "user" 336 label = "user";
337 reg = <0x00500 337 reg = <0x00500000 0x07a00000>;
338 }; 338 };
339 partition@7f00000 { 339 partition@7f00000 {
340 label = "env1" 340 label = "env1";
341 reg = <0x07f00 341 reg = <0x07f00000 0x00040000>;
342 }; 342 };
343 partition@7f40000 { 343 partition@7f40000 {
344 label = "env2" 344 label = "env2";
345 reg = <0x07f40 345 reg = <0x07f40000 0x00040000>;
346 }; 346 };
347 partition@7f80000 { 347 partition@7f80000 {
348 label = "u-boo 348 label = "u-boot";
349 reg = <0x07f80 349 reg = <0x07f80000 0x00080000>;
350 read-only; 350 read-only;
351 }; 351 };
352 }; 352 };
353 353
354 /* Note: CAN support needs be 354 /* Note: CAN support needs be enabled in U-Boot */
355 can0@2,0 { 355 can0@2,0 {
356 compatible = "intel,82 356 compatible = "intel,82527"; // Bosch CC770
357 reg = <2 0x0 0x100>; 357 reg = <2 0x0 0x100>;
358 interrupts = <4 1>; 358 interrupts = <4 1>;
359 interrupt-parent = <&m 359 interrupt-parent = <&mpic>;
360 }; 360 };
361 361
362 can1@2,100 { 362 can1@2,100 {
363 compatible = "intel,82 363 compatible = "intel,82527"; // Bosch CC770
364 reg = <2 0x100 0x100>; 364 reg = <2 0x100 0x100>;
365 interrupts = <4 1>; 365 interrupts = <4 1>;
366 interrupt-parent = <&m 366 interrupt-parent = <&mpic>;
367 }; 367 };
368 }; 368 };
369 369
370 pci0: pci@e0008000 { 370 pci0: pci@e0008000 {
371 #interrupt-cells = <1>; 371 #interrupt-cells = <1>;
372 #size-cells = <2>; 372 #size-cells = <2>;
373 #address-cells = <3>; 373 #address-cells = <3>;
374 compatible = "fsl,mpc8540-pcix 374 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
375 device_type = "pci"; 375 device_type = "pci";
376 reg = <0xe0008000 0x1000>; 376 reg = <0xe0008000 0x1000>;
377 clock-frequency = <66666666>; 377 clock-frequency = <66666666>;
378 interrupt-map-mask = <0xf800 0 378 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
379 interrupt-map = < 379 interrupt-map = <
380 /* IDSEL 28 */ 380 /* IDSEL 28 */
381 0xe000 0 0 1 381 0xe000 0 0 1 &mpic 2 1
382 0xe000 0 0 2 382 0xe000 0 0 2 &mpic 3 1
383 0xe000 0 0 3 383 0xe000 0 0 3 &mpic 6 1
384 0xe000 0 0 4 384 0xe000 0 0 4 &mpic 5 1
385 385
386 /* IDSEL 11 */ 386 /* IDSEL 11 */
387 0x5800 0 0 1 387 0x5800 0 0 1 &mpic 6 1
388 0x5800 0 0 2 388 0x5800 0 0 2 &mpic 5 1
389 >; 389 >;
390 390
391 interrupt-parent = <&mpic>; 391 interrupt-parent = <&mpic>;
392 interrupts = <24 2>; 392 interrupts = <24 2>;
393 bus-range = <0 0>; 393 bus-range = <0 0>;
394 ranges = <0x02000000 0 0x80000 394 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
395 0x01000000 0 0x00000 395 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
396 }; 396 };
397 }; 397 };
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