1 // SPDX-License-Identifier: GPL-2.0-only <<
2 /* 1 /*
3 * Copyright (C) 2009 Extreme Engineering Solu 2 * Copyright (C) 2009 Extreme Engineering Solutions, Inc.
4 * Based on TQM8548 device tree 3 * Based on TQM8548 device tree
5 * 4 *
6 * XPedite5200 PrPMC/XMC module based on MPC85 5 * XPedite5200 PrPMC/XMC module based on MPC8548E
>> 6 *
>> 7 * This is free software; you can redistribute it and/or modify
>> 8 * it under the terms of the GNU General Public License version 2 as
>> 9 * published by the Free Software Foundation.
7 */ 10 */
8 11
9 /dts-v1/; 12 /dts-v1/;
10 13
11 / { 14 / {
12 model = "xes,xpedite5200"; 15 model = "xes,xpedite5200";
13 compatible = "xes,xpedite5200", "xes,M 16 compatible = "xes,xpedite5200", "xes,MPC8548";
14 #address-cells = <1>; 17 #address-cells = <1>;
15 #size-cells = <1>; 18 #size-cells = <1>;
16 19
17 aliases { 20 aliases {
18 ethernet0 = &enet0; 21 ethernet0 = &enet0;
19 ethernet1 = &enet1; 22 ethernet1 = &enet1;
20 ethernet2 = &enet2; 23 ethernet2 = &enet2;
21 ethernet3 = &enet3; 24 ethernet3 = &enet3;
22 25
23 serial0 = &serial0; 26 serial0 = &serial0;
24 serial1 = &serial1; 27 serial1 = &serial1;
25 pci0 = &pci0; 28 pci0 = &pci0;
26 }; 29 };
27 30
28 cpus { 31 cpus {
29 #address-cells = <1>; 32 #address-cells = <1>;
30 #size-cells = <0>; 33 #size-cells = <0>;
31 34
32 PowerPC,8548@0 { 35 PowerPC,8548@0 {
33 device_type = "cpu"; 36 device_type = "cpu";
34 reg = <0>; 37 reg = <0>;
35 d-cache-line-size = <3 38 d-cache-line-size = <32>; // 32 bytes
36 i-cache-line-size = <3 39 i-cache-line-size = <32>; // 32 bytes
37 d-cache-size = <0x8000 40 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000 41 i-cache-size = <0x8000>; // L1, 32K
39 next-level-cache = <&L 42 next-level-cache = <&L2>;
40 }; 43 };
41 }; 44 };
42 45
43 memory { 46 memory {
44 device_type = "memory"; 47 device_type = "memory";
45 reg = <0x0 0x0>; // Fil 48 reg = <0x0 0x0>; // Filled in by U-Boot
46 }; 49 };
47 50
48 soc@ef000000 { 51 soc@ef000000 {
49 #address-cells = <1>; 52 #address-cells = <1>;
50 #size-cells = <1>; 53 #size-cells = <1>;
51 device_type = "soc"; 54 device_type = "soc";
52 ranges = <0x0 0xef000000 0x100 55 ranges = <0x0 0xef000000 0x100000>;
53 bus-frequency = <0>; 56 bus-frequency = <0>;
54 compatible = "fsl,mpc8548-immr 57 compatible = "fsl,mpc8548-immr", "simple-bus";
55 58
56 ecm-law@0 { 59 ecm-law@0 {
57 compatible = "fsl,ecm- 60 compatible = "fsl,ecm-law";
58 reg = <0x0 0x1000>; 61 reg = <0x0 0x1000>;
59 fsl,num-laws = <12>; 62 fsl,num-laws = <12>;
60 }; 63 };
61 64
62 ecm@1000 { 65 ecm@1000 {
63 compatible = "fsl,mpc8 66 compatible = "fsl,mpc8548-ecm", "fsl,ecm";
64 reg = <0x1000 0x1000>; 67 reg = <0x1000 0x1000>;
65 interrupts = <17 2>; 68 interrupts = <17 2>;
66 interrupt-parent = <&m 69 interrupt-parent = <&mpic>;
67 }; 70 };
68 71
69 memory-controller@2000 { 72 memory-controller@2000 {
70 compatible = "fsl,mpc8 73 compatible = "fsl,mpc8548-memory-controller";
71 reg = <0x2000 0x1000>; 74 reg = <0x2000 0x1000>;
72 interrupt-parent = <&m 75 interrupt-parent = <&mpic>;
73 interrupts = <18 2>; 76 interrupts = <18 2>;
74 }; 77 };
75 78
76 L2: l2-cache-controller@20000 79 L2: l2-cache-controller@20000 {
77 compatible = "fsl,mpc8 80 compatible = "fsl,mpc8548-l2-cache-controller";
78 reg = <0x20000 0x1000> 81 reg = <0x20000 0x1000>;
79 cache-line-size = <32> 82 cache-line-size = <32>; // 32 bytes
80 cache-size = <0x80000> 83 cache-size = <0x80000>; // L2, 512K
81 interrupt-parent = <&m 84 interrupt-parent = <&mpic>;
82 interrupts = <16 2>; 85 interrupts = <16 2>;
83 }; 86 };
84 87
85 /* On-card I2C */ 88 /* On-card I2C */
86 i2c@3000 { 89 i2c@3000 {
87 #address-cells = <1>; 90 #address-cells = <1>;
88 #size-cells = <0>; 91 #size-cells = <0>;
89 cell-index = <0>; 92 cell-index = <0>;
90 compatible = "fsl-i2c" 93 compatible = "fsl-i2c";
91 reg = <0x3000 0x100>; 94 reg = <0x3000 0x100>;
92 interrupts = <43 2>; 95 interrupts = <43 2>;
93 interrupt-parent = <&m 96 interrupt-parent = <&mpic>;
94 dfsrr; 97 dfsrr;
95 98
96 /* 99 /*
97 * Board GPIO: 100 * Board GPIO:
98 * 0: BRD_CFG0 (1 101 * 0: BRD_CFG0 (1: P14 IO present)
99 * 1: BRD_CFG1 (1 102 * 1: BRD_CFG1 (1: FP ethernet present)
100 * 2: BRD_CFG2 (1 103 * 2: BRD_CFG2 (1: XMC IO present)
101 * 3: XMC root co 104 * 3: XMC root complex indicator
102 * 4: Flash boot 105 * 4: Flash boot device indicator
103 * 5: Flash write 106 * 5: Flash write protect enable
104 * 6: PMC monarch 107 * 6: PMC monarch indicator
105 * 7: PMC EREADY 108 * 7: PMC EREADY
106 */ 109 */
107 gpio1: gpio@18 { 110 gpio1: gpio@18 {
108 compatible = " 111 compatible = "nxp,pca9556";
109 reg = <0x18>; 112 reg = <0x18>;
110 #gpio-cells = 113 #gpio-cells = <2>;
111 gpio-controlle 114 gpio-controller;
112 polarity = <0x 115 polarity = <0x00>;
113 }; 116 };
114 117
115 /* P14 GPIO */ 118 /* P14 GPIO */
116 gpio2: gpio@19 { 119 gpio2: gpio@19 {
117 compatible = " 120 compatible = "nxp,pca9556";
118 reg = <0x19>; 121 reg = <0x19>;
119 #gpio-cells = 122 #gpio-cells = <2>;
120 gpio-controlle 123 gpio-controller;
121 polarity = <0x 124 polarity = <0x00>;
122 }; 125 };
123 126
124 eeprom@50 { 127 eeprom@50 {
125 compatible = " 128 compatible = "atmel,at24c16";
126 reg = <0x50>; 129 reg = <0x50>;
127 }; 130 };
128 131
129 rtc@68 { 132 rtc@68 {
130 compatible = " 133 compatible = "st,m41t00",
131 " 134 "dallas,ds1338";
132 reg = <0x68>; 135 reg = <0x68>;
133 }; 136 };
134 137
135 dtt@34 { !! 138 dtt@48 {
136 compatible = " 139 compatible = "maxim,max1237";
137 reg = <0x34>; 140 reg = <0x34>;
138 }; 141 };
139 }; 142 };
140 143
141 /* Off-card I2C */ 144 /* Off-card I2C */
142 i2c@3100 { 145 i2c@3100 {
143 #address-cells = <1>; 146 #address-cells = <1>;
144 #size-cells = <0>; 147 #size-cells = <0>;
145 cell-index = <1>; 148 cell-index = <1>;
146 compatible = "fsl-i2c" 149 compatible = "fsl-i2c";
147 reg = <0x3100 0x100>; 150 reg = <0x3100 0x100>;
148 interrupts = <43 2>; 151 interrupts = <43 2>;
149 interrupt-parent = <&m 152 interrupt-parent = <&mpic>;
150 dfsrr; 153 dfsrr;
151 }; 154 };
152 155
153 dma@21300 { 156 dma@21300 {
154 #address-cells = <1>; 157 #address-cells = <1>;
155 #size-cells = <1>; 158 #size-cells = <1>;
156 compatible = "fsl,mpc8 159 compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
157 reg = <0x21300 0x4>; 160 reg = <0x21300 0x4>;
158 ranges = <0x0 0x21100 161 ranges = <0x0 0x21100 0x200>;
159 cell-index = <0>; 162 cell-index = <0>;
160 dma-channel@0 { 163 dma-channel@0 {
161 compatible = " 164 compatible = "fsl,mpc8548-dma-channel",
162 165 "fsl,eloplus-dma-channel";
163 reg = <0x0 0x8 166 reg = <0x0 0x80>;
164 cell-index = < 167 cell-index = <0>;
165 interrupt-pare 168 interrupt-parent = <&mpic>;
166 interrupts = < 169 interrupts = <20 2>;
167 }; 170 };
168 dma-channel@80 { 171 dma-channel@80 {
169 compatible = " 172 compatible = "fsl,mpc8548-dma-channel",
170 173 "fsl,eloplus-dma-channel";
171 reg = <0x80 0x 174 reg = <0x80 0x80>;
172 cell-index = < 175 cell-index = <1>;
173 interrupt-pare 176 interrupt-parent = <&mpic>;
174 interrupts = < 177 interrupts = <21 2>;
175 }; 178 };
176 dma-channel@100 { 179 dma-channel@100 {
177 compatible = " 180 compatible = "fsl,mpc8548-dma-channel",
178 181 "fsl,eloplus-dma-channel";
179 reg = <0x100 0 182 reg = <0x100 0x80>;
180 cell-index = < 183 cell-index = <2>;
181 interrupt-pare 184 interrupt-parent = <&mpic>;
182 interrupts = < 185 interrupts = <22 2>;
183 }; 186 };
184 dma-channel@180 { 187 dma-channel@180 {
185 compatible = " 188 compatible = "fsl,mpc8548-dma-channel",
186 189 "fsl,eloplus-dma-channel";
187 reg = <0x180 0 190 reg = <0x180 0x80>;
188 cell-index = < 191 cell-index = <3>;
189 interrupt-pare 192 interrupt-parent = <&mpic>;
190 interrupts = < 193 interrupts = <23 2>;
191 }; 194 };
192 }; 195 };
193 196
194 /* eTSEC1: Front panel port 0 197 /* eTSEC1: Front panel port 0 */
195 enet0: ethernet@24000 { 198 enet0: ethernet@24000 {
196 #address-cells = <1>; 199 #address-cells = <1>;
197 #size-cells = <1>; 200 #size-cells = <1>;
198 cell-index = <0>; 201 cell-index = <0>;
199 device_type = "network 202 device_type = "network";
200 model = "eTSEC"; 203 model = "eTSEC";
201 compatible = "gianfar" 204 compatible = "gianfar";
202 reg = <0x24000 0x1000> 205 reg = <0x24000 0x1000>;
203 ranges = <0x0 0x24000 206 ranges = <0x0 0x24000 0x1000>;
204 local-mac-address = [ 207 local-mac-address = [ 00 00 00 00 00 00 ];
205 interrupts = <29 2 30 208 interrupts = <29 2 30 2 34 2>;
206 interrupt-parent = <&m 209 interrupt-parent = <&mpic>;
207 tbi-handle = <&tbi0>; 210 tbi-handle = <&tbi0>;
208 phy-handle = <&phy0>; 211 phy-handle = <&phy0>;
209 212
210 mdio@520 { 213 mdio@520 {
211 #address-cells 214 #address-cells = <1>;
212 #size-cells = 215 #size-cells = <0>;
213 compatible = " 216 compatible = "fsl,gianfar-mdio";
214 reg = <0x520 0 217 reg = <0x520 0x20>;
215 218
216 phy0: ethernet 219 phy0: ethernet-phy@1 {
217 interr 220 interrupt-parent = <&mpic>;
218 interr 221 interrupts = <8 1>;
219 reg = 222 reg = <0x1>;
220 }; 223 };
221 phy1: ethernet 224 phy1: ethernet-phy@2 {
222 interr 225 interrupt-parent = <&mpic>;
223 interr 226 interrupts = <8 1>;
224 reg = 227 reg = <0x2>;
225 }; 228 };
226 phy2: ethernet 229 phy2: ethernet-phy@3 {
227 interr 230 interrupt-parent = <&mpic>;
228 interr 231 interrupts = <8 1>;
229 reg = 232 reg = <0x3>;
230 }; 233 };
231 phy3: ethernet 234 phy3: ethernet-phy@4 {
232 interr 235 interrupt-parent = <&mpic>;
233 interr 236 interrupts = <8 1>;
234 reg = 237 reg = <0x4>;
235 }; 238 };
236 tbi0: tbi-phy@ 239 tbi0: tbi-phy@11 {
237 reg = 240 reg = <0x11>;
238 device 241 device_type = "tbi-phy";
239 }; 242 };
240 }; 243 };
241 }; 244 };
242 245
243 /* eTSEC2: Front panel port 1 246 /* eTSEC2: Front panel port 1 */
244 enet1: ethernet@25000 { 247 enet1: ethernet@25000 {
245 #address-cells = <1>; 248 #address-cells = <1>;
246 #size-cells = <1>; 249 #size-cells = <1>;
247 cell-index = <1>; 250 cell-index = <1>;
248 device_type = "network 251 device_type = "network";
249 model = "eTSEC"; 252 model = "eTSEC";
250 compatible = "gianfar" 253 compatible = "gianfar";
251 reg = <0x25000 0x1000> 254 reg = <0x25000 0x1000>;
252 ranges = <0x0 0x25000 255 ranges = <0x0 0x25000 0x1000>;
253 local-mac-address = [ 256 local-mac-address = [ 00 00 00 00 00 00 ];
254 interrupts = <35 2 36 257 interrupts = <35 2 36 2 40 2>;
255 interrupt-parent = <&m 258 interrupt-parent = <&mpic>;
256 tbi-handle = <&tbi1>; 259 tbi-handle = <&tbi1>;
257 phy-handle = <&phy1>; 260 phy-handle = <&phy1>;
258 261
259 mdio@520 { 262 mdio@520 {
260 #address-cells 263 #address-cells = <1>;
261 #size-cells = 264 #size-cells = <0>;
262 compatible = " 265 compatible = "fsl,gianfar-tbi";
263 reg = <0x520 0 266 reg = <0x520 0x20>;
264 267
265 tbi1: tbi-phy@ 268 tbi1: tbi-phy@11 {
266 reg = 269 reg = <0x11>;
267 device 270 device_type = "tbi-phy";
268 }; 271 };
269 }; 272 };
270 }; 273 };
271 274
272 /* eTSEC3: Rear panel port 2 * 275 /* eTSEC3: Rear panel port 2 */
273 enet2: ethernet@26000 { 276 enet2: ethernet@26000 {
274 #address-cells = <1>; 277 #address-cells = <1>;
275 #size-cells = <1>; 278 #size-cells = <1>;
276 cell-index = <2>; 279 cell-index = <2>;
277 device_type = "network 280 device_type = "network";
278 model = "eTSEC"; 281 model = "eTSEC";
279 compatible = "gianfar" 282 compatible = "gianfar";
280 reg = <0x26000 0x1000> 283 reg = <0x26000 0x1000>;
281 ranges = <0x0 0x26000 284 ranges = <0x0 0x26000 0x1000>;
282 local-mac-address = [ 285 local-mac-address = [ 00 00 00 00 00 00 ];
283 interrupts = <31 2 32 286 interrupts = <31 2 32 2 33 2>;
284 interrupt-parent = <&m 287 interrupt-parent = <&mpic>;
285 tbi-handle = <&tbi2>; 288 tbi-handle = <&tbi2>;
286 phy-handle = <&phy2>; 289 phy-handle = <&phy2>;
287 290
288 mdio@520 { 291 mdio@520 {
289 #address-cells 292 #address-cells = <1>;
290 #size-cells = 293 #size-cells = <0>;
291 compatible = " 294 compatible = "fsl,gianfar-tbi";
292 reg = <0x520 0 295 reg = <0x520 0x20>;
293 296
294 tbi2: tbi-phy@ 297 tbi2: tbi-phy@11 {
295 reg = 298 reg = <0x11>;
296 device 299 device_type = "tbi-phy";
297 }; 300 };
298 }; 301 };
299 }; 302 };
300 303
301 /* eTSEC4: Rear panel port 3 * 304 /* eTSEC4: Rear panel port 3 */
302 enet3: ethernet@27000 { 305 enet3: ethernet@27000 {
303 #address-cells = <1>; 306 #address-cells = <1>;
304 #size-cells = <1>; 307 #size-cells = <1>;
305 cell-index = <3>; 308 cell-index = <3>;
306 device_type = "network 309 device_type = "network";
307 model = "eTSEC"; 310 model = "eTSEC";
308 compatible = "gianfar" 311 compatible = "gianfar";
309 reg = <0x27000 0x1000> 312 reg = <0x27000 0x1000>;
310 ranges = <0x0 0x27000 313 ranges = <0x0 0x27000 0x1000>;
311 local-mac-address = [ 314 local-mac-address = [ 00 00 00 00 00 00 ];
312 interrupts = <37 2 38 315 interrupts = <37 2 38 2 39 2>;
313 interrupt-parent = <&m 316 interrupt-parent = <&mpic>;
314 tbi-handle = <&tbi3>; 317 tbi-handle = <&tbi3>;
315 phy-handle = <&phy3>; 318 phy-handle = <&phy3>;
316 319
317 mdio@520 { 320 mdio@520 {
318 #address-cells 321 #address-cells = <1>;
319 #size-cells = 322 #size-cells = <0>;
320 compatible = " 323 compatible = "fsl,gianfar-tbi";
321 reg = <0x520 0 324 reg = <0x520 0x20>;
322 325
323 tbi3: tbi-phy@ 326 tbi3: tbi-phy@11 {
324 reg = 327 reg = <0x11>;
325 device 328 device_type = "tbi-phy";
326 }; 329 };
327 }; 330 };
328 }; 331 };
329 332
330 serial0: serial@4500 { 333 serial0: serial@4500 {
331 cell-index = <0>; 334 cell-index = <0>;
332 device_type = "serial" 335 device_type = "serial";
333 compatible = "fsl,ns16 336 compatible = "fsl,ns16550", "ns16550";
334 reg = <0x4500 0x100>; 337 reg = <0x4500 0x100>;
335 clock-frequency = <0>; 338 clock-frequency = <0>;
336 current-speed = <11520 339 current-speed = <115200>;
337 interrupts = <42 2>; 340 interrupts = <42 2>;
338 interrupt-parent = <&m 341 interrupt-parent = <&mpic>;
339 }; 342 };
340 343
341 serial1: serial@4600 { 344 serial1: serial@4600 {
342 cell-index = <1>; 345 cell-index = <1>;
343 device_type = "serial" 346 device_type = "serial";
344 compatible = "fsl,ns16 347 compatible = "fsl,ns16550", "ns16550";
345 reg = <0x4600 0x100>; 348 reg = <0x4600 0x100>;
346 clock-frequency = <0>; 349 clock-frequency = <0>;
347 current-speed = <11520 350 current-speed = <115200>;
348 interrupts = <42 2>; 351 interrupts = <42 2>;
349 interrupt-parent = <&m 352 interrupt-parent = <&mpic>;
350 }; 353 };
351 354
352 global-utilities@e0000 { 355 global-utilities@e0000 { // global utilities reg
353 compatible = "fsl,mpc8 356 compatible = "fsl,mpc8548-guts";
354 reg = <0xe0000 0x1000> 357 reg = <0xe0000 0x1000>;
355 fsl,has-rstcr; 358 fsl,has-rstcr;
356 }; 359 };
357 360
358 mpic: pic@40000 { 361 mpic: pic@40000 {
359 interrupt-controller; 362 interrupt-controller;
360 #address-cells = <0>; 363 #address-cells = <0>;
361 #interrupt-cells = <2> 364 #interrupt-cells = <2>;
362 reg = <0x40000 0x40000 365 reg = <0x40000 0x40000>;
363 compatible = "chrp,ope 366 compatible = "chrp,open-pic";
364 device_type = "open-pi 367 device_type = "open-pic";
365 }; 368 };
366 }; 369 };
367 370
368 localbus@ef005000 { 371 localbus@ef005000 {
369 compatible = "fsl,mpc8548-loca 372 compatible = "fsl,mpc8548-localbus", "fsl,pq3-localbus",
370 "simple-bus"; 373 "simple-bus";
371 #address-cells = <2>; 374 #address-cells = <2>;
372 #size-cells = <1>; 375 #size-cells = <1>;
373 reg = <0xef005000 0x100>; 376 reg = <0xef005000 0x100>; // BRx, ORx, etc.
374 interrupt-parent = <&mpic>; 377 interrupt-parent = <&mpic>;
375 interrupts = <19 2>; 378 interrupts = <19 2>;
376 379
377 ranges = < 380 ranges = <
378 0 0x0 0xfc000000 0x040 381 0 0x0 0xfc000000 0x04000000 // NOR boot flash
379 1 0x0 0xf8000000 0x040 382 1 0x0 0xf8000000 0x04000000 // NOR expansion flash
380 2 0x0 0xef800000 0x000 383 2 0x0 0xef800000 0x00010000 // NAND CE1
381 3 0x0 0xef840000 0x000 384 3 0x0 0xef840000 0x00010000 // NAND CE2
382 >; 385 >;
383 386
384 nor-boot@0,0 { 387 nor-boot@0,0 {
385 #address-cells = <1>; 388 #address-cells = <1>;
386 #size-cells = <1>; 389 #size-cells = <1>;
387 compatible = "cfi-flas 390 compatible = "cfi-flash";
388 reg = <0 0x0 0x4000000 391 reg = <0 0x0 0x4000000>;
389 bank-width = <2>; 392 bank-width = <2>;
390 393
391 partition@0 { 394 partition@0 {
392 label = "Prima 395 label = "Primary OS";
393 reg = <0x00000 396 reg = <0x00000000 0x180000>;
394 }; 397 };
395 partition@180000 { 398 partition@180000 {
396 label = "Secon 399 label = "Secondary OS";
397 reg = <0x00180 400 reg = <0x00180000 0x180000>;
398 }; 401 };
399 partition@300000 { 402 partition@300000 {
400 label = "User" 403 label = "User";
401 reg = <0x00300 404 reg = <0x00300000 0x3c80000>;
402 }; 405 };
403 partition@3f80000 { 406 partition@3f80000 {
404 label = "Boot 407 label = "Boot firmware";
405 reg = <0x03f80 408 reg = <0x03f80000 0x80000>;
406 }; 409 };
407 }; 410 };
408 411
409 nor-alternate@1,0 { 412 nor-alternate@1,0 {
410 #address-cells = <1>; 413 #address-cells = <1>;
411 #size-cells = <1>; 414 #size-cells = <1>;
412 compatible = "cfi-flas 415 compatible = "cfi-flash";
413 reg = <1 0x0 0x4000000 416 reg = <1 0x0 0x4000000>;
414 bank-width = <2>; 417 bank-width = <2>;
415 418
416 partition@0 { 419 partition@0 {
417 label = "Files 420 label = "Filesystem";
418 reg = <0x00000 421 reg = <0x00000000 0x3f80000>;
419 }; 422 };
420 partition@3f80000 { 423 partition@3f80000 {
421 label = "Alter 424 label = "Alternate boot firmware";
422 reg = <0x03f80 425 reg = <0x03f80000 0x80000>;
423 }; 426 };
424 }; 427 };
425 428
426 nand@2,0 { 429 nand@2,0 {
427 #address-cells = <1>; 430 #address-cells = <1>;
428 #size-cells = <1>; 431 #size-cells = <1>;
429 compatible = "xes,addr 432 compatible = "xes,address-ctl-nand";
430 reg = <2 0x0 0x10000>; 433 reg = <2 0x0 0x10000>;
431 cle-line = <0x8>; 434 cle-line = <0x8>; /* CLE tied to A3 */
432 ale-line = <0x10>; 435 ale-line = <0x10>; /* ALE tied to A4 */
433 436
434 /* U-Boot should fix t 437 /* U-Boot should fix this up */
435 partition@0 { 438 partition@0 {
436 label = "NAND 439 label = "NAND Filesystem";
437 reg = <0 0x400 440 reg = <0 0x40000000>;
438 }; 441 };
439 }; 442 };
440 }; 443 };
441 444
442 /* PMC interface */ 445 /* PMC interface */
443 pci0: pci@ef008000 { 446 pci0: pci@ef008000 {
444 #interrupt-cells = <1>; 447 #interrupt-cells = <1>;
445 #size-cells = <2>; 448 #size-cells = <2>;
446 #address-cells = <3>; 449 #address-cells = <3>;
447 compatible = "fsl,mpc8540-pcix 450 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
448 device_type = "pci"; 451 device_type = "pci";
449 reg = <0xef008000 0x1000>; 452 reg = <0xef008000 0x1000>;
450 clock-frequency = <33333333>; 453 clock-frequency = <33333333>;
451 interrupt-map-mask = <0xf800 0 454 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
452 interrupt-map = < 455 interrupt-map = <
453 /* IDSEL */ 456 /* IDSEL */
454 0xe000 0 0 1 457 0xe000 0 0 1 &mpic 2 1
455 0xe000 0 0 2 458 0xe000 0 0 2 &mpic 3 1>;
456 459
457 interrupt-parent = <&mpic>; 460 interrupt-parent = <&mpic>;
458 interrupts = <24 2>; 461 interrupts = <24 2>;
459 bus-range = <0 0>; 462 bus-range = <0 0>;
460 ranges = <0x02000000 0 0x80000 463 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x40000000
461 0x01000000 0 0x00000 464 0x01000000 0 0x00000000 0xe8000000 0 0x00800000>;
462 }; 465 };
463 466
464 /* XMC PCIe is not yet enabled in U-Bo 467 /* XMC PCIe is not yet enabled in U-Boot on XPedite5200 */
465 }; 468 };
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