1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * Copyright (C) 2008 Extreme Engineering Solu 3 * Copyright (C) 2008 Extreme Engineering Solutions, Inc.
4 * Based on MPC8572DS device tree from Freesca 4 * Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
5 * 5 *
6 * XPedite5301 PMC/XMC module based on MPC8572 6 * XPedite5301 PMC/XMC module based on MPC8572E
7 */ 7 */
8 8
9 /dts-v1/; 9 /dts-v1/;
10 / { 10 / {
11 model = "xes,xpedite5301"; 11 model = "xes,xpedite5301";
12 compatible = "xes,xpedite5301", "xes,M 12 compatible = "xes,xpedite5301", "xes,MPC8572";
13 #address-cells = <2>; 13 #address-cells = <2>;
14 #size-cells = <2>; 14 #size-cells = <2>;
15 form-factor = "PMC/XMC"; 15 form-factor = "PMC/XMC";
16 boot-bank = <0x0>; /* 0: Primary 16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
17 17
18 aliases { 18 aliases {
19 ethernet0 = &enet0; 19 ethernet0 = &enet0;
20 ethernet1 = &enet1; 20 ethernet1 = &enet1;
21 serial0 = &serial0; 21 serial0 = &serial0;
22 serial1 = &serial1; 22 serial1 = &serial1;
23 pci1 = &pci1; 23 pci1 = &pci1;
24 pci2 = &pci2; 24 pci2 = &pci2;
25 }; 25 };
26 26
27 cpus { 27 cpus {
28 #address-cells = <1>; 28 #address-cells = <1>;
29 #size-cells = <0>; 29 #size-cells = <0>;
30 30
31 PowerPC,8572@0 { 31 PowerPC,8572@0 {
32 device_type = "cpu"; 32 device_type = "cpu";
33 reg = <0x0>; 33 reg = <0x0>;
34 d-cache-line-size = <3 34 d-cache-line-size = <32>; // 32 bytes
35 i-cache-line-size = <3 35 i-cache-line-size = <32>; // 32 bytes
36 d-cache-size = <0x8000 36 d-cache-size = <0x8000>; // L1, 32K
37 i-cache-size = <0x8000 37 i-cache-size = <0x8000>; // L1, 32K
38 timebase-frequency = < 38 timebase-frequency = <0>;
39 bus-frequency = <0>; 39 bus-frequency = <0>;
40 clock-frequency = <0>; 40 clock-frequency = <0>;
41 next-level-cache = <&L 41 next-level-cache = <&L2>;
42 }; 42 };
43 43
44 PowerPC,8572@1 { 44 PowerPC,8572@1 {
45 device_type = "cpu"; 45 device_type = "cpu";
46 reg = <0x1>; 46 reg = <0x1>;
47 d-cache-line-size = <3 47 d-cache-line-size = <32>; // 32 bytes
48 i-cache-line-size = <3 48 i-cache-line-size = <32>; // 32 bytes
49 d-cache-size = <0x8000 49 d-cache-size = <0x8000>; // L1, 32K
50 i-cache-size = <0x8000 50 i-cache-size = <0x8000>; // L1, 32K
51 timebase-frequency = < 51 timebase-frequency = <0>;
52 bus-frequency = <0>; 52 bus-frequency = <0>;
53 clock-frequency = <0>; 53 clock-frequency = <0>;
54 next-level-cache = <&L 54 next-level-cache = <&L2>;
55 }; 55 };
56 }; 56 };
57 57
58 memory { 58 memory {
59 device_type = "memory"; 59 device_type = "memory";
60 reg = <0x0 0x0 0x0 0x0>; 60 reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
61 }; 61 };
62 62
63 localbus@ef005000 { 63 localbus@ef005000 {
64 #address-cells = <2>; 64 #address-cells = <2>;
65 #size-cells = <1>; 65 #size-cells = <1>;
66 compatible = "fsl,mpc8572-elbc 66 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
67 reg = <0 0xef005000 0 0x1000>; 67 reg = <0 0xef005000 0 0x1000>;
68 interrupts = <19 2>; 68 interrupts = <19 2>;
69 interrupt-parent = <&mpic>; 69 interrupt-parent = <&mpic>;
70 /* Local bus region mappings * 70 /* Local bus region mappings */
71 ranges = <0 0 0 0xf8000000 0x8 71 ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
72 1 0 0 0xf0000000 0x8 72 1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
73 2 0 0 0xef800000 0x4 73 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
74 3 0 0 0xef840000 0x4 74 3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */
75 75
76 nor-boot@0,0 { 76 nor-boot@0,0 {
77 compatible = "amd,s29g 77 compatible = "amd,s29gl01gp", "cfi-flash";
78 bank-width = <2>; 78 bank-width = <2>;
79 reg = <0 0 0x8000000>; 79 reg = <0 0 0x8000000>; /* 128MB */
80 #address-cells = <1>; 80 #address-cells = <1>;
81 #size-cells = <1>; 81 #size-cells = <1>;
82 partition@0 { 82 partition@0 {
83 label = "Prima 83 label = "Primary user space";
84 reg = <0x00000 84 reg = <0x00000000 0x6f00000>; /* 111 MB */
85 }; 85 };
86 partition@6f00000 { 86 partition@6f00000 {
87 label = "Prima 87 label = "Primary kernel";
88 reg = <0x6f000 88 reg = <0x6f00000 0x1000000>; /* 16 MB */
89 }; 89 };
90 partition@7f00000 { 90 partition@7f00000 {
91 label = "Prima 91 label = "Primary DTB";
92 reg = <0x7f000 92 reg = <0x7f00000 0x40000>; /* 256 KB */
93 }; 93 };
94 partition@7f40000 { 94 partition@7f40000 {
95 label = "Prima 95 label = "Primary U-Boot environment";
96 reg = <0x7f400 96 reg = <0x7f40000 0x40000>; /* 256 KB */
97 }; 97 };
98 partition@7f80000 { 98 partition@7f80000 {
99 label = "Prima 99 label = "Primary U-Boot";
100 reg = <0x7f800 100 reg = <0x7f80000 0x80000>; /* 512 KB */
101 read-only; 101 read-only;
102 }; 102 };
103 }; 103 };
104 104
105 nor-alternate@1,0 { 105 nor-alternate@1,0 {
106 compatible = "amd,s29g 106 compatible = "amd,s29gl01gp", "cfi-flash";
107 bank-width = <2>; 107 bank-width = <2>;
108 //reg = <0xf0000000 0x 108 //reg = <0xf0000000 0x08000000>; /* 128MB */
109 reg = <1 0 0x8000000>; 109 reg = <1 0 0x8000000>; /* 128MB */
110 #address-cells = <1>; 110 #address-cells = <1>;
111 #size-cells = <1>; 111 #size-cells = <1>;
112 partition@0 { 112 partition@0 {
113 label = "Secon 113 label = "Secondary user space";
114 reg = <0x00000 114 reg = <0x00000000 0x6f00000>; /* 111 MB */
115 }; 115 };
116 partition@6f00000 { 116 partition@6f00000 {
117 label = "Secon 117 label = "Secondary kernel";
118 reg = <0x6f000 118 reg = <0x6f00000 0x1000000>; /* 16 MB */
119 }; 119 };
120 partition@7f00000 { 120 partition@7f00000 {
121 label = "Secon 121 label = "Secondary DTB";
122 reg = <0x7f000 122 reg = <0x7f00000 0x40000>; /* 256 KB */
123 }; 123 };
124 partition@7f40000 { 124 partition@7f40000 {
125 label = "Secon 125 label = "Secondary U-Boot environment";
126 reg = <0x7f400 126 reg = <0x7f40000 0x40000>; /* 256 KB */
127 }; 127 };
128 partition@7f80000 { 128 partition@7f80000 {
129 label = "Secon 129 label = "Secondary U-Boot";
130 reg = <0x7f800 130 reg = <0x7f80000 0x80000>; /* 512 KB */
131 read-only; 131 read-only;
132 }; 132 };
133 }; 133 };
134 134
135 nand@2,0 { 135 nand@2,0 {
136 #address-cells = <1>; 136 #address-cells = <1>;
137 #size-cells = <1>; 137 #size-cells = <1>;
138 /* 138 /*
139 * Actual part could b 139 * Actual part could be ST Micro NAND08GW3B2A (1 GB),
140 * Micron MT29F8G08DAA 140 * Micron MT29F8G08DAA (2x 512 MB), or Micron
141 * MT29F16G08FAA (2x 1 141 * MT29F16G08FAA (2x 1 GB), depending on the build
142 * configuration 142 * configuration
143 */ 143 */
144 compatible = "fsl,mpc8 144 compatible = "fsl,mpc8572-fcm-nand",
145 "fsl,elbc 145 "fsl,elbc-fcm-nand";
146 reg = <2 0 0x40000>; 146 reg = <2 0 0x40000>;
147 /* U-Boot should fix t 147 /* U-Boot should fix this up if chip size > 1 GB */
148 partition@0 { 148 partition@0 {
149 label = "NAND 149 label = "NAND Filesystem";
150 reg = <0 0x400 150 reg = <0 0x40000000>;
151 }; 151 };
152 }; 152 };
153 153
154 }; 154 };
155 155
156 soc8572@ef000000 { 156 soc8572@ef000000 {
157 #address-cells = <1>; 157 #address-cells = <1>;
158 #size-cells = <1>; 158 #size-cells = <1>;
159 device_type = "soc"; 159 device_type = "soc";
160 compatible = "fsl,mpc8572-immr 160 compatible = "fsl,mpc8572-immr", "simple-bus";
161 ranges = <0x0 0 0xef000000 0x1 161 ranges = <0x0 0 0xef000000 0x100000>;
162 bus-frequency = <0>; 162 bus-frequency = <0>; // Filled out by uboot.
163 163
164 ecm-law@0 { 164 ecm-law@0 {
165 compatible = "fsl,ecm- 165 compatible = "fsl,ecm-law";
166 reg = <0x0 0x1000>; 166 reg = <0x0 0x1000>;
167 fsl,num-laws = <12>; 167 fsl,num-laws = <12>;
168 }; 168 };
169 169
170 ecm@1000 { 170 ecm@1000 {
171 compatible = "fsl,mpc8 171 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
172 reg = <0x1000 0x1000>; 172 reg = <0x1000 0x1000>;
173 interrupts = <17 2>; 173 interrupts = <17 2>;
174 interrupt-parent = <&m 174 interrupt-parent = <&mpic>;
175 }; 175 };
176 176
177 memory-controller@2000 { 177 memory-controller@2000 {
178 compatible = "fsl,mpc8 178 compatible = "fsl,mpc8572-memory-controller";
179 reg = <0x2000 0x1000>; 179 reg = <0x2000 0x1000>;
180 interrupt-parent = <&m 180 interrupt-parent = <&mpic>;
181 interrupts = <18 2>; 181 interrupts = <18 2>;
182 }; 182 };
183 183
184 memory-controller@6000 { 184 memory-controller@6000 {
185 compatible = "fsl,mpc8 185 compatible = "fsl,mpc8572-memory-controller";
186 reg = <0x6000 0x1000>; 186 reg = <0x6000 0x1000>;
187 interrupt-parent = <&m 187 interrupt-parent = <&mpic>;
188 interrupts = <18 2>; 188 interrupts = <18 2>;
189 }; 189 };
190 190
191 L2: l2-cache-controller@20000 191 L2: l2-cache-controller@20000 {
192 compatible = "fsl,mpc8 192 compatible = "fsl,mpc8572-l2-cache-controller";
193 reg = <0x20000 0x1000> 193 reg = <0x20000 0x1000>;
194 cache-line-size = <32> 194 cache-line-size = <32>; // 32 bytes
195 cache-size = <0x100000 195 cache-size = <0x100000>; // L2, 1M
196 interrupt-parent = <&m 196 interrupt-parent = <&mpic>;
197 interrupts = <16 2>; 197 interrupts = <16 2>;
198 }; 198 };
199 199
200 i2c@3000 { 200 i2c@3000 {
201 #address-cells = <1>; 201 #address-cells = <1>;
202 #size-cells = <0>; 202 #size-cells = <0>;
203 cell-index = <0>; 203 cell-index = <0>;
204 compatible = "fsl-i2c" 204 compatible = "fsl-i2c";
205 reg = <0x3000 0x100>; 205 reg = <0x3000 0x100>;
206 interrupts = <43 2>; 206 interrupts = <43 2>;
207 interrupt-parent = <&m 207 interrupt-parent = <&mpic>;
208 dfsrr; 208 dfsrr;
209 209
210 temp-sensor@48 { 210 temp-sensor@48 {
211 compatible = " 211 compatible = "dallas,ds1631", "dallas,ds1621";
212 reg = <0x48>; 212 reg = <0x48>;
213 }; 213 };
214 214
215 temp-sensor@4c { 215 temp-sensor@4c {
216 compatible = " 216 compatible = "adi,adt7461";
217 reg = <0x4c>; 217 reg = <0x4c>;
218 }; 218 };
219 219
220 cpu-supervisor@51 { 220 cpu-supervisor@51 {
221 compatible = " 221 compatible = "dallas,ds4510";
222 reg = <0x51>; 222 reg = <0x51>;
223 }; 223 };
224 224
225 eeprom@54 { 225 eeprom@54 {
226 compatible = " 226 compatible = "atmel,at24c128b";
227 reg = <0x54>; 227 reg = <0x54>;
228 }; 228 };
229 229
230 rtc@68 { 230 rtc@68 {
231 compatible = " 231 compatible = "st,m41t00",
232 " 232 "dallas,ds1338";
233 reg = <0x68>; 233 reg = <0x68>;
234 }; 234 };
235 235
236 pcie-switch@70 { 236 pcie-switch@70 {
237 compatible = " 237 compatible = "plx,pex8518";
238 reg = <0x70>; 238 reg = <0x70>;
239 }; 239 };
240 240
241 gpio1: gpio@18 { 241 gpio1: gpio@18 {
242 compatible = " 242 compatible = "nxp,pca9557";
243 reg = <0x18>; 243 reg = <0x18>;
244 #gpio-cells = 244 #gpio-cells = <2>;
245 gpio-controlle 245 gpio-controller;
246 polarity = <0x 246 polarity = <0x00>;
247 }; 247 };
248 248
249 gpio2: gpio@1c { 249 gpio2: gpio@1c {
250 compatible = " 250 compatible = "nxp,pca9557";
251 reg = <0x1c>; 251 reg = <0x1c>;
252 #gpio-cells = 252 #gpio-cells = <2>;
253 gpio-controlle 253 gpio-controller;
254 polarity = <0x 254 polarity = <0x00>;
255 }; 255 };
256 256
257 gpio3: gpio@1e { 257 gpio3: gpio@1e {
258 compatible = " 258 compatible = "nxp,pca9557";
259 reg = <0x1e>; 259 reg = <0x1e>;
260 #gpio-cells = 260 #gpio-cells = <2>;
261 gpio-controlle 261 gpio-controller;
262 polarity = <0x 262 polarity = <0x00>;
263 }; 263 };
264 264
265 gpio4: gpio@1f { 265 gpio4: gpio@1f {
266 compatible = " 266 compatible = "nxp,pca9557";
267 reg = <0x1f>; 267 reg = <0x1f>;
268 #gpio-cells = 268 #gpio-cells = <2>;
269 gpio-controlle 269 gpio-controller;
270 polarity = <0x 270 polarity = <0x00>;
271 }; 271 };
272 }; 272 };
273 273
274 i2c@3100 { 274 i2c@3100 {
275 #address-cells = <1>; 275 #address-cells = <1>;
276 #size-cells = <0>; 276 #size-cells = <0>;
277 cell-index = <1>; 277 cell-index = <1>;
278 compatible = "fsl-i2c" 278 compatible = "fsl-i2c";
279 reg = <0x3100 0x100>; 279 reg = <0x3100 0x100>;
280 interrupts = <43 2>; 280 interrupts = <43 2>;
281 interrupt-parent = <&m 281 interrupt-parent = <&mpic>;
282 dfsrr; 282 dfsrr;
283 }; 283 };
284 284
285 dma@c300 { 285 dma@c300 {
286 #address-cells = <1>; 286 #address-cells = <1>;
287 #size-cells = <1>; 287 #size-cells = <1>;
288 compatible = "fsl,mpc8 288 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
289 reg = <0xc300 0x4>; 289 reg = <0xc300 0x4>;
290 ranges = <0x0 0xc100 0 290 ranges = <0x0 0xc100 0x200>;
291 cell-index = <1>; 291 cell-index = <1>;
292 dma-channel@0 { 292 dma-channel@0 {
293 compatible = " 293 compatible = "fsl,mpc8572-dma-channel",
294 294 "fsl,eloplus-dma-channel";
295 reg = <0x0 0x8 295 reg = <0x0 0x80>;
296 cell-index = < 296 cell-index = <0>;
297 interrupt-pare 297 interrupt-parent = <&mpic>;
298 interrupts = < 298 interrupts = <76 2>;
299 }; 299 };
300 dma-channel@80 { 300 dma-channel@80 {
301 compatible = " 301 compatible = "fsl,mpc8572-dma-channel",
302 302 "fsl,eloplus-dma-channel";
303 reg = <0x80 0x 303 reg = <0x80 0x80>;
304 cell-index = < 304 cell-index = <1>;
305 interrupt-pare 305 interrupt-parent = <&mpic>;
306 interrupts = < 306 interrupts = <77 2>;
307 }; 307 };
308 dma-channel@100 { 308 dma-channel@100 {
309 compatible = " 309 compatible = "fsl,mpc8572-dma-channel",
310 310 "fsl,eloplus-dma-channel";
311 reg = <0x100 0 311 reg = <0x100 0x80>;
312 cell-index = < 312 cell-index = <2>;
313 interrupt-pare 313 interrupt-parent = <&mpic>;
314 interrupts = < 314 interrupts = <78 2>;
315 }; 315 };
316 dma-channel@180 { 316 dma-channel@180 {
317 compatible = " 317 compatible = "fsl,mpc8572-dma-channel",
318 318 "fsl,eloplus-dma-channel";
319 reg = <0x180 0 319 reg = <0x180 0x80>;
320 cell-index = < 320 cell-index = <3>;
321 interrupt-pare 321 interrupt-parent = <&mpic>;
322 interrupts = < 322 interrupts = <79 2>;
323 }; 323 };
324 }; 324 };
325 325
326 dma@21300 { 326 dma@21300 {
327 #address-cells = <1>; 327 #address-cells = <1>;
328 #size-cells = <1>; 328 #size-cells = <1>;
329 compatible = "fsl,mpc8 329 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
330 reg = <0x21300 0x4>; 330 reg = <0x21300 0x4>;
331 ranges = <0x0 0x21100 331 ranges = <0x0 0x21100 0x200>;
332 cell-index = <0>; 332 cell-index = <0>;
333 dma-channel@0 { 333 dma-channel@0 {
334 compatible = " 334 compatible = "fsl,mpc8572-dma-channel",
335 335 "fsl,eloplus-dma-channel";
336 reg = <0x0 0x8 336 reg = <0x0 0x80>;
337 cell-index = < 337 cell-index = <0>;
338 interrupt-pare 338 interrupt-parent = <&mpic>;
339 interrupts = < 339 interrupts = <20 2>;
340 }; 340 };
341 dma-channel@80 { 341 dma-channel@80 {
342 compatible = " 342 compatible = "fsl,mpc8572-dma-channel",
343 343 "fsl,eloplus-dma-channel";
344 reg = <0x80 0x 344 reg = <0x80 0x80>;
345 cell-index = < 345 cell-index = <1>;
346 interrupt-pare 346 interrupt-parent = <&mpic>;
347 interrupts = < 347 interrupts = <21 2>;
348 }; 348 };
349 dma-channel@100 { 349 dma-channel@100 {
350 compatible = " 350 compatible = "fsl,mpc8572-dma-channel",
351 351 "fsl,eloplus-dma-channel";
352 reg = <0x100 0 352 reg = <0x100 0x80>;
353 cell-index = < 353 cell-index = <2>;
354 interrupt-pare 354 interrupt-parent = <&mpic>;
355 interrupts = < 355 interrupts = <22 2>;
356 }; 356 };
357 dma-channel@180 { 357 dma-channel@180 {
358 compatible = " 358 compatible = "fsl,mpc8572-dma-channel",
359 359 "fsl,eloplus-dma-channel";
360 reg = <0x180 0 360 reg = <0x180 0x80>;
361 cell-index = < 361 cell-index = <3>;
362 interrupt-pare 362 interrupt-parent = <&mpic>;
363 interrupts = < 363 interrupts = <23 2>;
364 }; 364 };
365 }; 365 };
366 366
367 /* eTSEC 1 */ 367 /* eTSEC 1 */
368 enet0: ethernet@24000 { 368 enet0: ethernet@24000 {
369 #address-cells = <1>; 369 #address-cells = <1>;
370 #size-cells = <1>; 370 #size-cells = <1>;
371 cell-index = <0>; 371 cell-index = <0>;
372 device_type = "network 372 device_type = "network";
373 model = "eTSEC"; 373 model = "eTSEC";
374 compatible = "gianfar" 374 compatible = "gianfar";
375 reg = <0x24000 0x1000> 375 reg = <0x24000 0x1000>;
376 ranges = <0x0 0x24000 376 ranges = <0x0 0x24000 0x1000>;
377 local-mac-address = [ 377 local-mac-address = [ 00 00 00 00 00 00 ];
378 interrupts = <29 2 30 378 interrupts = <29 2 30 2 34 2>;
379 interrupt-parent = <&m 379 interrupt-parent = <&mpic>;
380 tbi-handle = <&tbi0>; 380 tbi-handle = <&tbi0>;
381 phy-handle = <&phy0>; 381 phy-handle = <&phy0>;
382 phy-connection-type = 382 phy-connection-type = "sgmii";
383 383
384 mdio@520 { 384 mdio@520 {
385 #address-cells 385 #address-cells = <1>;
386 #size-cells = 386 #size-cells = <0>;
387 compatible = " 387 compatible = "fsl,gianfar-mdio";
388 reg = <0x520 0 388 reg = <0x520 0x20>;
389 389
390 phy0: ethernet 390 phy0: ethernet-phy@1 {
391 interr 391 interrupt-parent = <&mpic>;
392 interr 392 interrupts = <8 1>;
393 reg = 393 reg = <0x1>;
394 }; 394 };
395 phy1: ethernet 395 phy1: ethernet-phy@2 {
396 interr 396 interrupt-parent = <&mpic>;
397 interr 397 interrupts = <8 1>;
398 reg = 398 reg = <0x2>;
399 }; 399 };
400 tbi0: tbi-phy@ 400 tbi0: tbi-phy@11 {
401 reg = 401 reg = <0x11>;
402 device 402 device_type = "tbi-phy";
403 }; 403 };
404 }; 404 };
405 }; 405 };
406 406
407 /* eTSEC 2 */ 407 /* eTSEC 2 */
408 enet1: ethernet@25000 { 408 enet1: ethernet@25000 {
409 #address-cells = <1>; 409 #address-cells = <1>;
410 #size-cells = <1>; 410 #size-cells = <1>;
411 cell-index = <1>; 411 cell-index = <1>;
412 device_type = "network 412 device_type = "network";
413 model = "eTSEC"; 413 model = "eTSEC";
414 compatible = "gianfar" 414 compatible = "gianfar";
415 reg = <0x25000 0x1000> 415 reg = <0x25000 0x1000>;
416 ranges = <0x0 0x25000 416 ranges = <0x0 0x25000 0x1000>;
417 local-mac-address = [ 417 local-mac-address = [ 00 00 00 00 00 00 ];
418 interrupts = <35 2 36 418 interrupts = <35 2 36 2 40 2>;
419 interrupt-parent = <&m 419 interrupt-parent = <&mpic>;
420 tbi-handle = <&tbi1>; 420 tbi-handle = <&tbi1>;
421 phy-handle = <&phy1>; 421 phy-handle = <&phy1>;
422 phy-connection-type = 422 phy-connection-type = "sgmii";
423 423
424 mdio@520 { 424 mdio@520 {
425 #address-cells 425 #address-cells = <1>;
426 #size-cells = 426 #size-cells = <0>;
427 compatible = " 427 compatible = "fsl,gianfar-tbi";
428 reg = <0x520 0 428 reg = <0x520 0x20>;
429 429
430 tbi1: tbi-phy@ 430 tbi1: tbi-phy@11 {
431 reg = 431 reg = <0x11>;
432 device 432 device_type = "tbi-phy";
433 }; 433 };
434 }; 434 };
435 }; 435 };
436 436
437 /* UART0 */ 437 /* UART0 */
438 serial0: serial@4500 { 438 serial0: serial@4500 {
439 cell-index = <0>; 439 cell-index = <0>;
440 device_type = "serial" 440 device_type = "serial";
441 compatible = "fsl,ns16 441 compatible = "fsl,ns16550", "ns16550";
442 reg = <0x4500 0x100>; 442 reg = <0x4500 0x100>;
443 clock-frequency = <0>; 443 clock-frequency = <0>;
444 interrupts = <42 2>; 444 interrupts = <42 2>;
445 interrupt-parent = <&m 445 interrupt-parent = <&mpic>;
446 }; 446 };
447 447
448 /* UART1 */ 448 /* UART1 */
449 serial1: serial@4600 { 449 serial1: serial@4600 {
450 cell-index = <1>; 450 cell-index = <1>;
451 device_type = "serial" 451 device_type = "serial";
452 compatible = "fsl,ns16 452 compatible = "fsl,ns16550", "ns16550";
453 reg = <0x4600 0x100>; 453 reg = <0x4600 0x100>;
454 clock-frequency = <0>; 454 clock-frequency = <0>;
455 interrupts = <42 2>; 455 interrupts = <42 2>;
456 interrupt-parent = <&m 456 interrupt-parent = <&mpic>;
457 }; 457 };
458 458
459 global-utilities@e0000 { 459 global-utilities@e0000 { //global utilities block
460 compatible = "fsl,mpc8 460 compatible = "fsl,mpc8572-guts";
461 reg = <0xe0000 0x1000> 461 reg = <0xe0000 0x1000>;
462 fsl,has-rstcr; 462 fsl,has-rstcr;
463 }; 463 };
464 464
465 msi@41600 { 465 msi@41600 {
466 compatible = "fsl,mpc8 466 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
467 reg = <0x41600 0x80>; 467 reg = <0x41600 0x80>;
468 msi-available-ranges = 468 msi-available-ranges = <0 0x100>;
469 interrupts = < 469 interrupts = <
470 0xe0 0 470 0xe0 0
471 0xe1 0 471 0xe1 0
472 0xe2 0 472 0xe2 0
473 0xe3 0 473 0xe3 0
474 0xe4 0 474 0xe4 0
475 0xe5 0 475 0xe5 0
476 0xe6 0 476 0xe6 0
477 0xe7 0>; 477 0xe7 0>;
478 interrupt-parent = <&m 478 interrupt-parent = <&mpic>;
479 }; 479 };
480 480
481 crypto@30000 { 481 crypto@30000 {
482 compatible = "fsl,sec3 482 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
483 "fsl,sec2 483 "fsl,sec2.1", "fsl,sec2.0";
484 reg = <0x30000 0x10000 484 reg = <0x30000 0x10000>;
485 interrupts = <45 2 58 485 interrupts = <45 2 58 2>;
486 interrupt-parent = <&m 486 interrupt-parent = <&mpic>;
487 fsl,num-channels = <4> 487 fsl,num-channels = <4>;
488 fsl,channel-fifo-len = 488 fsl,channel-fifo-len = <24>;
489 fsl,exec-units-mask = 489 fsl,exec-units-mask = <0x9fe>;
490 fsl,descriptor-types-m 490 fsl,descriptor-types-mask = <0x3ab0ebf>;
491 }; 491 };
492 492
493 mpic: pic@40000 { 493 mpic: pic@40000 {
494 interrupt-controller; 494 interrupt-controller;
495 #address-cells = <0>; 495 #address-cells = <0>;
496 #interrupt-cells = <2> 496 #interrupt-cells = <2>;
497 reg = <0x40000 0x40000 497 reg = <0x40000 0x40000>;
498 compatible = "chrp,ope 498 compatible = "chrp,open-pic";
499 device_type = "open-pi 499 device_type = "open-pic";
500 }; 500 };
501 501
502 gpio0: gpio@f000 { 502 gpio0: gpio@f000 {
503 compatible = "fsl,mpc8 503 compatible = "fsl,mpc8572-gpio";
504 reg = <0xf000 0x1000>; 504 reg = <0xf000 0x1000>;
505 interrupts = <47 2>; 505 interrupts = <47 2>;
506 interrupt-parent = <&m 506 interrupt-parent = <&mpic>;
507 #gpio-cells = <2>; 507 #gpio-cells = <2>;
508 gpio-controller; 508 gpio-controller;
509 }; 509 };
510 510
511 gpio-leds { 511 gpio-leds {
512 compatible = "gpio-led 512 compatible = "gpio-leds";
513 513
514 heartbeat { 514 heartbeat {
515 label = "Heart 515 label = "Heartbeat";
516 gpios = <&gpio 516 gpios = <&gpio0 4 1>;
517 linux,default- 517 linux,default-trigger = "heartbeat";
518 }; 518 };
519 519
520 yellow { 520 yellow {
521 label = "Yello 521 label = "Yellow";
522 gpios = <&gpio 522 gpios = <&gpio0 5 1>;
523 }; 523 };
524 524
525 red { 525 red {
526 label = "Red"; 526 label = "Red";
527 gpios = <&gpio 527 gpios = <&gpio0 6 1>;
528 }; 528 };
529 529
530 green { 530 green {
531 label = "Green 531 label = "Green";
532 gpios = <&gpio 532 gpios = <&gpio0 7 1>;
533 }; 533 };
534 }; 534 };
535 535
536 /* PME (pattern-matcher) */ 536 /* PME (pattern-matcher) */
537 pme@10000 { 537 pme@10000 {
538 compatible = "fsl,mpc8 538 compatible = "fsl,mpc8572-pme", "pme8572";
539 reg = <0x10000 0x5000> 539 reg = <0x10000 0x5000>;
540 interrupts = <57 2 64 540 interrupts = <57 2 64 2 65 2 66 2 67 2>;
541 interrupt-parent = <&m 541 interrupt-parent = <&mpic>;
542 }; 542 };
543 543
544 tlu@2f000 { 544 tlu@2f000 {
545 compatible = "fsl,mpc8 545 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
546 reg = <0x2f000 0x1000> 546 reg = <0x2f000 0x1000>;
547 interrupts = <61 2>; 547 interrupts = <61 2>;
548 interrupt-parent = <&m 548 interrupt-parent = <&mpic>;
549 }; 549 };
550 550
551 tlu@15000 { 551 tlu@15000 {
552 compatible = "fsl,mpc8 552 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
553 reg = <0x15000 0x1000> 553 reg = <0x15000 0x1000>;
554 interrupts = <75 2>; 554 interrupts = <75 2>;
555 interrupt-parent = <&m 555 interrupt-parent = <&mpic>;
556 }; 556 };
557 }; 557 };
558 558
559 /* 559 /*
560 * PCI Express controller 3 @ ef008000 560 * PCI Express controller 3 @ ef008000 is not used.
561 * This would have been pci0 on other 561 * This would have been pci0 on other mpc85xx platforms.
562 */ 562 */
563 563
564 /* PCI Express controller 2, wired to 564 /* PCI Express controller 2, wired to XMC P15 connector */
565 pci1: pcie@ef009000 { 565 pci1: pcie@ef009000 {
566 compatible = "fsl,mpc8548-pcie 566 compatible = "fsl,mpc8548-pcie";
567 device_type = "pci"; 567 device_type = "pci";
568 #interrupt-cells = <1>; 568 #interrupt-cells = <1>;
569 #size-cells = <2>; 569 #size-cells = <2>;
570 #address-cells = <3>; 570 #address-cells = <3>;
571 reg = <0 0xef009000 0 0x1000>; 571 reg = <0 0xef009000 0 0x1000>;
572 bus-range = <0 255>; 572 bus-range = <0 255>;
573 ranges = <0x2000000 0x0 0xc000 573 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
574 0x1000000 0x0 0x0000 574 0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x00010000>;
575 clock-frequency = <33333333>; 575 clock-frequency = <33333333>;
576 interrupt-parent = <&mpic>; 576 interrupt-parent = <&mpic>;
577 interrupts = <25 2>; 577 interrupts = <25 2>;
578 interrupt-map-mask = <0xf800 0 578 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
579 interrupt-map = < 579 interrupt-map = <
580 /* IDSEL 0x0 */ 580 /* IDSEL 0x0 */
581 0x0 0x0 0x0 0x1 &mpic 581 0x0 0x0 0x0 0x1 &mpic 0x4 0x1
582 0x0 0x0 0x0 0x2 &mpic 582 0x0 0x0 0x0 0x2 &mpic 0x5 0x1
583 0x0 0x0 0x0 0x3 &mpic 583 0x0 0x0 0x0 0x3 &mpic 0x6 0x1
584 0x0 0x0 0x0 0x4 &mpic 584 0x0 0x0 0x0 0x4 &mpic 0x7 0x1
585 >; 585 >;
586 pcie@0 { 586 pcie@0 {
587 reg = <0x00000000 0x00 587 reg = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
588 #size-cells = <2>; 588 #size-cells = <2>;
589 #address-cells = <3>; 589 #address-cells = <3>;
590 device_type = "pci"; 590 device_type = "pci";
591 ranges = <0x2000000 0x 591 ranges = <0x2000000 0x0 0xc0000000
592 0x2000000 0x 592 0x2000000 0x0 0xc0000000
593 0x0 0x100000 593 0x0 0x10000000
594 594
595 0x1000000 0x 595 0x1000000 0x0 0x0
596 0x1000000 0x 596 0x1000000 0x0 0x0
597 0x0 0x100000 597 0x0 0x100000>;
598 }; 598 };
599 }; 599 };
600 600
601 /* PCI Express controller 1, wired to 601 /* PCI Express controller 1, wired to PEX8112 for PMC interface */
602 pci2: pcie@ef00a000 { 602 pci2: pcie@ef00a000 {
603 compatible = "fsl,mpc8548-pcie 603 compatible = "fsl,mpc8548-pcie";
604 device_type = "pci"; 604 device_type = "pci";
605 #interrupt-cells = <1>; 605 #interrupt-cells = <1>;
606 #size-cells = <2>; 606 #size-cells = <2>;
607 #address-cells = <3>; 607 #address-cells = <3>;
608 reg = <0 0xef00a000 0 0x1000>; 608 reg = <0 0xef00a000 0 0x1000>;
609 bus-range = <0 255>; 609 bus-range = <0 255>;
610 ranges = <0x2000000 0x0 0x8000 610 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
611 0x1000000 0x0 0x0000 611 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
612 clock-frequency = <33333333>; 612 clock-frequency = <33333333>;
613 interrupt-parent = <&mpic>; 613 interrupt-parent = <&mpic>;
614 interrupts = <26 2>; 614 interrupts = <26 2>;
615 interrupt-map-mask = <0xf800 0 615 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
616 interrupt-map = < 616 interrupt-map = <
617 /* IDSEL 0x0 */ 617 /* IDSEL 0x0 */
618 0x0 0x0 0x0 0x1 &mpic 618 0x0 0x0 0x0 0x1 &mpic 0x0 0x1
619 0x0 0x0 0x0 0x2 &mpic 619 0x0 0x0 0x0 0x2 &mpic 0x1 0x1
620 0x0 0x0 0x0 0x3 &mpic 620 0x0 0x0 0x0 0x3 &mpic 0x2 0x1
621 0x0 0x0 0x0 0x4 &mpic 621 0x0 0x0 0x0 0x4 &mpic 0x3 0x1
622 >; 622 >;
623 pcie@0 { 623 pcie@0 {
624 reg = <0x0 0x0 0x0 0x0 624 reg = <0x0 0x0 0x0 0x0 0x0>;
625 #size-cells = <2>; 625 #size-cells = <2>;
626 #address-cells = <3>; 626 #address-cells = <3>;
627 device_type = "pci"; 627 device_type = "pci";
628 ranges = <0x2000000 0x 628 ranges = <0x2000000 0x0 0x80000000
629 0x2000000 0x 629 0x2000000 0x0 0x80000000
630 0x0 0x400000 630 0x0 0x40000000
631 631
632 0x1000000 0x 632 0x1000000 0x0 0x0
633 0x1000000 0x 633 0x1000000 0x0 0x0
634 0x0 0x100000 634 0x0 0x100000>;
635 }; 635 };
636 }; 636 };
637 }; 637 };
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