1 // SPDX-License-Identifier: GPL-2.0-only <<
2 /* 1 /*
3 * Copyright (C) 2008 Extreme Engineering Solu 2 * Copyright (C) 2008 Extreme Engineering Solutions, Inc.
4 * Based on MPC8572DS device tree from Freesca 3 * Based on MPC8572DS device tree from Freescale Semiconductor, Inc.
5 * 4 *
6 * XPedite5301 PMC/XMC module based on MPC8572 5 * XPedite5301 PMC/XMC module based on MPC8572E
>> 6 *
>> 7 * This is free software; you can redistribute it and/or modify
>> 8 * it under the terms of the GNU General Public License version 2 as
>> 9 * published by the Free Software Foundation.
7 */ 10 */
8 11
9 /dts-v1/; 12 /dts-v1/;
10 / { 13 / {
11 model = "xes,xpedite5301"; 14 model = "xes,xpedite5301";
12 compatible = "xes,xpedite5301", "xes,M 15 compatible = "xes,xpedite5301", "xes,MPC8572";
13 #address-cells = <2>; 16 #address-cells = <2>;
14 #size-cells = <2>; 17 #size-cells = <2>;
15 form-factor = "PMC/XMC"; 18 form-factor = "PMC/XMC";
16 boot-bank = <0x0>; /* 0: Primary 19 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
17 20
18 aliases { 21 aliases {
19 ethernet0 = &enet0; 22 ethernet0 = &enet0;
20 ethernet1 = &enet1; 23 ethernet1 = &enet1;
21 serial0 = &serial0; 24 serial0 = &serial0;
22 serial1 = &serial1; 25 serial1 = &serial1;
23 pci1 = &pci1; 26 pci1 = &pci1;
24 pci2 = &pci2; 27 pci2 = &pci2;
25 }; 28 };
26 29
27 cpus { 30 cpus {
28 #address-cells = <1>; 31 #address-cells = <1>;
29 #size-cells = <0>; 32 #size-cells = <0>;
30 33
31 PowerPC,8572@0 { 34 PowerPC,8572@0 {
32 device_type = "cpu"; 35 device_type = "cpu";
33 reg = <0x0>; 36 reg = <0x0>;
34 d-cache-line-size = <3 37 d-cache-line-size = <32>; // 32 bytes
35 i-cache-line-size = <3 38 i-cache-line-size = <32>; // 32 bytes
36 d-cache-size = <0x8000 39 d-cache-size = <0x8000>; // L1, 32K
37 i-cache-size = <0x8000 40 i-cache-size = <0x8000>; // L1, 32K
38 timebase-frequency = < 41 timebase-frequency = <0>;
39 bus-frequency = <0>; 42 bus-frequency = <0>;
40 clock-frequency = <0>; 43 clock-frequency = <0>;
41 next-level-cache = <&L 44 next-level-cache = <&L2>;
42 }; 45 };
43 46
44 PowerPC,8572@1 { 47 PowerPC,8572@1 {
45 device_type = "cpu"; 48 device_type = "cpu";
46 reg = <0x1>; 49 reg = <0x1>;
47 d-cache-line-size = <3 50 d-cache-line-size = <32>; // 32 bytes
48 i-cache-line-size = <3 51 i-cache-line-size = <32>; // 32 bytes
49 d-cache-size = <0x8000 52 d-cache-size = <0x8000>; // L1, 32K
50 i-cache-size = <0x8000 53 i-cache-size = <0x8000>; // L1, 32K
51 timebase-frequency = < 54 timebase-frequency = <0>;
52 bus-frequency = <0>; 55 bus-frequency = <0>;
53 clock-frequency = <0>; 56 clock-frequency = <0>;
54 next-level-cache = <&L 57 next-level-cache = <&L2>;
55 }; 58 };
56 }; 59 };
57 60
58 memory { 61 memory {
59 device_type = "memory"; 62 device_type = "memory";
60 reg = <0x0 0x0 0x0 0x0>; 63 reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
61 }; 64 };
62 65
63 localbus@ef005000 { 66 localbus@ef005000 {
64 #address-cells = <2>; 67 #address-cells = <2>;
65 #size-cells = <1>; 68 #size-cells = <1>;
66 compatible = "fsl,mpc8572-elbc 69 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
67 reg = <0 0xef005000 0 0x1000>; 70 reg = <0 0xef005000 0 0x1000>;
68 interrupts = <19 2>; 71 interrupts = <19 2>;
69 interrupt-parent = <&mpic>; 72 interrupt-parent = <&mpic>;
70 /* Local bus region mappings * 73 /* Local bus region mappings */
71 ranges = <0 0 0 0xf8000000 0x8 74 ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
72 1 0 0 0xf0000000 0x8 75 1 0 0 0xf0000000 0x8000000 /* CS1: Alternate flash */
73 2 0 0 0xef800000 0x4 76 2 0 0 0xef800000 0x40000 /* CS2: NAND CE1 */
74 3 0 0 0xef840000 0x4 77 3 0 0 0xef840000 0x40000>; /* CS3: NAND CE2 */
75 78
76 nor-boot@0,0 { 79 nor-boot@0,0 {
77 compatible = "amd,s29g 80 compatible = "amd,s29gl01gp", "cfi-flash";
78 bank-width = <2>; 81 bank-width = <2>;
79 reg = <0 0 0x8000000>; 82 reg = <0 0 0x8000000>; /* 128MB */
80 #address-cells = <1>; 83 #address-cells = <1>;
81 #size-cells = <1>; 84 #size-cells = <1>;
82 partition@0 { 85 partition@0 {
83 label = "Prima 86 label = "Primary user space";
84 reg = <0x00000 87 reg = <0x00000000 0x6f00000>; /* 111 MB */
85 }; 88 };
86 partition@6f00000 { 89 partition@6f00000 {
87 label = "Prima 90 label = "Primary kernel";
88 reg = <0x6f000 91 reg = <0x6f00000 0x1000000>; /* 16 MB */
89 }; 92 };
90 partition@7f00000 { 93 partition@7f00000 {
91 label = "Prima 94 label = "Primary DTB";
92 reg = <0x7f000 95 reg = <0x7f00000 0x40000>; /* 256 KB */
93 }; 96 };
94 partition@7f40000 { 97 partition@7f40000 {
95 label = "Prima 98 label = "Primary U-Boot environment";
96 reg = <0x7f400 99 reg = <0x7f40000 0x40000>; /* 256 KB */
97 }; 100 };
98 partition@7f80000 { 101 partition@7f80000 {
99 label = "Prima 102 label = "Primary U-Boot";
100 reg = <0x7f800 103 reg = <0x7f80000 0x80000>; /* 512 KB */
101 read-only; 104 read-only;
102 }; 105 };
103 }; 106 };
104 107
105 nor-alternate@1,0 { 108 nor-alternate@1,0 {
106 compatible = "amd,s29g 109 compatible = "amd,s29gl01gp", "cfi-flash";
107 bank-width = <2>; 110 bank-width = <2>;
108 //reg = <0xf0000000 0x 111 //reg = <0xf0000000 0x08000000>; /* 128MB */
109 reg = <1 0 0x8000000>; 112 reg = <1 0 0x8000000>; /* 128MB */
110 #address-cells = <1>; 113 #address-cells = <1>;
111 #size-cells = <1>; 114 #size-cells = <1>;
112 partition@0 { 115 partition@0 {
113 label = "Secon 116 label = "Secondary user space";
114 reg = <0x00000 117 reg = <0x00000000 0x6f00000>; /* 111 MB */
115 }; 118 };
116 partition@6f00000 { 119 partition@6f00000 {
117 label = "Secon 120 label = "Secondary kernel";
118 reg = <0x6f000 121 reg = <0x6f00000 0x1000000>; /* 16 MB */
119 }; 122 };
120 partition@7f00000 { 123 partition@7f00000 {
121 label = "Secon 124 label = "Secondary DTB";
122 reg = <0x7f000 125 reg = <0x7f00000 0x40000>; /* 256 KB */
123 }; 126 };
124 partition@7f40000 { 127 partition@7f40000 {
125 label = "Secon 128 label = "Secondary U-Boot environment";
126 reg = <0x7f400 129 reg = <0x7f40000 0x40000>; /* 256 KB */
127 }; 130 };
128 partition@7f80000 { 131 partition@7f80000 {
129 label = "Secon 132 label = "Secondary U-Boot";
130 reg = <0x7f800 133 reg = <0x7f80000 0x80000>; /* 512 KB */
131 read-only; 134 read-only;
132 }; 135 };
133 }; 136 };
134 137
135 nand@2,0 { 138 nand@2,0 {
136 #address-cells = <1>; 139 #address-cells = <1>;
137 #size-cells = <1>; 140 #size-cells = <1>;
138 /* 141 /*
139 * Actual part could b 142 * Actual part could be ST Micro NAND08GW3B2A (1 GB),
140 * Micron MT29F8G08DAA 143 * Micron MT29F8G08DAA (2x 512 MB), or Micron
141 * MT29F16G08FAA (2x 1 144 * MT29F16G08FAA (2x 1 GB), depending on the build
142 * configuration 145 * configuration
143 */ 146 */
144 compatible = "fsl,mpc8 147 compatible = "fsl,mpc8572-fcm-nand",
145 "fsl,elbc 148 "fsl,elbc-fcm-nand";
146 reg = <2 0 0x40000>; 149 reg = <2 0 0x40000>;
147 /* U-Boot should fix t 150 /* U-Boot should fix this up if chip size > 1 GB */
148 partition@0 { 151 partition@0 {
149 label = "NAND 152 label = "NAND Filesystem";
150 reg = <0 0x400 153 reg = <0 0x40000000>;
151 }; 154 };
152 }; 155 };
153 156
154 }; 157 };
155 158
156 soc8572@ef000000 { 159 soc8572@ef000000 {
157 #address-cells = <1>; 160 #address-cells = <1>;
158 #size-cells = <1>; 161 #size-cells = <1>;
159 device_type = "soc"; 162 device_type = "soc";
160 compatible = "fsl,mpc8572-immr 163 compatible = "fsl,mpc8572-immr", "simple-bus";
161 ranges = <0x0 0 0xef000000 0x1 164 ranges = <0x0 0 0xef000000 0x100000>;
162 bus-frequency = <0>; 165 bus-frequency = <0>; // Filled out by uboot.
163 166
164 ecm-law@0 { 167 ecm-law@0 {
165 compatible = "fsl,ecm- 168 compatible = "fsl,ecm-law";
166 reg = <0x0 0x1000>; 169 reg = <0x0 0x1000>;
167 fsl,num-laws = <12>; 170 fsl,num-laws = <12>;
168 }; 171 };
169 172
170 ecm@1000 { 173 ecm@1000 {
171 compatible = "fsl,mpc8 174 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
172 reg = <0x1000 0x1000>; 175 reg = <0x1000 0x1000>;
173 interrupts = <17 2>; 176 interrupts = <17 2>;
174 interrupt-parent = <&m 177 interrupt-parent = <&mpic>;
175 }; 178 };
176 179
177 memory-controller@2000 { 180 memory-controller@2000 {
178 compatible = "fsl,mpc8 181 compatible = "fsl,mpc8572-memory-controller";
179 reg = <0x2000 0x1000>; 182 reg = <0x2000 0x1000>;
180 interrupt-parent = <&m 183 interrupt-parent = <&mpic>;
181 interrupts = <18 2>; 184 interrupts = <18 2>;
182 }; 185 };
183 186
184 memory-controller@6000 { 187 memory-controller@6000 {
185 compatible = "fsl,mpc8 188 compatible = "fsl,mpc8572-memory-controller";
186 reg = <0x6000 0x1000>; 189 reg = <0x6000 0x1000>;
187 interrupt-parent = <&m 190 interrupt-parent = <&mpic>;
188 interrupts = <18 2>; 191 interrupts = <18 2>;
189 }; 192 };
190 193
191 L2: l2-cache-controller@20000 194 L2: l2-cache-controller@20000 {
192 compatible = "fsl,mpc8 195 compatible = "fsl,mpc8572-l2-cache-controller";
193 reg = <0x20000 0x1000> 196 reg = <0x20000 0x1000>;
194 cache-line-size = <32> 197 cache-line-size = <32>; // 32 bytes
195 cache-size = <0x100000 198 cache-size = <0x100000>; // L2, 1M
196 interrupt-parent = <&m 199 interrupt-parent = <&mpic>;
197 interrupts = <16 2>; 200 interrupts = <16 2>;
198 }; 201 };
199 202
200 i2c@3000 { 203 i2c@3000 {
201 #address-cells = <1>; 204 #address-cells = <1>;
202 #size-cells = <0>; 205 #size-cells = <0>;
203 cell-index = <0>; 206 cell-index = <0>;
204 compatible = "fsl-i2c" 207 compatible = "fsl-i2c";
205 reg = <0x3000 0x100>; 208 reg = <0x3000 0x100>;
206 interrupts = <43 2>; 209 interrupts = <43 2>;
207 interrupt-parent = <&m 210 interrupt-parent = <&mpic>;
208 dfsrr; 211 dfsrr;
209 212
210 temp-sensor@48 { 213 temp-sensor@48 {
211 compatible = " 214 compatible = "dallas,ds1631", "dallas,ds1621";
212 reg = <0x48>; 215 reg = <0x48>;
213 }; 216 };
214 217
215 temp-sensor@4c { 218 temp-sensor@4c {
216 compatible = " 219 compatible = "adi,adt7461";
217 reg = <0x4c>; 220 reg = <0x4c>;
218 }; 221 };
219 222
220 cpu-supervisor@51 { 223 cpu-supervisor@51 {
221 compatible = " 224 compatible = "dallas,ds4510";
222 reg = <0x51>; 225 reg = <0x51>;
223 }; 226 };
224 227
225 eeprom@54 { 228 eeprom@54 {
226 compatible = " 229 compatible = "atmel,at24c128b";
227 reg = <0x54>; 230 reg = <0x54>;
228 }; 231 };
229 232
230 rtc@68 { 233 rtc@68 {
231 compatible = " 234 compatible = "st,m41t00",
232 " 235 "dallas,ds1338";
233 reg = <0x68>; 236 reg = <0x68>;
234 }; 237 };
235 238
236 pcie-switch@70 { 239 pcie-switch@70 {
237 compatible = " 240 compatible = "plx,pex8518";
238 reg = <0x70>; 241 reg = <0x70>;
239 }; 242 };
240 243
241 gpio1: gpio@18 { 244 gpio1: gpio@18 {
242 compatible = " 245 compatible = "nxp,pca9557";
243 reg = <0x18>; 246 reg = <0x18>;
244 #gpio-cells = 247 #gpio-cells = <2>;
245 gpio-controlle 248 gpio-controller;
246 polarity = <0x 249 polarity = <0x00>;
247 }; 250 };
248 251
249 gpio2: gpio@1c { 252 gpio2: gpio@1c {
250 compatible = " 253 compatible = "nxp,pca9557";
251 reg = <0x1c>; 254 reg = <0x1c>;
252 #gpio-cells = 255 #gpio-cells = <2>;
253 gpio-controlle 256 gpio-controller;
254 polarity = <0x 257 polarity = <0x00>;
255 }; 258 };
256 259
257 gpio3: gpio@1e { 260 gpio3: gpio@1e {
258 compatible = " 261 compatible = "nxp,pca9557";
259 reg = <0x1e>; 262 reg = <0x1e>;
260 #gpio-cells = 263 #gpio-cells = <2>;
261 gpio-controlle 264 gpio-controller;
262 polarity = <0x 265 polarity = <0x00>;
263 }; 266 };
264 267
265 gpio4: gpio@1f { 268 gpio4: gpio@1f {
266 compatible = " 269 compatible = "nxp,pca9557";
267 reg = <0x1f>; 270 reg = <0x1f>;
268 #gpio-cells = 271 #gpio-cells = <2>;
269 gpio-controlle 272 gpio-controller;
270 polarity = <0x 273 polarity = <0x00>;
271 }; 274 };
272 }; 275 };
273 276
274 i2c@3100 { 277 i2c@3100 {
275 #address-cells = <1>; 278 #address-cells = <1>;
276 #size-cells = <0>; 279 #size-cells = <0>;
277 cell-index = <1>; 280 cell-index = <1>;
278 compatible = "fsl-i2c" 281 compatible = "fsl-i2c";
279 reg = <0x3100 0x100>; 282 reg = <0x3100 0x100>;
280 interrupts = <43 2>; 283 interrupts = <43 2>;
281 interrupt-parent = <&m 284 interrupt-parent = <&mpic>;
282 dfsrr; 285 dfsrr;
283 }; 286 };
284 287
285 dma@c300 { 288 dma@c300 {
286 #address-cells = <1>; 289 #address-cells = <1>;
287 #size-cells = <1>; 290 #size-cells = <1>;
288 compatible = "fsl,mpc8 291 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
289 reg = <0xc300 0x4>; 292 reg = <0xc300 0x4>;
290 ranges = <0x0 0xc100 0 293 ranges = <0x0 0xc100 0x200>;
291 cell-index = <1>; 294 cell-index = <1>;
292 dma-channel@0 { 295 dma-channel@0 {
293 compatible = " 296 compatible = "fsl,mpc8572-dma-channel",
294 297 "fsl,eloplus-dma-channel";
295 reg = <0x0 0x8 298 reg = <0x0 0x80>;
296 cell-index = < 299 cell-index = <0>;
297 interrupt-pare 300 interrupt-parent = <&mpic>;
298 interrupts = < 301 interrupts = <76 2>;
299 }; 302 };
300 dma-channel@80 { 303 dma-channel@80 {
301 compatible = " 304 compatible = "fsl,mpc8572-dma-channel",
302 305 "fsl,eloplus-dma-channel";
303 reg = <0x80 0x 306 reg = <0x80 0x80>;
304 cell-index = < 307 cell-index = <1>;
305 interrupt-pare 308 interrupt-parent = <&mpic>;
306 interrupts = < 309 interrupts = <77 2>;
307 }; 310 };
308 dma-channel@100 { 311 dma-channel@100 {
309 compatible = " 312 compatible = "fsl,mpc8572-dma-channel",
310 313 "fsl,eloplus-dma-channel";
311 reg = <0x100 0 314 reg = <0x100 0x80>;
312 cell-index = < 315 cell-index = <2>;
313 interrupt-pare 316 interrupt-parent = <&mpic>;
314 interrupts = < 317 interrupts = <78 2>;
315 }; 318 };
316 dma-channel@180 { 319 dma-channel@180 {
317 compatible = " 320 compatible = "fsl,mpc8572-dma-channel",
318 321 "fsl,eloplus-dma-channel";
319 reg = <0x180 0 322 reg = <0x180 0x80>;
320 cell-index = < 323 cell-index = <3>;
321 interrupt-pare 324 interrupt-parent = <&mpic>;
322 interrupts = < 325 interrupts = <79 2>;
323 }; 326 };
324 }; 327 };
325 328
326 dma@21300 { 329 dma@21300 {
327 #address-cells = <1>; 330 #address-cells = <1>;
328 #size-cells = <1>; 331 #size-cells = <1>;
329 compatible = "fsl,mpc8 332 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
330 reg = <0x21300 0x4>; 333 reg = <0x21300 0x4>;
331 ranges = <0x0 0x21100 334 ranges = <0x0 0x21100 0x200>;
332 cell-index = <0>; 335 cell-index = <0>;
333 dma-channel@0 { 336 dma-channel@0 {
334 compatible = " 337 compatible = "fsl,mpc8572-dma-channel",
335 338 "fsl,eloplus-dma-channel";
336 reg = <0x0 0x8 339 reg = <0x0 0x80>;
337 cell-index = < 340 cell-index = <0>;
338 interrupt-pare 341 interrupt-parent = <&mpic>;
339 interrupts = < 342 interrupts = <20 2>;
340 }; 343 };
341 dma-channel@80 { 344 dma-channel@80 {
342 compatible = " 345 compatible = "fsl,mpc8572-dma-channel",
343 346 "fsl,eloplus-dma-channel";
344 reg = <0x80 0x 347 reg = <0x80 0x80>;
345 cell-index = < 348 cell-index = <1>;
346 interrupt-pare 349 interrupt-parent = <&mpic>;
347 interrupts = < 350 interrupts = <21 2>;
348 }; 351 };
349 dma-channel@100 { 352 dma-channel@100 {
350 compatible = " 353 compatible = "fsl,mpc8572-dma-channel",
351 354 "fsl,eloplus-dma-channel";
352 reg = <0x100 0 355 reg = <0x100 0x80>;
353 cell-index = < 356 cell-index = <2>;
354 interrupt-pare 357 interrupt-parent = <&mpic>;
355 interrupts = < 358 interrupts = <22 2>;
356 }; 359 };
357 dma-channel@180 { 360 dma-channel@180 {
358 compatible = " 361 compatible = "fsl,mpc8572-dma-channel",
359 362 "fsl,eloplus-dma-channel";
360 reg = <0x180 0 363 reg = <0x180 0x80>;
361 cell-index = < 364 cell-index = <3>;
362 interrupt-pare 365 interrupt-parent = <&mpic>;
363 interrupts = < 366 interrupts = <23 2>;
364 }; 367 };
365 }; 368 };
366 369
367 /* eTSEC 1 */ 370 /* eTSEC 1 */
368 enet0: ethernet@24000 { 371 enet0: ethernet@24000 {
369 #address-cells = <1>; 372 #address-cells = <1>;
370 #size-cells = <1>; 373 #size-cells = <1>;
371 cell-index = <0>; 374 cell-index = <0>;
372 device_type = "network 375 device_type = "network";
373 model = "eTSEC"; 376 model = "eTSEC";
374 compatible = "gianfar" 377 compatible = "gianfar";
375 reg = <0x24000 0x1000> 378 reg = <0x24000 0x1000>;
376 ranges = <0x0 0x24000 379 ranges = <0x0 0x24000 0x1000>;
377 local-mac-address = [ 380 local-mac-address = [ 00 00 00 00 00 00 ];
378 interrupts = <29 2 30 381 interrupts = <29 2 30 2 34 2>;
379 interrupt-parent = <&m 382 interrupt-parent = <&mpic>;
380 tbi-handle = <&tbi0>; 383 tbi-handle = <&tbi0>;
381 phy-handle = <&phy0>; 384 phy-handle = <&phy0>;
382 phy-connection-type = 385 phy-connection-type = "sgmii";
383 386
384 mdio@520 { 387 mdio@520 {
385 #address-cells 388 #address-cells = <1>;
386 #size-cells = 389 #size-cells = <0>;
387 compatible = " 390 compatible = "fsl,gianfar-mdio";
388 reg = <0x520 0 391 reg = <0x520 0x20>;
389 392
390 phy0: ethernet 393 phy0: ethernet-phy@1 {
391 interr 394 interrupt-parent = <&mpic>;
392 interr 395 interrupts = <8 1>;
393 reg = 396 reg = <0x1>;
394 }; 397 };
395 phy1: ethernet 398 phy1: ethernet-phy@2 {
396 interr 399 interrupt-parent = <&mpic>;
397 interr 400 interrupts = <8 1>;
398 reg = 401 reg = <0x2>;
399 }; 402 };
400 tbi0: tbi-phy@ 403 tbi0: tbi-phy@11 {
401 reg = 404 reg = <0x11>;
402 device 405 device_type = "tbi-phy";
403 }; 406 };
404 }; 407 };
405 }; 408 };
406 409
407 /* eTSEC 2 */ 410 /* eTSEC 2 */
408 enet1: ethernet@25000 { 411 enet1: ethernet@25000 {
409 #address-cells = <1>; 412 #address-cells = <1>;
410 #size-cells = <1>; 413 #size-cells = <1>;
411 cell-index = <1>; 414 cell-index = <1>;
412 device_type = "network 415 device_type = "network";
413 model = "eTSEC"; 416 model = "eTSEC";
414 compatible = "gianfar" 417 compatible = "gianfar";
415 reg = <0x25000 0x1000> 418 reg = <0x25000 0x1000>;
416 ranges = <0x0 0x25000 419 ranges = <0x0 0x25000 0x1000>;
417 local-mac-address = [ 420 local-mac-address = [ 00 00 00 00 00 00 ];
418 interrupts = <35 2 36 421 interrupts = <35 2 36 2 40 2>;
419 interrupt-parent = <&m 422 interrupt-parent = <&mpic>;
420 tbi-handle = <&tbi1>; 423 tbi-handle = <&tbi1>;
421 phy-handle = <&phy1>; 424 phy-handle = <&phy1>;
422 phy-connection-type = 425 phy-connection-type = "sgmii";
423 426
424 mdio@520 { 427 mdio@520 {
425 #address-cells 428 #address-cells = <1>;
426 #size-cells = 429 #size-cells = <0>;
427 compatible = " 430 compatible = "fsl,gianfar-tbi";
428 reg = <0x520 0 431 reg = <0x520 0x20>;
429 432
430 tbi1: tbi-phy@ 433 tbi1: tbi-phy@11 {
431 reg = 434 reg = <0x11>;
432 device 435 device_type = "tbi-phy";
433 }; 436 };
434 }; 437 };
435 }; 438 };
436 439
437 /* UART0 */ 440 /* UART0 */
438 serial0: serial@4500 { 441 serial0: serial@4500 {
439 cell-index = <0>; 442 cell-index = <0>;
440 device_type = "serial" 443 device_type = "serial";
441 compatible = "fsl,ns16 444 compatible = "fsl,ns16550", "ns16550";
442 reg = <0x4500 0x100>; 445 reg = <0x4500 0x100>;
443 clock-frequency = <0>; 446 clock-frequency = <0>;
444 interrupts = <42 2>; 447 interrupts = <42 2>;
445 interrupt-parent = <&m 448 interrupt-parent = <&mpic>;
446 }; 449 };
447 450
448 /* UART1 */ 451 /* UART1 */
449 serial1: serial@4600 { 452 serial1: serial@4600 {
450 cell-index = <1>; 453 cell-index = <1>;
451 device_type = "serial" 454 device_type = "serial";
452 compatible = "fsl,ns16 455 compatible = "fsl,ns16550", "ns16550";
453 reg = <0x4600 0x100>; 456 reg = <0x4600 0x100>;
454 clock-frequency = <0>; 457 clock-frequency = <0>;
455 interrupts = <42 2>; 458 interrupts = <42 2>;
456 interrupt-parent = <&m 459 interrupt-parent = <&mpic>;
457 }; 460 };
458 461
459 global-utilities@e0000 { 462 global-utilities@e0000 { //global utilities block
460 compatible = "fsl,mpc8 463 compatible = "fsl,mpc8572-guts";
461 reg = <0xe0000 0x1000> 464 reg = <0xe0000 0x1000>;
462 fsl,has-rstcr; 465 fsl,has-rstcr;
463 }; 466 };
464 467
465 msi@41600 { 468 msi@41600 {
466 compatible = "fsl,mpc8 469 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
467 reg = <0x41600 0x80>; 470 reg = <0x41600 0x80>;
468 msi-available-ranges = 471 msi-available-ranges = <0 0x100>;
469 interrupts = < 472 interrupts = <
470 0xe0 0 473 0xe0 0
471 0xe1 0 474 0xe1 0
472 0xe2 0 475 0xe2 0
473 0xe3 0 476 0xe3 0
474 0xe4 0 477 0xe4 0
475 0xe5 0 478 0xe5 0
476 0xe6 0 479 0xe6 0
477 0xe7 0>; 480 0xe7 0>;
478 interrupt-parent = <&m 481 interrupt-parent = <&mpic>;
479 }; 482 };
480 483
481 crypto@30000 { 484 crypto@30000 {
482 compatible = "fsl,sec3 485 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
483 "fsl,sec2 486 "fsl,sec2.1", "fsl,sec2.0";
484 reg = <0x30000 0x10000 487 reg = <0x30000 0x10000>;
485 interrupts = <45 2 58 488 interrupts = <45 2 58 2>;
486 interrupt-parent = <&m 489 interrupt-parent = <&mpic>;
487 fsl,num-channels = <4> 490 fsl,num-channels = <4>;
488 fsl,channel-fifo-len = 491 fsl,channel-fifo-len = <24>;
489 fsl,exec-units-mask = 492 fsl,exec-units-mask = <0x9fe>;
490 fsl,descriptor-types-m 493 fsl,descriptor-types-mask = <0x3ab0ebf>;
491 }; 494 };
492 495
493 mpic: pic@40000 { 496 mpic: pic@40000 {
494 interrupt-controller; 497 interrupt-controller;
495 #address-cells = <0>; 498 #address-cells = <0>;
496 #interrupt-cells = <2> 499 #interrupt-cells = <2>;
497 reg = <0x40000 0x40000 500 reg = <0x40000 0x40000>;
498 compatible = "chrp,ope 501 compatible = "chrp,open-pic";
499 device_type = "open-pi 502 device_type = "open-pic";
500 }; 503 };
501 504
502 gpio0: gpio@f000 { 505 gpio0: gpio@f000 {
503 compatible = "fsl,mpc8 506 compatible = "fsl,mpc8572-gpio";
504 reg = <0xf000 0x1000>; 507 reg = <0xf000 0x1000>;
505 interrupts = <47 2>; 508 interrupts = <47 2>;
506 interrupt-parent = <&m 509 interrupt-parent = <&mpic>;
507 #gpio-cells = <2>; 510 #gpio-cells = <2>;
508 gpio-controller; 511 gpio-controller;
509 }; 512 };
510 513
511 gpio-leds { 514 gpio-leds {
512 compatible = "gpio-led 515 compatible = "gpio-leds";
513 516
514 heartbeat { 517 heartbeat {
515 label = "Heart 518 label = "Heartbeat";
516 gpios = <&gpio 519 gpios = <&gpio0 4 1>;
517 linux,default- 520 linux,default-trigger = "heartbeat";
518 }; 521 };
519 522
520 yellow { 523 yellow {
521 label = "Yello 524 label = "Yellow";
522 gpios = <&gpio 525 gpios = <&gpio0 5 1>;
523 }; 526 };
524 527
525 red { 528 red {
526 label = "Red"; 529 label = "Red";
527 gpios = <&gpio 530 gpios = <&gpio0 6 1>;
528 }; 531 };
529 532
530 green { 533 green {
531 label = "Green 534 label = "Green";
532 gpios = <&gpio 535 gpios = <&gpio0 7 1>;
533 }; 536 };
534 }; 537 };
535 538
536 /* PME (pattern-matcher) */ 539 /* PME (pattern-matcher) */
537 pme@10000 { 540 pme@10000 {
538 compatible = "fsl,mpc8 541 compatible = "fsl,mpc8572-pme", "pme8572";
539 reg = <0x10000 0x5000> 542 reg = <0x10000 0x5000>;
540 interrupts = <57 2 64 543 interrupts = <57 2 64 2 65 2 66 2 67 2>;
541 interrupt-parent = <&m 544 interrupt-parent = <&mpic>;
542 }; 545 };
543 546
544 tlu@2f000 { 547 tlu@2f000 {
545 compatible = "fsl,mpc8 548 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
546 reg = <0x2f000 0x1000> 549 reg = <0x2f000 0x1000>;
547 interrupts = <61 2>; 550 interrupts = <61 2>;
548 interrupt-parent = <&m 551 interrupt-parent = <&mpic>;
549 }; 552 };
550 553
551 tlu@15000 { 554 tlu@15000 {
552 compatible = "fsl,mpc8 555 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
553 reg = <0x15000 0x1000> 556 reg = <0x15000 0x1000>;
554 interrupts = <75 2>; 557 interrupts = <75 2>;
555 interrupt-parent = <&m 558 interrupt-parent = <&mpic>;
556 }; 559 };
557 }; 560 };
558 561
559 /* 562 /*
560 * PCI Express controller 3 @ ef008000 563 * PCI Express controller 3 @ ef008000 is not used.
561 * This would have been pci0 on other 564 * This would have been pci0 on other mpc85xx platforms.
562 */ 565 */
563 566
564 /* PCI Express controller 2, wired to 567 /* PCI Express controller 2, wired to XMC P15 connector */
565 pci1: pcie@ef009000 { 568 pci1: pcie@ef009000 {
566 compatible = "fsl,mpc8548-pcie 569 compatible = "fsl,mpc8548-pcie";
567 device_type = "pci"; 570 device_type = "pci";
568 #interrupt-cells = <1>; 571 #interrupt-cells = <1>;
569 #size-cells = <2>; 572 #size-cells = <2>;
570 #address-cells = <3>; 573 #address-cells = <3>;
571 reg = <0 0xef009000 0 0x1000>; 574 reg = <0 0xef009000 0 0x1000>;
572 bus-range = <0 255>; 575 bus-range = <0 255>;
573 ranges = <0x2000000 0x0 0xc000 576 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x10000000
574 0x1000000 0x0 0x0000 577 0x1000000 0x0 0x00000000 0 0xe8800000 0x0 0x00010000>;
575 clock-frequency = <33333333>; 578 clock-frequency = <33333333>;
576 interrupt-parent = <&mpic>; 579 interrupt-parent = <&mpic>;
577 interrupts = <25 2>; 580 interrupts = <25 2>;
578 interrupt-map-mask = <0xf800 0 581 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
579 interrupt-map = < 582 interrupt-map = <
580 /* IDSEL 0x0 */ 583 /* IDSEL 0x0 */
581 0x0 0x0 0x0 0x1 &mpic 584 0x0 0x0 0x0 0x1 &mpic 0x4 0x1
582 0x0 0x0 0x0 0x2 &mpic 585 0x0 0x0 0x0 0x2 &mpic 0x5 0x1
583 0x0 0x0 0x0 0x3 &mpic 586 0x0 0x0 0x0 0x3 &mpic 0x6 0x1
584 0x0 0x0 0x0 0x4 &mpic 587 0x0 0x0 0x0 0x4 &mpic 0x7 0x1
585 >; 588 >;
586 pcie@0 { 589 pcie@0 {
587 reg = <0x00000000 0x00 590 reg = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
588 #size-cells = <2>; 591 #size-cells = <2>;
589 #address-cells = <3>; 592 #address-cells = <3>;
590 device_type = "pci"; 593 device_type = "pci";
591 ranges = <0x2000000 0x 594 ranges = <0x2000000 0x0 0xc0000000
592 0x2000000 0x 595 0x2000000 0x0 0xc0000000
593 0x0 0x100000 596 0x0 0x10000000
594 597
595 0x1000000 0x 598 0x1000000 0x0 0x0
596 0x1000000 0x 599 0x1000000 0x0 0x0
597 0x0 0x100000 600 0x0 0x100000>;
598 }; 601 };
599 }; 602 };
600 603
601 /* PCI Express controller 1, wired to 604 /* PCI Express controller 1, wired to PEX8112 for PMC interface */
602 pci2: pcie@ef00a000 { 605 pci2: pcie@ef00a000 {
603 compatible = "fsl,mpc8548-pcie 606 compatible = "fsl,mpc8548-pcie";
604 device_type = "pci"; 607 device_type = "pci";
605 #interrupt-cells = <1>; 608 #interrupt-cells = <1>;
606 #size-cells = <2>; 609 #size-cells = <2>;
607 #address-cells = <3>; 610 #address-cells = <3>;
608 reg = <0 0xef00a000 0 0x1000>; 611 reg = <0 0xef00a000 0 0x1000>;
609 bus-range = <0 255>; 612 bus-range = <0 255>;
610 ranges = <0x2000000 0x0 0x8000 613 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x40000000
611 0x1000000 0x0 0x0000 614 0x1000000 0x0 0x00000000 0 0xe8000000 0x0 0x10000>;
612 clock-frequency = <33333333>; 615 clock-frequency = <33333333>;
613 interrupt-parent = <&mpic>; 616 interrupt-parent = <&mpic>;
614 interrupts = <26 2>; 617 interrupts = <26 2>;
615 interrupt-map-mask = <0xf800 0 618 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
616 interrupt-map = < 619 interrupt-map = <
617 /* IDSEL 0x0 */ 620 /* IDSEL 0x0 */
618 0x0 0x0 0x0 0x1 &mpic 621 0x0 0x0 0x0 0x1 &mpic 0x0 0x1
619 0x0 0x0 0x0 0x2 &mpic 622 0x0 0x0 0x0 0x2 &mpic 0x1 0x1
620 0x0 0x0 0x0 0x3 &mpic 623 0x0 0x0 0x0 0x3 &mpic 0x2 0x1
621 0x0 0x0 0x0 0x4 &mpic 624 0x0 0x0 0x0 0x4 &mpic 0x3 0x1
622 >; 625 >;
623 pcie@0 { 626 pcie@0 {
624 reg = <0x0 0x0 0x0 0x0 627 reg = <0x0 0x0 0x0 0x0 0x0>;
625 #size-cells = <2>; 628 #size-cells = <2>;
626 #address-cells = <3>; 629 #address-cells = <3>;
627 device_type = "pci"; 630 device_type = "pci";
628 ranges = <0x2000000 0x 631 ranges = <0x2000000 0x0 0x80000000
629 0x2000000 0x 632 0x2000000 0x0 0x80000000
630 0x0 0x400000 633 0x0 0x40000000
631 634
632 0x1000000 0x 635 0x1000000 0x0 0x0
633 0x1000000 0x 636 0x1000000 0x0 0x0
634 0x0 0x100000 637 0x0 0x100000>;
635 }; 638 };
636 }; 639 };
637 }; 640 };
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