1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright (C) 2019-20 Sean Anderson <seanga2 3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
4 * Copyright (C) 2020 Western Digital Corporat 4 * Copyright (C) 2020 Western Digital Corporation or its affiliates.
5 */ 5 */
6 #include <dt-bindings/clock/k210-clk.h> 6 #include <dt-bindings/clock/k210-clk.h>
7 #include <dt-bindings/pinctrl/k210-fpioa.h> 7 #include <dt-bindings/pinctrl/k210-fpioa.h>
8 #include <dt-bindings/reset/k210-rst.h> 8 #include <dt-bindings/reset/k210-rst.h>
9 9
10 / { 10 / {
11 /* 11 /*
12 * Although the K210 is a 64-bit CPU, 12 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
13 * wide, and the upper half of all add 13 * wide, and the upper half of all addresses is ignored.
14 */ 14 */
15 #address-cells = <1>; 15 #address-cells = <1>;
16 #size-cells = <1>; 16 #size-cells = <1>;
17 compatible = "canaan,kendryte-k210"; 17 compatible = "canaan,kendryte-k210";
18 18
>> 19 aliases {
>> 20 serial0 = &uarths0;
>> 21 serial1 = &uart1;
>> 22 serial2 = &uart2;
>> 23 serial3 = &uart3;
>> 24 };
>> 25
19 /* 26 /*
20 * The K210 has an sv39 MMU following 27 * The K210 has an sv39 MMU following the privileged specification v1.9.
21 * Since this is a non-ratified draft 28 * Since this is a non-ratified draft specification, the kernel does not
22 * support it and the K210 support ena 29 * support it and the K210 support enabled only for the !MMU case.
23 * Be consistent with this by setting 30 * Be consistent with this by setting the CPUs MMU type to "none".
24 */ 31 */
25 cpus { 32 cpus {
26 #address-cells = <1>; 33 #address-cells = <1>;
27 #size-cells = <0>; 34 #size-cells = <0>;
28 timebase-frequency = <7800000> 35 timebase-frequency = <7800000>;
29 cpu0: cpu@0 { 36 cpu0: cpu@0 {
30 device_type = "cpu"; 37 device_type = "cpu";
31 compatible = "canaan,k 38 compatible = "canaan,k210", "riscv";
32 reg = <0>; 39 reg = <0>;
33 riscv,isa = "rv64imafd 40 riscv,isa = "rv64imafdc";
34 mmu-type = "riscv,none 41 mmu-type = "riscv,none";
35 i-cache-block-size = < 42 i-cache-block-size = <64>;
36 i-cache-size = <0x8000 43 i-cache-size = <0x8000>;
37 d-cache-block-size = < 44 d-cache-block-size = <64>;
38 d-cache-size = <0x8000 45 d-cache-size = <0x8000>;
39 cpu0_intc: interrupt-c 46 cpu0_intc: interrupt-controller {
40 #interrupt-cel 47 #interrupt-cells = <1>;
41 interrupt-cont 48 interrupt-controller;
42 compatible = " 49 compatible = "riscv,cpu-intc";
43 }; 50 };
44 }; 51 };
45 cpu1: cpu@1 { 52 cpu1: cpu@1 {
46 device_type = "cpu"; 53 device_type = "cpu";
47 compatible = "canaan,k 54 compatible = "canaan,k210", "riscv";
48 reg = <1>; 55 reg = <1>;
49 riscv,isa = "rv64imafd 56 riscv,isa = "rv64imafdc";
50 mmu-type = "riscv,none 57 mmu-type = "riscv,none";
51 i-cache-block-size = < 58 i-cache-block-size = <64>;
52 i-cache-size = <0x8000 59 i-cache-size = <0x8000>;
53 d-cache-block-size = < 60 d-cache-block-size = <64>;
54 d-cache-size = <0x8000 61 d-cache-size = <0x8000>;
55 cpu1_intc: interrupt-c 62 cpu1_intc: interrupt-controller {
56 #interrupt-cel 63 #interrupt-cells = <1>;
57 interrupt-cont 64 interrupt-controller;
58 compatible = " 65 compatible = "riscv,cpu-intc";
59 }; 66 };
60 }; 67 };
61 68
62 cpu-map { 69 cpu-map {
63 cluster0 { 70 cluster0 {
64 core0 { 71 core0 {
65 cpu = 72 cpu = <&cpu0>;
66 }; 73 };
67 74
68 core1 { 75 core1 {
69 cpu = 76 cpu = <&cpu1>;
70 }; 77 };
71 }; 78 };
72 }; 79 };
73 }; 80 };
74 81
75 sram: memory@80000000 { 82 sram: memory@80000000 {
76 device_type = "memory"; 83 device_type = "memory";
77 reg = <0x80000000 0x400000>, / 84 reg = <0x80000000 0x400000>, /* sram0 4 MiB */
78 <0x80400000 0x200000>, / 85 <0x80400000 0x200000>, /* sram1 2 MiB */
79 <0x80600000 0x200000>; / 86 <0x80600000 0x200000>; /* aisram 2 MiB */
80 }; 87 };
81 88
82 sram_controller: memory-controller { 89 sram_controller: memory-controller {
83 compatible = "canaan,k210-sram 90 compatible = "canaan,k210-sram";
84 clocks = <&sysclk K210_CLK_SRA 91 clocks = <&sysclk K210_CLK_SRAM0>,
85 <&sysclk K210_CLK_SRA 92 <&sysclk K210_CLK_SRAM1>,
86 <&sysclk K210_CLK_AI> 93 <&sysclk K210_CLK_AI>;
87 clock-names = "sram0", "sram1" 94 clock-names = "sram0", "sram1", "aisram";
88 }; 95 };
89 96
90 clocks { 97 clocks {
91 in0: oscillator { 98 in0: oscillator {
92 compatible = "fixed-cl 99 compatible = "fixed-clock";
93 #clock-cells = <0>; 100 #clock-cells = <0>;
94 clock-frequency = <260 101 clock-frequency = <26000000>;
95 }; 102 };
96 }; 103 };
97 104
98 soc { 105 soc {
99 #address-cells = <1>; 106 #address-cells = <1>;
100 #size-cells = <1>; 107 #size-cells = <1>;
101 compatible = "simple-bus"; 108 compatible = "simple-bus";
102 ranges; 109 ranges;
103 interrupt-parent = <&plic0>; 110 interrupt-parent = <&plic0>;
104 111
105 rom0: nvmem@1000 { 112 rom0: nvmem@1000 {
106 reg = <0x1000 0x1000>; 113 reg = <0x1000 0x1000>;
107 read-only; 114 read-only;
108 }; 115 };
109 116
110 clint0: timer@2000000 { 117 clint0: timer@2000000 {
111 compatible = "canaan,k 118 compatible = "canaan,k210-clint", "sifive,clint0";
112 reg = <0x2000000 0xC00 119 reg = <0x2000000 0xC000>;
113 interrupts-extended = 120 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
114 121 <&cpu1_intc 3>, <&cpu1_intc 7>;
115 }; 122 };
116 123
117 plic0: interrupt-controller@c0 124 plic0: interrupt-controller@c000000 {
118 #interrupt-cells = <1> 125 #interrupt-cells = <1>;
119 #address-cells = <0>; 126 #address-cells = <0>;
120 compatible = "canaan,k 127 compatible = "canaan,k210-plic", "sifive,plic-1.0.0";
121 reg = <0xC000000 0x400 128 reg = <0xC000000 0x4000000>;
122 interrupt-controller; 129 interrupt-controller;
123 interrupts-extended = 130 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
124 131 <&cpu1_intc 11>, <&cpu1_intc 9>;
125 riscv,ndev = <65>; 132 riscv,ndev = <65>;
126 }; 133 };
127 134
128 uarths0: serial@38000000 { 135 uarths0: serial@38000000 {
129 compatible = "canaan,k 136 compatible = "canaan,k210-uarths", "sifive,uart0";
130 reg = <0x38000000 0x10 137 reg = <0x38000000 0x1000>;
131 interrupts = <33>; 138 interrupts = <33>;
132 clocks = <&sysclk K210 139 clocks = <&sysclk K210_CLK_CPU>;
133 status = "disabled"; <<
134 }; 140 };
135 141
136 gpio0: gpio-controller@3800100 142 gpio0: gpio-controller@38001000 {
137 #interrupt-cells = <2> 143 #interrupt-cells = <2>;
138 #gpio-cells = <2>; 144 #gpio-cells = <2>;
139 compatible = "canaan,k 145 compatible = "canaan,k210-gpiohs", "sifive,gpio0";
140 reg = <0x38001000 0x10 146 reg = <0x38001000 0x1000>;
141 interrupt-controller; 147 interrupt-controller;
142 interrupts = <34>, <35 148 interrupts = <34>, <35>, <36>, <37>, <38>, <39>, <40>,
143 <41>, <42 149 <41>, <42>, <43>, <44>, <45>, <46>, <47>,
144 <48>, <49 150 <48>, <49>, <50>, <51>, <52>, <53>, <54>,
145 <55>, <56 151 <55>, <56>, <57>, <58>, <59>, <60>, <61>,
146 <62>, <63 152 <62>, <63>, <64>, <65>;
147 gpio-controller; 153 gpio-controller;
148 ngpios = <32>; 154 ngpios = <32>;
149 status = "disabled"; <<
150 }; 155 };
151 156
152 dmac0: dma-controller@50000000 157 dmac0: dma-controller@50000000 {
153 compatible = "snps,axi 158 compatible = "snps,axi-dma-1.01a";
154 reg = <0x50000000 0x10 159 reg = <0x50000000 0x1000>;
155 interrupts = <27>, <28 160 interrupts = <27>, <28>, <29>, <30>, <31>, <32>;
156 #dma-cells = <1>; 161 #dma-cells = <1>;
157 clocks = <&sysclk K210 162 clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>;
158 clock-names = "core-cl 163 clock-names = "core-clk", "cfgr-clk";
159 resets = <&sysrst K210 164 resets = <&sysrst K210_RST_DMA>;
160 dma-channels = <6>; 165 dma-channels = <6>;
161 snps,dma-masters = <2> 166 snps,dma-masters = <2>;
162 snps,priority = <0 1 2 167 snps,priority = <0 1 2 3 4 5>;
163 snps,data-width = <5>; 168 snps,data-width = <5>;
164 snps,block-size = <0x2 169 snps,block-size = <0x200000 0x200000 0x200000
165 0x2 170 0x200000 0x200000 0x200000>;
166 snps,axi-max-burst-len 171 snps,axi-max-burst-len = <256>;
167 }; 172 };
168 173
169 apb0: bus@50200000 { 174 apb0: bus@50200000 {
170 #address-cells = <1>; 175 #address-cells = <1>;
171 #size-cells = <1>; 176 #size-cells = <1>;
172 compatible = "simple-p 177 compatible = "simple-pm-bus";
173 ranges = <0x50200000 0 178 ranges = <0x50200000 0x50200000 0x200000>;
174 clocks = <&sysclk K210 179 clocks = <&sysclk K210_CLK_APB0>;
175 180
176 gpio1: gpio@50200000 { 181 gpio1: gpio@50200000 {
177 #address-cells 182 #address-cells = <1>;
178 #size-cells = 183 #size-cells = <0>;
179 compatible = " 184 compatible = "snps,dw-apb-gpio";
180 reg = <0x50200 185 reg = <0x50200000 0x80>;
181 clocks = <&sys 186 clocks = <&sysclk K210_CLK_APB0>,
182 <&sys 187 <&sysclk K210_CLK_GPIO>;
183 clock-names = 188 clock-names = "bus", "db";
184 resets = <&sys 189 resets = <&sysrst K210_RST_GPIO>;
185 status = "disa <<
186 190
187 gpio1_0: gpio- 191 gpio1_0: gpio-port@0 {
188 #gpio- 192 #gpio-cells = <2>;
189 #inter 193 #interrupt-cells = <2>;
190 compat 194 compatible = "snps,dw-apb-gpio-port";
191 reg = 195 reg = <0>;
192 interr 196 interrupt-controller;
193 interr 197 interrupts = <23>;
194 gpio-c 198 gpio-controller;
195 ngpios 199 ngpios = <8>;
196 }; 200 };
197 }; 201 };
198 202
199 uart1: serial@50210000 203 uart1: serial@50210000 {
200 compatible = " 204 compatible = "snps,dw-apb-uart";
201 reg = <0x50210 205 reg = <0x50210000 0x100>;
202 interrupts = < 206 interrupts = <11>;
203 clocks = <&sys 207 clocks = <&sysclk K210_CLK_UART1>,
204 <&sys 208 <&sysclk K210_CLK_APB0>;
205 clock-names = 209 clock-names = "baudclk", "apb_pclk";
206 resets = <&sys 210 resets = <&sysrst K210_RST_UART1>;
207 reg-io-width = 211 reg-io-width = <4>;
208 reg-shift = <2 212 reg-shift = <2>;
209 dcd-override; 213 dcd-override;
210 dsr-override; 214 dsr-override;
211 cts-override; 215 cts-override;
212 ri-override; 216 ri-override;
213 status = "disa <<
214 }; 217 };
215 218
216 uart2: serial@50220000 219 uart2: serial@50220000 {
217 compatible = " 220 compatible = "snps,dw-apb-uart";
218 reg = <0x50220 221 reg = <0x50220000 0x100>;
219 interrupts = < 222 interrupts = <12>;
220 clocks = <&sys 223 clocks = <&sysclk K210_CLK_UART2>,
221 <&sys 224 <&sysclk K210_CLK_APB0>;
222 clock-names = 225 clock-names = "baudclk", "apb_pclk";
223 resets = <&sys 226 resets = <&sysrst K210_RST_UART2>;
224 reg-io-width = 227 reg-io-width = <4>;
225 reg-shift = <2 228 reg-shift = <2>;
226 dcd-override; 229 dcd-override;
227 dsr-override; 230 dsr-override;
228 cts-override; 231 cts-override;
229 ri-override; 232 ri-override;
230 status = "disa <<
231 }; 233 };
232 234
233 uart3: serial@50230000 235 uart3: serial@50230000 {
234 compatible = " 236 compatible = "snps,dw-apb-uart";
235 reg = <0x50230 237 reg = <0x50230000 0x100>;
236 interrupts = < 238 interrupts = <13>;
237 clocks = <&sys 239 clocks = <&sysclk K210_CLK_UART3>,
238 <&sys 240 <&sysclk K210_CLK_APB0>;
239 clock-names = 241 clock-names = "baudclk", "apb_pclk";
240 resets = <&sys 242 resets = <&sysrst K210_RST_UART3>;
241 reg-io-width = 243 reg-io-width = <4>;
242 reg-shift = <2 244 reg-shift = <2>;
243 dcd-override; 245 dcd-override;
244 dsr-override; 246 dsr-override;
245 cts-override; 247 cts-override;
246 ri-override; 248 ri-override;
247 status = "disa <<
248 }; 249 };
249 250
250 spi2: spi@50240000 { 251 spi2: spi@50240000 {
251 compatible = " 252 compatible = "canaan,k210-spi";
252 spi-slave; 253 spi-slave;
253 reg = <0x50240 254 reg = <0x50240000 0x100>;
254 #address-cells 255 #address-cells = <0>;
255 #size-cells = 256 #size-cells = <0>;
256 interrupts = < 257 interrupts = <3>;
257 clocks = <&sys 258 clocks = <&sysclk K210_CLK_SPI2>,
258 <&sys 259 <&sysclk K210_CLK_APB0>;
259 clock-names = 260 clock-names = "ssi_clk", "pclk";
260 resets = <&sys 261 resets = <&sysrst K210_RST_SPI2>;
261 status = "disa <<
262 }; 262 };
263 263
264 i2s0: i2s@50250000 { 264 i2s0: i2s@50250000 {
265 compatible = " 265 compatible = "canaan,k210-i2s", "snps,designware-i2s";
266 reg = <0x50250 266 reg = <0x50250000 0x200>;
267 interrupts = < 267 interrupts = <5>;
268 clocks = <&sys 268 clocks = <&sysclk K210_CLK_I2S0>;
269 clock-names = 269 clock-names = "i2sclk";
270 resets = <&sys 270 resets = <&sysrst K210_RST_I2S0>;
271 status = "disa <<
272 }; 271 };
273 272
274 i2s1: i2s@50260000 { 273 i2s1: i2s@50260000 {
275 compatible = " 274 compatible = "canaan,k210-i2s", "snps,designware-i2s";
276 reg = <0x50260 275 reg = <0x50260000 0x200>;
277 interrupts = < 276 interrupts = <6>;
278 clocks = <&sys 277 clocks = <&sysclk K210_CLK_I2S1>;
279 clock-names = 278 clock-names = "i2sclk";
280 resets = <&sys 279 resets = <&sysrst K210_RST_I2S1>;
281 status = "disa <<
282 }; 280 };
283 281
284 i2s2: i2s@50270000 { 282 i2s2: i2s@50270000 {
285 compatible = " 283 compatible = "canaan,k210-i2s", "snps,designware-i2s";
286 reg = <0x50270 284 reg = <0x50270000 0x200>;
287 interrupts = < 285 interrupts = <7>;
288 clocks = <&sys 286 clocks = <&sysclk K210_CLK_I2S2>;
289 clock-names = 287 clock-names = "i2sclk";
290 resets = <&sys 288 resets = <&sysrst K210_RST_I2S2>;
291 status = "disa <<
292 }; 289 };
293 290
294 i2c0: i2c@50280000 { 291 i2c0: i2c@50280000 {
295 compatible = " 292 compatible = "snps,designware-i2c";
296 reg = <0x50280 293 reg = <0x50280000 0x100>;
297 interrupts = < 294 interrupts = <8>;
298 clocks = <&sys 295 clocks = <&sysclk K210_CLK_I2C0>,
299 <&sys 296 <&sysclk K210_CLK_APB0>;
300 clock-names = 297 clock-names = "ref", "pclk";
301 resets = <&sys 298 resets = <&sysrst K210_RST_I2C0>;
302 status = "disa <<
303 }; 299 };
304 300
305 i2c1: i2c@50290000 { 301 i2c1: i2c@50290000 {
306 compatible = " 302 compatible = "snps,designware-i2c";
307 reg = <0x50290 303 reg = <0x50290000 0x100>;
308 interrupts = < 304 interrupts = <9>;
309 clocks = <&sys 305 clocks = <&sysclk K210_CLK_I2C1>,
310 <&sys 306 <&sysclk K210_CLK_APB0>;
311 clock-names = 307 clock-names = "ref", "pclk";
312 resets = <&sys 308 resets = <&sysrst K210_RST_I2C1>;
313 status = "disa <<
314 }; 309 };
315 310
316 i2c2: i2c@502a0000 { 311 i2c2: i2c@502a0000 {
317 compatible = " 312 compatible = "snps,designware-i2c";
318 reg = <0x502A0 313 reg = <0x502A0000 0x100>;
319 interrupts = < 314 interrupts = <10>;
320 clocks = <&sys 315 clocks = <&sysclk K210_CLK_I2C2>,
321 <&sys 316 <&sysclk K210_CLK_APB0>;
322 clock-names = 317 clock-names = "ref", "pclk";
323 resets = <&sys 318 resets = <&sysrst K210_RST_I2C2>;
324 status = "disa <<
325 }; 319 };
326 320
327 fpioa: pinmux@502b0000 321 fpioa: pinmux@502b0000 {
328 compatible = " 322 compatible = "canaan,k210-fpioa";
329 reg = <0x502B0 323 reg = <0x502B0000 0x100>;
330 clocks = <&sys 324 clocks = <&sysclk K210_CLK_FPIOA>,
331 <&sys 325 <&sysclk K210_CLK_APB0>;
332 clock-names = 326 clock-names = "ref", "pclk";
333 resets = <&sys 327 resets = <&sysrst K210_RST_FPIOA>;
334 canaan,k210-sy 328 canaan,k210-sysctl-power = <&sysctl 108>;
335 }; 329 };
336 330
337 timer0: timer@502d0000 331 timer0: timer@502d0000 {
338 compatible = " 332 compatible = "snps,dw-apb-timer";
339 reg = <0x502D0 333 reg = <0x502D0000 0x14>;
340 interrupts = < 334 interrupts = <14>;
341 clocks = <&sys 335 clocks = <&sysclk K210_CLK_TIMER0>,
342 <&sys 336 <&sysclk K210_CLK_APB0>;
343 clock-names = 337 clock-names = "timer", "pclk";
344 resets = <&sys 338 resets = <&sysrst K210_RST_TIMER0>;
345 }; 339 };
346 340
347 timer1: timer@502d0014 341 timer1: timer@502d0014 {
348 compatible = " 342 compatible = "snps,dw-apb-timer";
349 reg = <0x502D0 343 reg = <0x502D0014 0x14>;
350 interrupts = < 344 interrupts = <15>;
351 clocks = <&sys 345 clocks = <&sysclk K210_CLK_TIMER0>,
352 <&sys 346 <&sysclk K210_CLK_APB0>;
353 clock-names = 347 clock-names = "timer", "pclk";
354 resets = <&sys 348 resets = <&sysrst K210_RST_TIMER0>;
355 }; 349 };
356 350
357 timer2: timer@502e0000 351 timer2: timer@502e0000 {
358 compatible = " 352 compatible = "snps,dw-apb-timer";
359 reg = <0x502E0 353 reg = <0x502E0000 0x14>;
360 interrupts = < 354 interrupts = <16>;
361 clocks = <&sys 355 clocks = <&sysclk K210_CLK_TIMER1>,
362 <&sys 356 <&sysclk K210_CLK_APB0>;
363 clock-names = 357 clock-names = "timer", "pclk";
364 resets = <&sys 358 resets = <&sysrst K210_RST_TIMER1>;
365 }; 359 };
366 360
367 timer3: timer@502e0014 361 timer3: timer@502e0014 {
368 compatible = " 362 compatible = "snps,dw-apb-timer";
369 reg = <0x502E0 363 reg = <0x502E0014 0x114>;
370 interrupts = < 364 interrupts = <17>;
371 clocks = <&sys 365 clocks = <&sysclk K210_CLK_TIMER1>,
372 <&sys 366 <&sysclk K210_CLK_APB0>;
373 clock-names = 367 clock-names = "timer", "pclk";
374 resets = <&sys 368 resets = <&sysrst K210_RST_TIMER1>;
375 }; 369 };
376 370
377 timer4: timer@502f0000 371 timer4: timer@502f0000 {
378 compatible = " 372 compatible = "snps,dw-apb-timer";
379 reg = <0x502F0 373 reg = <0x502F0000 0x14>;
380 interrupts = < 374 interrupts = <18>;
381 clocks = <&sys 375 clocks = <&sysclk K210_CLK_TIMER2>,
382 <&sys 376 <&sysclk K210_CLK_APB0>;
383 clock-names = 377 clock-names = "timer", "pclk";
384 resets = <&sys 378 resets = <&sysrst K210_RST_TIMER2>;
385 }; 379 };
386 380
387 timer5: timer@502f0014 381 timer5: timer@502f0014 {
388 compatible = " 382 compatible = "snps,dw-apb-timer";
389 reg = <0x502F0 383 reg = <0x502F0014 0x14>;
390 interrupts = < 384 interrupts = <19>;
391 clocks = <&sys 385 clocks = <&sysclk K210_CLK_TIMER2>,
392 <&sys 386 <&sysclk K210_CLK_APB0>;
393 clock-names = 387 clock-names = "timer", "pclk";
394 resets = <&sys 388 resets = <&sysrst K210_RST_TIMER2>;
395 }; 389 };
396 }; 390 };
397 391
398 apb1: bus@50400000 { 392 apb1: bus@50400000 {
399 #address-cells = <1>; 393 #address-cells = <1>;
400 #size-cells = <1>; 394 #size-cells = <1>;
401 compatible = "simple-p 395 compatible = "simple-pm-bus";
402 ranges = <0x50400000 0 396 ranges = <0x50400000 0x50400000 0x40100>;
403 clocks = <&sysclk K210 397 clocks = <&sysclk K210_CLK_APB1>;
404 398
405 wdt0: watchdog@5040000 399 wdt0: watchdog@50400000 {
406 compatible = " 400 compatible = "snps,dw-wdt";
407 reg = <0x50400 401 reg = <0x50400000 0x100>;
408 interrupts = < 402 interrupts = <21>;
409 clocks = <&sys 403 clocks = <&sysclk K210_CLK_WDT0>,
410 <&sys 404 <&sysclk K210_CLK_APB1>;
411 clock-names = 405 clock-names = "tclk", "pclk";
412 resets = <&sys 406 resets = <&sysrst K210_RST_WDT0>;
413 }; 407 };
414 408
415 wdt1: watchdog@5041000 409 wdt1: watchdog@50410000 {
416 compatible = " 410 compatible = "snps,dw-wdt";
417 reg = <0x50410 411 reg = <0x50410000 0x100>;
418 interrupts = < 412 interrupts = <22>;
419 clocks = <&sys 413 clocks = <&sysclk K210_CLK_WDT1>,
420 <&sys 414 <&sysclk K210_CLK_APB1>;
421 clock-names = 415 clock-names = "tclk", "pclk";
422 resets = <&sys 416 resets = <&sysrst K210_RST_WDT1>;
423 }; 417 };
424 418
425 sysctl: syscon@5044000 419 sysctl: syscon@50440000 {
426 compatible = " 420 compatible = "canaan,k210-sysctl",
427 " 421 "syscon", "simple-mfd";
428 reg = <0x50440 422 reg = <0x50440000 0x100>;
429 clocks = <&sys 423 clocks = <&sysclk K210_CLK_APB1>;
430 clock-names = 424 clock-names = "pclk";
431 425
432 sysclk: clock- 426 sysclk: clock-controller {
433 #clock 427 #clock-cells = <1>;
434 compat 428 compatible = "canaan,k210-clk";
435 clocks 429 clocks = <&in0>;
436 }; 430 };
437 431
438 sysrst: reset- 432 sysrst: reset-controller {
439 compat 433 compatible = "canaan,k210-rst";
440 #reset 434 #reset-cells = <1>;
441 }; 435 };
442 436
443 reboot: syscon 437 reboot: syscon-reboot {
444 compat 438 compatible = "syscon-reboot";
445 regmap 439 regmap = <&sysctl>;
446 offset 440 offset = <48>;
447 mask = 441 mask = <1>;
448 value 442 value = <1>;
449 }; 443 };
450 }; 444 };
451 }; 445 };
452 446
453 apb2: bus@52000000 { 447 apb2: bus@52000000 {
454 #address-cells = <1>; 448 #address-cells = <1>;
455 #size-cells = <1>; 449 #size-cells = <1>;
456 compatible = "simple-p 450 compatible = "simple-pm-bus";
457 ranges = <0x52000000 0 451 ranges = <0x52000000 0x52000000 0x2000200>;
458 clocks = <&sysclk K210 452 clocks = <&sysclk K210_CLK_APB2>;
459 453
460 spi0: spi@52000000 { 454 spi0: spi@52000000 {
461 #address-cells 455 #address-cells = <1>;
462 #size-cells = 456 #size-cells = <0>;
463 compatible = " 457 compatible = "canaan,k210-spi";
464 reg = <0x52000 458 reg = <0x52000000 0x100>;
465 interrupts = < 459 interrupts = <1>;
466 clocks = <&sys 460 clocks = <&sysclk K210_CLK_SPI0>,
467 <&sys 461 <&sysclk K210_CLK_APB2>;
468 clock-names = 462 clock-names = "ssi_clk", "pclk";
469 resets = <&sys 463 resets = <&sysrst K210_RST_SPI0>;
470 reset-names = 464 reset-names = "spi";
471 num-cs = <4>; 465 num-cs = <4>;
472 reg-io-width = 466 reg-io-width = <4>;
473 status = "disa <<
474 }; 467 };
475 468
476 spi1: spi@53000000 { 469 spi1: spi@53000000 {
477 #address-cells 470 #address-cells = <1>;
478 #size-cells = 471 #size-cells = <0>;
479 compatible = " 472 compatible = "canaan,k210-spi";
480 reg = <0x53000 473 reg = <0x53000000 0x100>;
481 interrupts = < 474 interrupts = <2>;
482 clocks = <&sys 475 clocks = <&sysclk K210_CLK_SPI1>,
483 <&sys 476 <&sysclk K210_CLK_APB2>;
484 clock-names = 477 clock-names = "ssi_clk", "pclk";
485 resets = <&sys 478 resets = <&sysrst K210_RST_SPI1>;
486 reset-names = 479 reset-names = "spi";
487 num-cs = <4>; 480 num-cs = <4>;
488 reg-io-width = 481 reg-io-width = <4>;
489 status = "disa <<
490 }; 482 };
491 483
492 spi3: spi@54000000 { 484 spi3: spi@54000000 {
493 #address-cells 485 #address-cells = <1>;
494 #size-cells = 486 #size-cells = <0>;
495 compatible = " 487 compatible = "snps,dwc-ssi-1.01a";
496 reg = <0x54000 488 reg = <0x54000000 0x200>;
497 interrupts = < 489 interrupts = <4>;
498 clocks = <&sys 490 clocks = <&sysclk K210_CLK_SPI3>,
499 <&sys 491 <&sysclk K210_CLK_APB2>;
500 clock-names = 492 clock-names = "ssi_clk", "pclk";
501 resets = <&sys 493 resets = <&sysrst K210_RST_SPI3>;
502 reset-names = 494 reset-names = "spi";
503 495
504 num-cs = <4>; 496 num-cs = <4>;
505 reg-io-width = 497 reg-io-width = <4>;
506 status = "disa <<
507 }; 498 };
508 }; 499 };
509 }; 500 };
510 }; 501 };
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