1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technolog 2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
3 3
4 /dts-v1/; 4 /dts-v1/;
5 5
6 #include "mpfs.dtsi" 6 #include "mpfs.dtsi"
7 #include "mpfs-icicle-kit-fabric.dtsi" 7 #include "mpfs-icicle-kit-fabric.dtsi"
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/leds/common.h> 9 #include <dt-bindings/leds/common.h>
10 10
>> 11 /* Clock frequency (in Hz) of the rtcclk */
>> 12 #define RTCCLK_FREQ 1000000
>> 13
11 / { 14 / {
12 model = "Microchip PolarFire-SoC Icicl 15 model = "Microchip PolarFire-SoC Icicle Kit";
13 compatible = "microchip,mpfs-icicle-re 16 compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
14 "microchip,mpfs"; 17 "microchip,mpfs";
15 18
16 aliases { 19 aliases {
17 ethernet0 = &mac1; 20 ethernet0 = &mac1;
18 serial0 = &mmuart0; 21 serial0 = &mmuart0;
19 serial1 = &mmuart1; 22 serial1 = &mmuart1;
20 serial2 = &mmuart2; 23 serial2 = &mmuart2;
21 serial3 = &mmuart3; 24 serial3 = &mmuart3;
22 serial4 = &mmuart4; 25 serial4 = &mmuart4;
23 }; 26 };
24 27
25 chosen { 28 chosen {
26 stdout-path = "serial1:115200n 29 stdout-path = "serial1:115200n8";
27 }; 30 };
28 31
>> 32 cpus {
>> 33 timebase-frequency = <RTCCLK_FREQ>;
>> 34 };
>> 35
29 leds { 36 leds {
30 compatible = "gpio-leds"; 37 compatible = "gpio-leds";
31 38
32 led-1 { 39 led-1 {
33 gpios = <&gpio2 16 GPI 40 gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
34 color = <LED_COLOR_ID_ 41 color = <LED_COLOR_ID_RED>;
35 label = "led1"; 42 label = "led1";
36 }; 43 };
37 44
38 led-2 { 45 led-2 {
39 gpios = <&gpio2 17 GPI 46 gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
40 color = <LED_COLOR_ID_ 47 color = <LED_COLOR_ID_RED>;
41 label = "led2"; 48 label = "led2";
42 }; 49 };
43 50
44 led-3 { 51 led-3 {
45 gpios = <&gpio2 18 GPI 52 gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
46 color = <LED_COLOR_ID_ 53 color = <LED_COLOR_ID_AMBER>;
47 label = "led3"; 54 label = "led3";
48 }; 55 };
49 56
50 led-4 { 57 led-4 {
51 gpios = <&gpio2 19 GPI 58 gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
52 color = <LED_COLOR_ID_ 59 color = <LED_COLOR_ID_AMBER>;
53 label = "led4"; 60 label = "led4";
54 }; 61 };
55 }; 62 };
56 63
57 ddrc_cache_lo: memory@80000000 { 64 ddrc_cache_lo: memory@80000000 {
58 device_type = "memory"; 65 device_type = "memory";
59 reg = <0x0 0x80000000 0x0 0x40 66 reg = <0x0 0x80000000 0x0 0x40000000>;
60 status = "okay"; 67 status = "okay";
61 }; 68 };
62 69
63 ddrc_cache_hi: memory@1040000000 { 70 ddrc_cache_hi: memory@1040000000 {
64 device_type = "memory"; 71 device_type = "memory";
65 reg = <0x10 0x40000000 0x0 0x4 72 reg = <0x10 0x40000000 0x0 0x40000000>;
66 status = "okay"; 73 status = "okay";
67 }; 74 };
68 75
69 reserved-memory { 76 reserved-memory {
70 #address-cells = <2>; 77 #address-cells = <2>;
71 #size-cells = <2>; 78 #size-cells = <2>;
72 ranges; 79 ranges;
73 80
74 hss_payload: region@BFC00000 { 81 hss_payload: region@BFC00000 {
75 reg = <0x0 0xBFC00000 82 reg = <0x0 0xBFC00000 0x0 0x400000>;
76 no-map; 83 no-map;
77 }; 84 };
78 }; 85 };
79 }; 86 };
80 87
81 &core_pwm0 { 88 &core_pwm0 {
82 status = "okay"; 89 status = "okay";
83 }; 90 };
84 91
85 &gpio2 { 92 &gpio2 {
86 interrupts = <53>, <53>, <53>, <53>, 93 interrupts = <53>, <53>, <53>, <53>,
87 <53>, <53>, <53>, <53>, 94 <53>, <53>, <53>, <53>,
88 <53>, <53>, <53>, <53>, 95 <53>, <53>, <53>, <53>,
89 <53>, <53>, <53>, <53>, 96 <53>, <53>, <53>, <53>,
90 <53>, <53>, <53>, <53>, 97 <53>, <53>, <53>, <53>,
91 <53>, <53>, <53>, <53>, 98 <53>, <53>, <53>, <53>,
92 <53>, <53>, <53>, <53>, 99 <53>, <53>, <53>, <53>,
93 <53>, <53>, <53>, <53>; 100 <53>, <53>, <53>, <53>;
94 status = "okay"; 101 status = "okay";
95 }; 102 };
96 103
97 &i2c0 { 104 &i2c0 {
98 status = "okay"; 105 status = "okay";
99 }; 106 };
100 107
101 &i2c1 { 108 &i2c1 {
102 status = "okay"; 109 status = "okay";
103 <<
104 power-monitor@10 { <<
105 compatible = "microchip,pac193 <<
106 reg = <0x10>; <<
107 <<
108 #address-cells = <1>; <<
109 #size-cells = <0>; <<
110 <<
111 channel@1 { <<
112 reg = <0x1>; <<
113 shunt-resistor-micro-o <<
114 label = "VDDREG"; <<
115 }; <<
116 <<
117 channel@2 { <<
118 reg = <0x2>; <<
119 shunt-resistor-micro-o <<
120 label = "VDDA25"; <<
121 }; <<
122 <<
123 channel@3 { <<
124 reg = <0x3>; <<
125 shunt-resistor-micro-o <<
126 label = "VDD25"; <<
127 }; <<
128 <<
129 channel@4 { <<
130 reg = <0x4>; <<
131 shunt-resistor-micro-o <<
132 label = "VDDA_REG"; <<
133 }; <<
134 }; <<
135 }; 110 };
136 111
137 &i2c2 { 112 &i2c2 {
138 status = "okay"; 113 status = "okay";
139 }; 114 };
140 115
141 &mac0 { 116 &mac0 {
142 phy-mode = "sgmii"; 117 phy-mode = "sgmii";
143 phy-handle = <&phy0>; 118 phy-handle = <&phy0>;
144 status = "okay"; 119 status = "okay";
145 }; 120 };
146 121
147 &mac1 { 122 &mac1 {
148 phy-mode = "sgmii"; 123 phy-mode = "sgmii";
149 phy-handle = <&phy1>; 124 phy-handle = <&phy1>;
150 status = "okay"; 125 status = "okay";
151 126
152 phy1: ethernet-phy@9 { 127 phy1: ethernet-phy@9 {
153 reg = <9>; 128 reg = <9>;
154 }; 129 };
155 130
156 phy0: ethernet-phy@8 { 131 phy0: ethernet-phy@8 {
157 reg = <8>; 132 reg = <8>;
158 }; 133 };
159 }; 134 };
160 135
161 &mbox { 136 &mbox {
162 status = "okay"; 137 status = "okay";
163 }; 138 };
164 139
165 &mmc { 140 &mmc {
166 bus-width = <4>; 141 bus-width = <4>;
167 disable-wp; 142 disable-wp;
168 cap-sd-highspeed; 143 cap-sd-highspeed;
169 cap-mmc-highspeed; 144 cap-mmc-highspeed;
170 mmc-ddr-1_8v; 145 mmc-ddr-1_8v;
171 mmc-hs200-1_8v; 146 mmc-hs200-1_8v;
172 sd-uhs-sdr12; 147 sd-uhs-sdr12;
173 sd-uhs-sdr25; 148 sd-uhs-sdr25;
174 sd-uhs-sdr50; 149 sd-uhs-sdr50;
175 sd-uhs-sdr104; 150 sd-uhs-sdr104;
176 status = "okay"; 151 status = "okay";
177 }; 152 };
178 153
179 &mmuart1 { 154 &mmuart1 {
180 status = "okay"; 155 status = "okay";
181 }; 156 };
182 157
183 &mmuart2 { 158 &mmuart2 {
184 status = "okay"; 159 status = "okay";
185 }; 160 };
186 161
187 &mmuart3 { 162 &mmuart3 {
188 status = "okay"; 163 status = "okay";
189 }; 164 };
190 165
191 &mmuart4 { 166 &mmuart4 {
192 status = "okay"; 167 status = "okay";
193 }; 168 };
194 169
195 &pcie { 170 &pcie {
196 status = "okay"; 171 status = "okay";
197 }; 172 };
198 173
199 &qspi { 174 &qspi {
200 status = "okay"; 175 status = "okay";
201 }; 176 };
202 177
203 &refclk { 178 &refclk {
204 clock-frequency = <125000000>; 179 clock-frequency = <125000000>;
205 }; 180 };
206 181
207 &refclk_ccc { 182 &refclk_ccc {
208 clock-frequency = <50000000>; 183 clock-frequency = <50000000>;
209 }; 184 };
210 185
211 &rtc { 186 &rtc {
212 status = "okay"; 187 status = "okay";
213 }; 188 };
214 189
215 &spi0 { 190 &spi0 {
216 status = "okay"; 191 status = "okay";
217 }; 192 };
218 193
219 &spi1 { 194 &spi1 {
220 status = "okay"; 195 status = "okay";
221 }; 196 };
222 197
223 &syscontroller { 198 &syscontroller {
224 status = "okay"; 199 status = "okay";
225 }; <<
226 <<
227 &syscontroller_qspi { <<
228 /* <<
229 * The flash *is* there, but Icicle ki <<
230 * silicon (write?) access to this fla <<
231 * controller itself can actually acce <<
232 * an image there. Instantiating a cor <<
233 * it to the flash instead should work <<
234 * silicon does not have this issue. <<
235 */ <<
236 status = "disabled"; <<
237 <<
238 sys_ctrl_flash: flash@0 { // MT25QL01G <<
239 compatible = "jedec,spi-nor"; <<
240 #address-cells = <1>; <<
241 #size-cells = <1>; <<
242 spi-max-frequency = <20000000> <<
243 spi-rx-bus-width = <1>; <<
244 reg = <0>; <<
245 }; <<
246 }; 200 };
247 201
248 &usb { 202 &usb {
249 status = "okay"; 203 status = "okay";
250 dr_mode = "host"; 204 dr_mode = "host";
251 }; 205 };
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