1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Original all-in-one devicetree: 3 * Original all-in-one devicetree:
4 * Copyright (C) 2021-2022 - Wolfgang Grandegg< 4 * Copyright (C) 2021-2022 - Wolfgang Grandegger <wg@aries-embedded.de>
5 * Rewritten to use includes: 5 * Rewritten to use includes:
6 * Copyright (C) 2022 - Conor Dooley <conor.doo 6 * Copyright (C) 2022 - Conor Dooley <conor.dooley@microchip.com>
7 */ 7 */
8 /dts-v1/; 8 /dts-v1/;
9 9
10 #include "mpfs.dtsi" 10 #include "mpfs.dtsi"
11 #include "mpfs-m100pfs-fabric.dtsi" 11 #include "mpfs-m100pfs-fabric.dtsi"
12 12
>> 13 /* Clock frequency (in Hz) of the rtcclk */
>> 14 #define MTIMER_FREQ 1000000
>> 15
13 / { 16 / {
14 model = "Aries Embedded M100PFEVPS"; 17 model = "Aries Embedded M100PFEVPS";
15 compatible = "aries,m100pfsevp", "micr 18 compatible = "aries,m100pfsevp", "microchip,mpfs";
16 19
17 aliases { 20 aliases {
18 ethernet0 = &mac0; 21 ethernet0 = &mac0;
19 ethernet1 = &mac1; 22 ethernet1 = &mac1;
20 serial0 = &mmuart0; 23 serial0 = &mmuart0;
21 serial1 = &mmuart1; 24 serial1 = &mmuart1;
22 serial2 = &mmuart2; 25 serial2 = &mmuart2;
23 serial3 = &mmuart3; 26 serial3 = &mmuart3;
24 serial4 = &mmuart4; 27 serial4 = &mmuart4;
25 gpio0 = &gpio0; 28 gpio0 = &gpio0;
26 gpio1 = &gpio2; 29 gpio1 = &gpio2;
27 }; 30 };
28 31
29 chosen { 32 chosen {
30 stdout-path = "serial1:115200n 33 stdout-path = "serial1:115200n8";
>> 34 };
>> 35
>> 36 cpus {
>> 37 timebase-frequency = <MTIMER_FREQ>;
31 }; 38 };
32 39
33 ddrc_cache_lo: memory@80000000 { 40 ddrc_cache_lo: memory@80000000 {
34 device_type = "memory"; 41 device_type = "memory";
35 reg = <0x0 0x80000000 0x0 0x40 42 reg = <0x0 0x80000000 0x0 0x40000000>;
36 }; 43 };
37 ddrc_cache_hi: memory@1040000000 { 44 ddrc_cache_hi: memory@1040000000 {
38 device_type = "memory"; 45 device_type = "memory";
39 reg = <0x10 0x40000000 0x0 0x4 46 reg = <0x10 0x40000000 0x0 0x40000000>;
40 }; 47 };
41 }; 48 };
42 49
43 &can0 { 50 &can0 {
44 status = "okay"; 51 status = "okay";
45 }; 52 };
46 53
47 &i2c0 { 54 &i2c0 {
48 status = "okay"; 55 status = "okay";
49 }; 56 };
50 57
51 &i2c1 { 58 &i2c1 {
52 status = "okay"; 59 status = "okay";
53 }; 60 };
54 61
55 &gpio0 { 62 &gpio0 {
56 interrupts = <13>, <14>, <15>, <16>, 63 interrupts = <13>, <14>, <15>, <16>,
57 <17>, <18>, <19>, <20>, 64 <17>, <18>, <19>, <20>,
58 <21>, <22>, <23>, <24>, 65 <21>, <22>, <23>, <24>,
59 <25>, <26>; 66 <25>, <26>;
60 ngpios = <14>; 67 ngpios = <14>;
61 status = "okay"; 68 status = "okay";
62 69
63 pmic-irq-hog { 70 pmic-irq-hog {
64 gpio-hog; 71 gpio-hog;
65 gpios = <13 0>; 72 gpios = <13 0>;
66 input; 73 input;
67 }; 74 };
68 75
69 /* Set to low for eMMC, high for SD-ca 76 /* Set to low for eMMC, high for SD-card */
70 mmc-sel-hog { 77 mmc-sel-hog {
71 gpio-hog; 78 gpio-hog;
72 gpios = <12 0>; 79 gpios = <12 0>;
73 output-high; 80 output-high;
74 }; 81 };
75 }; 82 };
76 83
77 &gpio2 { 84 &gpio2 {
78 interrupts = <13>, <14>, <15>, <16>, 85 interrupts = <13>, <14>, <15>, <16>,
79 <17>, <18>, <19>, <20>, 86 <17>, <18>, <19>, <20>,
80 <21>, <22>, <23>, <24>, 87 <21>, <22>, <23>, <24>,
81 <25>, <26>, <27>, <28>, 88 <25>, <26>, <27>, <28>,
82 <29>, <30>, <31>, <32>, 89 <29>, <30>, <31>, <32>,
83 <33>, <34>, <35>, <36>, 90 <33>, <34>, <35>, <36>,
84 <37>, <38>, <39>, <40>, 91 <37>, <38>, <39>, <40>,
85 <41>, <42>, <43>, <44>; 92 <41>, <42>, <43>, <44>;
86 status = "okay"; 93 status = "okay";
87 }; 94 };
88 95
89 &mac0 { 96 &mac0 {
90 status = "okay"; 97 status = "okay";
91 phy-mode = "gmii"; 98 phy-mode = "gmii";
92 phy-handle = <&phy0>; 99 phy-handle = <&phy0>;
93 phy0: ethernet-phy@0 { 100 phy0: ethernet-phy@0 {
94 reg = <0>; 101 reg = <0>;
95 }; 102 };
96 }; 103 };
97 104
98 &mac1 { 105 &mac1 {
99 status = "okay"; 106 status = "okay";
100 phy-mode = "gmii"; 107 phy-mode = "gmii";
101 phy-handle = <&phy1>; 108 phy-handle = <&phy1>;
102 phy1: ethernet-phy@0 { 109 phy1: ethernet-phy@0 {
103 reg = <0>; 110 reg = <0>;
104 }; 111 };
105 }; 112 };
106 113
107 &mbox { 114 &mbox {
108 status = "okay"; 115 status = "okay";
109 }; 116 };
110 117
111 &mmc { 118 &mmc {
112 max-frequency = <50000000>; 119 max-frequency = <50000000>;
113 bus-width = <4>; 120 bus-width = <4>;
114 cap-mmc-highspeed; 121 cap-mmc-highspeed;
115 cap-sd-highspeed; 122 cap-sd-highspeed;
116 no-1-8-v; 123 no-1-8-v;
117 sd-uhs-sdr12; 124 sd-uhs-sdr12;
118 sd-uhs-sdr25; 125 sd-uhs-sdr25;
119 sd-uhs-sdr50; 126 sd-uhs-sdr50;
120 sd-uhs-sdr104; 127 sd-uhs-sdr104;
121 disable-wp; 128 disable-wp;
122 status = "okay"; 129 status = "okay";
123 }; 130 };
124 131
125 &mmuart1 { 132 &mmuart1 {
126 status = "okay"; 133 status = "okay";
127 }; 134 };
128 135
129 &mmuart2 { 136 &mmuart2 {
130 status = "okay"; 137 status = "okay";
131 }; 138 };
132 139
133 &mmuart3 { 140 &mmuart3 {
134 status = "okay"; 141 status = "okay";
135 }; 142 };
136 143
137 &mmuart4 { 144 &mmuart4 {
138 status = "okay"; 145 status = "okay";
139 }; 146 };
140 147
141 &pcie { 148 &pcie {
142 status = "okay"; 149 status = "okay";
143 }; 150 };
144 151
145 &qspi { 152 &qspi {
146 status = "okay"; 153 status = "okay";
147 }; 154 };
148 155
149 &refclk { 156 &refclk {
150 clock-frequency = <125000000>; 157 clock-frequency = <125000000>;
151 }; 158 };
152 159
153 &rtc { 160 &rtc {
154 status = "okay"; 161 status = "okay";
155 }; 162 };
156 163
157 &spi0 { 164 &spi0 {
158 status = "okay"; 165 status = "okay";
159 }; 166 };
160 167
161 &spi1 { 168 &spi1 {
162 status = "okay"; 169 status = "okay";
163 }; 170 };
164 171
165 &syscontroller { 172 &syscontroller {
166 status = "okay"; 173 status = "okay";
167 }; 174 };
168 175
169 &usb { 176 &usb {
170 status = "okay"; 177 status = "okay";
171 dr_mode = "host"; 178 dr_mode = "host";
172 }; 179 };
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