1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2022 Microchip Technolog 2 /* Copyright (c) 2020-2022 Microchip Technology Inc */
3 3
4 /dts-v1/; 4 /dts-v1/;
5 5
6 #include "mpfs.dtsi" 6 #include "mpfs.dtsi"
7 #include "mpfs-polarberry-fabric.dtsi" 7 #include "mpfs-polarberry-fabric.dtsi"
8 8
>> 9 /* Clock frequency (in Hz) of the rtcclk */
>> 10 #define MTIMER_FREQ 1000000
>> 11
9 / { 12 / {
10 model = "Sundance PolarBerry"; 13 model = "Sundance PolarBerry";
11 compatible = "sundance,polarberry", "m 14 compatible = "sundance,polarberry", "microchip,mpfs";
12 15
13 aliases { 16 aliases {
14 ethernet0 = &mac1; 17 ethernet0 = &mac1;
15 serial0 = &mmuart0; 18 serial0 = &mmuart0;
16 }; 19 };
17 20
18 chosen { 21 chosen {
19 stdout-path = "serial0:115200n 22 stdout-path = "serial0:115200n8";
>> 23 };
>> 24
>> 25 cpus {
>> 26 timebase-frequency = <MTIMER_FREQ>;
20 }; 27 };
21 28
22 ddrc_cache_lo: memory@80000000 { 29 ddrc_cache_lo: memory@80000000 {
23 device_type = "memory"; 30 device_type = "memory";
24 reg = <0x0 0x80000000 0x0 0x2e 31 reg = <0x0 0x80000000 0x0 0x2e000000>;
25 }; 32 };
26 33
27 ddrc_cache_hi: memory@1000000000 { 34 ddrc_cache_hi: memory@1000000000 {
28 device_type = "memory"; 35 device_type = "memory";
29 reg = <0x10 0x00000000 0x0 0xC 36 reg = <0x10 0x00000000 0x0 0xC0000000>;
30 }; 37 };
31 }; 38 };
32 39
33 /* 40 /*
34 * phy0 is connected to mac0, but the port its 41 * phy0 is connected to mac0, but the port itself is on the (optional) carrier
35 * board. 42 * board.
36 */ 43 */
37 &mac0 { 44 &mac0 {
38 phy-mode = "sgmii"; 45 phy-mode = "sgmii";
39 phy-handle = <&phy0>; 46 phy-handle = <&phy0>;
40 status = "disabled"; 47 status = "disabled";
41 }; 48 };
42 49
43 &mac1 { 50 &mac1 {
44 phy-mode = "sgmii"; 51 phy-mode = "sgmii";
45 phy-handle = <&phy1>; 52 phy-handle = <&phy1>;
46 status = "okay"; 53 status = "okay";
47 54
48 phy1: ethernet-phy@5 { 55 phy1: ethernet-phy@5 {
49 reg = <5>; 56 reg = <5>;
50 }; 57 };
51 58
52 phy0: ethernet-phy@4 { 59 phy0: ethernet-phy@4 {
53 reg = <4>; 60 reg = <4>;
54 }; 61 };
55 }; 62 };
56 63
57 &mbox { 64 &mbox {
58 status = "okay"; 65 status = "okay";
59 }; 66 };
60 67
61 &mmc { 68 &mmc {
62 bus-width = <4>; 69 bus-width = <4>;
63 disable-wp; 70 disable-wp;
64 cap-sd-highspeed; 71 cap-sd-highspeed;
65 cap-mmc-highspeed; 72 cap-mmc-highspeed;
66 mmc-ddr-1_8v; 73 mmc-ddr-1_8v;
67 mmc-hs200-1_8v; 74 mmc-hs200-1_8v;
68 sd-uhs-sdr12; 75 sd-uhs-sdr12;
69 sd-uhs-sdr25; 76 sd-uhs-sdr25;
70 sd-uhs-sdr50; 77 sd-uhs-sdr50;
71 sd-uhs-sdr104; 78 sd-uhs-sdr104;
72 status = "okay"; 79 status = "okay";
73 }; 80 };
74 81
75 &mmuart0 { 82 &mmuart0 {
76 status = "okay"; 83 status = "okay";
77 }; 84 };
78 85
79 &refclk { 86 &refclk {
80 clock-frequency = <125000000>; 87 clock-frequency = <125000000>;
81 }; 88 };
82 89
83 &rtc { 90 &rtc {
84 status = "okay"; 91 status = "okay";
85 }; 92 };
86 93
87 &syscontroller { 94 &syscontroller {
88 status = "okay"; 95 status = "okay";
89 }; 96 };
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