1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2022 Microchip Technology Inc 2 /* Copyright (c) 2022 Microchip Technology Inc */
3 3
4 /dts-v1/; 4 /dts-v1/;
5 5
6 #include "mpfs.dtsi" 6 #include "mpfs.dtsi"
7 #include "mpfs-sev-kit-fabric.dtsi" 7 #include "mpfs-sev-kit-fabric.dtsi"
8 8
>> 9 /* Clock frequency (in Hz) of the rtcclk */
>> 10 #define MTIMER_FREQ 1000000
>> 11
9 / { 12 / {
10 #address-cells = <2>; 13 #address-cells = <2>;
11 #size-cells = <2>; 14 #size-cells = <2>;
12 model = "Microchip PolarFire-SoC SEV K 15 model = "Microchip PolarFire-SoC SEV Kit";
13 compatible = "microchip,mpfs-sev-kit", 16 compatible = "microchip,mpfs-sev-kit", "microchip,mpfs";
14 17
15 aliases { 18 aliases {
16 ethernet0 = &mac1; 19 ethernet0 = &mac1;
17 serial0 = &mmuart0; 20 serial0 = &mmuart0;
18 serial1 = &mmuart1; 21 serial1 = &mmuart1;
19 serial2 = &mmuart2; 22 serial2 = &mmuart2;
20 serial3 = &mmuart3; 23 serial3 = &mmuart3;
21 serial4 = &mmuart4; 24 serial4 = &mmuart4;
22 }; 25 };
23 26
24 chosen { 27 chosen {
25 stdout-path = "serial1:115200n 28 stdout-path = "serial1:115200n8";
>> 29 };
>> 30
>> 31 cpus {
>> 32 timebase-frequency = <MTIMER_FREQ>;
26 }; 33 };
27 34
28 reserved-memory { 35 reserved-memory {
29 #address-cells = <2>; 36 #address-cells = <2>;
30 #size-cells = <2>; 37 #size-cells = <2>;
31 ranges; 38 ranges;
32 39
33 fabricbuf0ddrc: buffer@8000000 40 fabricbuf0ddrc: buffer@80000000 {
34 compatible = "shared-d 41 compatible = "shared-dma-pool";
35 reg = <0x0 0x80000000 42 reg = <0x0 0x80000000 0x0 0x2000000>;
36 }; 43 };
37 44
38 fabricbuf1ddrnc: buffer@c40000 45 fabricbuf1ddrnc: buffer@c4000000 {
39 compatible = "shared-d 46 compatible = "shared-dma-pool";
40 reg = <0x0 0xc4000000 47 reg = <0x0 0xc4000000 0x0 0x4000000>;
41 }; 48 };
42 49
43 fabricbuf2ddrncwcb: buffer@d40 50 fabricbuf2ddrncwcb: buffer@d4000000 {
44 compatible = "shared-d 51 compatible = "shared-dma-pool";
45 reg = <0x0 0xd4000000 52 reg = <0x0 0xd4000000 0x0 0x4000000>;
46 }; 53 };
47 }; 54 };
48 55
49 ddrc_cache: memory@1000000000 { 56 ddrc_cache: memory@1000000000 {
50 device_type = "memory"; 57 device_type = "memory";
51 reg = <0x10 0x0 0x0 0x76000000 58 reg = <0x10 0x0 0x0 0x76000000>;
52 }; 59 };
53 }; 60 };
54 61
55 &i2c0 { 62 &i2c0 {
56 status = "okay"; 63 status = "okay";
57 }; 64 };
58 65
59 &gpio2 { 66 &gpio2 {
60 interrupts = <53>, <53>, <53>, <53>, 67 interrupts = <53>, <53>, <53>, <53>,
61 <53>, <53>, <53>, <53>, 68 <53>, <53>, <53>, <53>,
62 <53>, <53>, <53>, <53>, 69 <53>, <53>, <53>, <53>,
63 <53>, <53>, <53>, <53>, 70 <53>, <53>, <53>, <53>,
64 <53>, <53>, <53>, <53>, 71 <53>, <53>, <53>, <53>,
65 <53>, <53>, <53>, <53>, 72 <53>, <53>, <53>, <53>,
66 <53>, <53>, <53>, <53>, 73 <53>, <53>, <53>, <53>,
67 <53>, <53>, <53>, <53>; 74 <53>, <53>, <53>, <53>;
68 status = "okay"; 75 status = "okay";
69 }; 76 };
70 77
71 &mac0 { 78 &mac0 {
72 status = "okay"; 79 status = "okay";
73 phy-mode = "sgmii"; 80 phy-mode = "sgmii";
74 phy-handle = <&phy0>; 81 phy-handle = <&phy0>;
75 phy1: ethernet-phy@9 { 82 phy1: ethernet-phy@9 {
76 reg = <9>; 83 reg = <9>;
77 }; 84 };
78 phy0: ethernet-phy@8 { 85 phy0: ethernet-phy@8 {
79 reg = <8>; 86 reg = <8>;
80 }; 87 };
81 }; 88 };
82 89
83 &mac1 { 90 &mac1 {
84 status = "okay"; 91 status = "okay";
85 phy-mode = "sgmii"; 92 phy-mode = "sgmii";
86 phy-handle = <&phy1>; 93 phy-handle = <&phy1>;
87 }; 94 };
88 95
89 &mbox { 96 &mbox {
90 status = "okay"; 97 status = "okay";
91 }; 98 };
92 99
93 &mmc { 100 &mmc {
94 status = "okay"; 101 status = "okay";
95 bus-width = <4>; 102 bus-width = <4>;
96 disable-wp; 103 disable-wp;
97 cap-sd-highspeed; 104 cap-sd-highspeed;
98 cap-mmc-highspeed; 105 cap-mmc-highspeed;
99 mmc-ddr-1_8v; 106 mmc-ddr-1_8v;
100 mmc-hs200-1_8v; 107 mmc-hs200-1_8v;
101 sd-uhs-sdr12; 108 sd-uhs-sdr12;
102 sd-uhs-sdr25; 109 sd-uhs-sdr25;
103 sd-uhs-sdr50; 110 sd-uhs-sdr50;
104 sd-uhs-sdr104; 111 sd-uhs-sdr104;
105 }; 112 };
106 113
107 &mmuart1 { 114 &mmuart1 {
108 status = "okay"; 115 status = "okay";
109 }; 116 };
110 117
111 &mmuart2 { 118 &mmuart2 {
112 status = "okay"; 119 status = "okay";
113 }; 120 };
114 121
115 &mmuart3 { 122 &mmuart3 {
116 status = "okay"; 123 status = "okay";
117 }; 124 };
118 125
119 &mmuart4 { 126 &mmuart4 {
120 status = "okay"; 127 status = "okay";
121 }; 128 };
122 129
123 &refclk { 130 &refclk {
124 clock-frequency = <125000000>; 131 clock-frequency = <125000000>;
125 }; 132 };
126 133
127 &rtc { 134 &rtc {
128 status = "okay"; 135 status = "okay";
129 }; 136 };
130 137
131 &syscontroller { 138 &syscontroller {
132 status = "okay"; 139 status = "okay";
133 }; 140 };
134 141
135 &usb { 142 &usb {
136 status = "okay"; 143 status = "okay";
137 dr_mode = "otg"; 144 dr_mode = "otg";
138 }; 145 };
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