1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* 2 /*
3 * Copyright (C) 2023 Jisheng Zhang <jszhang@ke 3 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
4 * Copyright (C) 2023 Inochi Amaoto <inochiama@ 4 * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
5 */ 5 */
6 6
7 #include <dt-bindings/clock/sophgo,cv1800.h> <<
8 #include <dt-bindings/gpio/gpio.h> <<
9 #include <dt-bindings/interrupt-controller/irq 7 #include <dt-bindings/interrupt-controller/irq.h>
10 8
11 / { 9 / {
12 #address-cells = <1>; 10 #address-cells = <1>;
13 #size-cells = <1>; 11 #size-cells = <1>;
14 12
15 cpus: cpus { 13 cpus: cpus {
16 #address-cells = <1>; 14 #address-cells = <1>;
17 #size-cells = <0>; 15 #size-cells = <0>;
18 timebase-frequency = <25000000 16 timebase-frequency = <25000000>;
19 17
20 cpu0: cpu@0 { 18 cpu0: cpu@0 {
21 compatible = "thead,c9 19 compatible = "thead,c906", "riscv";
22 device_type = "cpu"; 20 device_type = "cpu";
23 reg = <0>; 21 reg = <0>;
24 d-cache-block-size = < 22 d-cache-block-size = <64>;
25 d-cache-sets = <512>; 23 d-cache-sets = <512>;
26 d-cache-size = <65536> 24 d-cache-size = <65536>;
27 i-cache-block-size = < 25 i-cache-block-size = <64>;
28 i-cache-sets = <128>; 26 i-cache-sets = <128>;
29 i-cache-size = <32768> 27 i-cache-size = <32768>;
30 mmu-type = "riscv,sv39 28 mmu-type = "riscv,sv39";
31 riscv,isa = "rv64imafd 29 riscv,isa = "rv64imafdc";
32 riscv,isa-base = "rv64 30 riscv,isa-base = "rv64i";
33 riscv,isa-extensions = 31 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
34 32 "zifencei", "zihpm";
35 33
36 cpu0_intc: interrupt-c 34 cpu0_intc: interrupt-controller {
37 compatible = " 35 compatible = "riscv,cpu-intc";
38 interrupt-cont 36 interrupt-controller;
39 #interrupt-cel 37 #interrupt-cells = <1>;
40 }; 38 };
41 }; 39 };
42 }; 40 };
43 41
44 osc: oscillator { 42 osc: oscillator {
45 compatible = "fixed-clock"; 43 compatible = "fixed-clock";
46 clock-output-names = "osc_25m" 44 clock-output-names = "osc_25m";
47 #clock-cells = <0>; 45 #clock-cells = <0>;
48 }; 46 };
49 47
50 soc { 48 soc {
51 compatible = "simple-bus"; 49 compatible = "simple-bus";
52 interrupt-parent = <&plic>; 50 interrupt-parent = <&plic>;
53 #address-cells = <1>; 51 #address-cells = <1>;
54 #size-cells = <1>; 52 #size-cells = <1>;
55 dma-noncoherent; 53 dma-noncoherent;
56 ranges; 54 ranges;
57 55
58 clk: clock-controller@3002000 <<
59 reg = <0x03002000 0x10 <<
60 clocks = <&osc>; <<
61 #clock-cells = <1>; <<
62 }; <<
63 <<
64 gpio0: gpio@3020000 { 56 gpio0: gpio@3020000 {
65 compatible = "snps,dw- 57 compatible = "snps,dw-apb-gpio";
66 reg = <0x3020000 0x100 58 reg = <0x3020000 0x1000>;
67 #address-cells = <1>; 59 #address-cells = <1>;
68 #size-cells = <0>; 60 #size-cells = <0>;
69 61
70 porta: gpio-controller 62 porta: gpio-controller@0 {
71 compatible = " 63 compatible = "snps,dw-apb-gpio-port";
72 gpio-controlle 64 gpio-controller;
73 #gpio-cells = 65 #gpio-cells = <2>;
74 ngpios = <32>; 66 ngpios = <32>;
75 reg = <0>; 67 reg = <0>;
76 interrupt-cont 68 interrupt-controller;
77 #interrupt-cel 69 #interrupt-cells = <2>;
78 interrupts = < 70 interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
79 }; 71 };
80 }; 72 };
81 73
82 gpio1: gpio@3021000 { 74 gpio1: gpio@3021000 {
83 compatible = "snps,dw- 75 compatible = "snps,dw-apb-gpio";
84 reg = <0x3021000 0x100 76 reg = <0x3021000 0x1000>;
85 #address-cells = <1>; 77 #address-cells = <1>;
86 #size-cells = <0>; 78 #size-cells = <0>;
87 79
88 portb: gpio-controller 80 portb: gpio-controller@0 {
89 compatible = " 81 compatible = "snps,dw-apb-gpio-port";
90 gpio-controlle 82 gpio-controller;
91 #gpio-cells = 83 #gpio-cells = <2>;
92 ngpios = <32>; 84 ngpios = <32>;
93 reg = <0>; 85 reg = <0>;
94 interrupt-cont 86 interrupt-controller;
95 #interrupt-cel 87 #interrupt-cells = <2>;
96 interrupts = < 88 interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
97 }; 89 };
98 }; 90 };
99 91
100 gpio2: gpio@3022000 { 92 gpio2: gpio@3022000 {
101 compatible = "snps,dw- 93 compatible = "snps,dw-apb-gpio";
102 reg = <0x3022000 0x100 94 reg = <0x3022000 0x1000>;
103 #address-cells = <1>; 95 #address-cells = <1>;
104 #size-cells = <0>; 96 #size-cells = <0>;
105 97
106 portc: gpio-controller 98 portc: gpio-controller@0 {
107 compatible = " 99 compatible = "snps,dw-apb-gpio-port";
108 gpio-controlle 100 gpio-controller;
109 #gpio-cells = 101 #gpio-cells = <2>;
110 ngpios = <32>; 102 ngpios = <32>;
111 reg = <0>; 103 reg = <0>;
112 interrupt-cont 104 interrupt-controller;
113 #interrupt-cel 105 #interrupt-cells = <2>;
114 interrupts = < 106 interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
115 }; 107 };
116 }; 108 };
117 109
118 gpio3: gpio@3023000 { 110 gpio3: gpio@3023000 {
119 compatible = "snps,dw- 111 compatible = "snps,dw-apb-gpio";
120 reg = <0x3023000 0x100 112 reg = <0x3023000 0x1000>;
121 #address-cells = <1>; 113 #address-cells = <1>;
122 #size-cells = <0>; 114 #size-cells = <0>;
123 115
124 portd: gpio-controller 116 portd: gpio-controller@0 {
125 compatible = " 117 compatible = "snps,dw-apb-gpio-port";
126 gpio-controlle 118 gpio-controller;
127 #gpio-cells = 119 #gpio-cells = <2>;
128 ngpios = <32>; 120 ngpios = <32>;
129 reg = <0>; 121 reg = <0>;
130 interrupt-cont 122 interrupt-controller;
131 #interrupt-cel 123 #interrupt-cells = <2>;
132 interrupts = < 124 interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
133 }; 125 };
134 }; 126 };
135 127
136 i2c0: i2c@4000000 { <<
137 compatible = "snps,des <<
138 reg = <0x04000000 0x10 <<
139 #address-cells = <1>; <<
140 #size-cells = <0>; <<
141 clocks = <&clk CLK_I2C <<
142 clock-names = "ref", " <<
143 interrupts = <49 IRQ_T <<
144 status = "disabled"; <<
145 }; <<
146 <<
147 i2c1: i2c@4010000 { <<
148 compatible = "snps,des <<
149 reg = <0x04010000 0x10 <<
150 #address-cells = <1>; <<
151 #size-cells = <0>; <<
152 clocks = <&clk CLK_I2C <<
153 clock-names = "ref", " <<
154 interrupts = <50 IRQ_T <<
155 status = "disabled"; <<
156 }; <<
157 <<
158 i2c2: i2c@4020000 { <<
159 compatible = "snps,des <<
160 reg = <0x04020000 0x10 <<
161 #address-cells = <1>; <<
162 #size-cells = <0>; <<
163 clocks = <&clk CLK_I2C <<
164 clock-names = "ref", " <<
165 interrupts = <51 IRQ_T <<
166 status = "disabled"; <<
167 }; <<
168 <<
169 i2c3: i2c@4030000 { <<
170 compatible = "snps,des <<
171 reg = <0x04030000 0x10 <<
172 #address-cells = <1>; <<
173 #size-cells = <0>; <<
174 clocks = <&clk CLK_I2C <<
175 clock-names = "ref", " <<
176 interrupts = <52 IRQ_T <<
177 status = "disabled"; <<
178 }; <<
179 <<
180 i2c4: i2c@4040000 { <<
181 compatible = "snps,des <<
182 reg = <0x04040000 0x10 <<
183 #address-cells = <1>; <<
184 #size-cells = <0>; <<
185 clocks = <&clk CLK_I2C <<
186 clock-names = "ref", " <<
187 interrupts = <53 IRQ_T <<
188 status = "disabled"; <<
189 }; <<
190 <<
191 uart0: serial@4140000 { 128 uart0: serial@4140000 {
192 compatible = "snps,dw- 129 compatible = "snps,dw-apb-uart";
193 reg = <0x04140000 0x10 130 reg = <0x04140000 0x100>;
194 interrupts = <44 IRQ_T 131 interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
195 clocks = <&clk CLK_UAR !! 132 clocks = <&osc>;
196 clock-names = "baudclk <<
197 reg-shift = <2>; 133 reg-shift = <2>;
198 reg-io-width = <4>; 134 reg-io-width = <4>;
199 status = "disabled"; 135 status = "disabled";
200 }; 136 };
201 137
202 uart1: serial@4150000 { 138 uart1: serial@4150000 {
203 compatible = "snps,dw- 139 compatible = "snps,dw-apb-uart";
204 reg = <0x04150000 0x10 140 reg = <0x04150000 0x100>;
205 interrupts = <45 IRQ_T 141 interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
206 clocks = <&clk CLK_UAR !! 142 clocks = <&osc>;
207 clock-names = "baudclk <<
208 reg-shift = <2>; 143 reg-shift = <2>;
209 reg-io-width = <4>; 144 reg-io-width = <4>;
210 status = "disabled"; 145 status = "disabled";
211 }; 146 };
212 147
213 uart2: serial@4160000 { 148 uart2: serial@4160000 {
214 compatible = "snps,dw- 149 compatible = "snps,dw-apb-uart";
215 reg = <0x04160000 0x10 150 reg = <0x04160000 0x100>;
216 interrupts = <46 IRQ_T 151 interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&clk CLK_UAR !! 152 clocks = <&osc>;
218 clock-names = "baudclk <<
219 reg-shift = <2>; 153 reg-shift = <2>;
220 reg-io-width = <4>; 154 reg-io-width = <4>;
221 status = "disabled"; 155 status = "disabled";
222 }; 156 };
223 157
224 uart3: serial@4170000 { 158 uart3: serial@4170000 {
225 compatible = "snps,dw- 159 compatible = "snps,dw-apb-uart";
226 reg = <0x04170000 0x10 160 reg = <0x04170000 0x100>;
227 interrupts = <47 IRQ_T 161 interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&clk CLK_UAR !! 162 clocks = <&osc>;
229 clock-names = "baudclk <<
230 reg-shift = <2>; 163 reg-shift = <2>;
231 reg-io-width = <4>; 164 reg-io-width = <4>;
232 status = "disabled"; 165 status = "disabled";
233 }; 166 };
234 167
235 spi0: spi@4180000 { <<
236 compatible = "snps,dw- <<
237 reg = <0x04180000 0x10 <<
238 #address-cells = <1>; <<
239 #size-cells = <0>; <<
240 clocks = <&clk CLK_SPI <<
241 clock-names = "ssi_clk <<
242 interrupts = <54 IRQ_T <<
243 status = "disabled"; <<
244 }; <<
245 <<
246 spi1: spi@4190000 { <<
247 compatible = "snps,dw- <<
248 reg = <0x04190000 0x10 <<
249 #address-cells = <1>; <<
250 #size-cells = <0>; <<
251 clocks = <&clk CLK_SPI <<
252 clock-names = "ssi_clk <<
253 interrupts = <55 IRQ_T <<
254 status = "disabled"; <<
255 }; <<
256 <<
257 spi2: spi@41a0000 { <<
258 compatible = "snps,dw- <<
259 reg = <0x041a0000 0x10 <<
260 #address-cells = <1>; <<
261 #size-cells = <0>; <<
262 clocks = <&clk CLK_SPI <<
263 clock-names = "ssi_clk <<
264 interrupts = <56 IRQ_T <<
265 status = "disabled"; <<
266 }; <<
267 <<
268 spi3: spi@41b0000 { <<
269 compatible = "snps,dw- <<
270 reg = <0x041b0000 0x10 <<
271 #address-cells = <1>; <<
272 #size-cells = <0>; <<
273 clocks = <&clk CLK_SPI <<
274 clock-names = "ssi_clk <<
275 interrupts = <57 IRQ_T <<
276 status = "disabled"; <<
277 }; <<
278 <<
279 uart4: serial@41c0000 { 168 uart4: serial@41c0000 {
280 compatible = "snps,dw- 169 compatible = "snps,dw-apb-uart";
281 reg = <0x041c0000 0x10 170 reg = <0x041c0000 0x100>;
282 interrupts = <48 IRQ_T 171 interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&clk CLK_UAR !! 172 clocks = <&osc>;
284 clock-names = "baudclk <<
285 reg-shift = <2>; 173 reg-shift = <2>;
286 reg-io-width = <4>; 174 reg-io-width = <4>;
287 status = "disabled"; <<
288 }; <<
289 <<
290 sdhci0: mmc@4310000 { <<
291 compatible = "sophgo,c <<
292 reg = <0x4310000 0x100 <<
293 interrupts = <36 IRQ_T <<
294 clocks = <&clk CLK_AXI <<
295 <&clk CLK_SD0 <<
296 clock-names = "core", <<
297 status = "disabled"; <<
298 }; <<
299 <<
300 dmac: dma-controller@4330000 { <<
301 compatible = "snps,axi <<
302 reg = <0x04330000 0x10 <<
303 interrupts = <29 IRQ_T <<
304 clocks = <&clk CLK_SDM <<
305 clock-names = "core-cl <<
306 #dma-cells = <1>; <<
307 dma-channels = <8>; <<
308 snps,block-size = <102 <<
309 102 <<
310 snps,priority = <0 1 2 <<
311 snps,dma-masters = <2> <<
312 snps,data-width = <4>; <<
313 status = "disabled"; 175 status = "disabled";
314 }; 176 };
315 177
316 plic: interrupt-controller@700 178 plic: interrupt-controller@70000000 {
317 reg = <0x70000000 0x40 179 reg = <0x70000000 0x4000000>;
318 interrupts-extended = 180 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
319 interrupt-controller; 181 interrupt-controller;
320 #address-cells = <0>; 182 #address-cells = <0>;
321 #interrupt-cells = <2> 183 #interrupt-cells = <2>;
322 riscv,ndev = <101>; 184 riscv,ndev = <101>;
323 }; 185 };
324 186
325 clint: timer@74000000 { 187 clint: timer@74000000 {
326 reg = <0x74000000 0x10 188 reg = <0x74000000 0x10000>;
327 interrupts-extended = 189 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
328 }; 190 };
329 }; 191 };
330 }; 192 };
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