1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3 * Copyright (C) 2022 Sophgo Technology Inc. A
4 */
5
6 /dts-v1/;
7 #include <dt-bindings/clock/sophgo,sg2042-clkg
8 #include <dt-bindings/clock/sophgo,sg2042-pll.
9 #include <dt-bindings/clock/sophgo,sg2042-rpga
10 #include <dt-bindings/interrupt-controller/irq
11 #include <dt-bindings/reset/sophgo,sg2042-rese
12
13 #include "sg2042-cpus.dtsi"
14
15 / {
16 compatible = "sophgo,sg2042";
17 #address-cells = <2>;
18 #size-cells = <2>;
19 dma-noncoherent;
20
21 aliases {
22 serial0 = &uart0;
23 };
24
25 cgi_main: oscillator0 {
26 compatible = "fixed-clock";
27 clock-output-names = "cgi_main
28 #clock-cells = <0>;
29 };
30
31 cgi_dpll0: oscillator1 {
32 compatible = "fixed-clock";
33 clock-output-names = "cgi_dpll
34 #clock-cells = <0>;
35 };
36
37 cgi_dpll1: oscillator2 {
38 compatible = "fixed-clock";
39 clock-output-names = "cgi_dpll
40 #clock-cells = <0>;
41 };
42
43 soc: soc {
44 compatible = "simple-bus";
45 #address-cells = <2>;
46 #size-cells = <2>;
47 interrupt-parent = <&intc>;
48 ranges;
49
50 i2c0: i2c@7030005000 {
51 compatible = "snps,des
52 reg = <0x70 0x30005000
53 #address-cells = <1>;
54 #size-cells = <0>;
55 clocks = <&clkgen GATE
56 clock-names = "ref";
57 clock-frequency = <100
58 interrupts = <101 IRQ_
59 resets = <&rstgen RST_
60 status = "disabled";
61 };
62
63 i2c1: i2c@7030006000 {
64 compatible = "snps,des
65 reg = <0x70 0x30006000
66 #address-cells = <1>;
67 #size-cells = <0>;
68 clocks = <&clkgen GATE
69 clock-names = "ref";
70 clock-frequency = <100
71 interrupts = <102 IRQ_
72 resets = <&rstgen RST_
73 status = "disabled";
74 };
75
76 i2c2: i2c@7030007000 {
77 compatible = "snps,des
78 reg = <0x70 0x30007000
79 #address-cells = <1>;
80 #size-cells = <0>;
81 clocks = <&clkgen GATE
82 clock-names = "ref";
83 clock-frequency = <100
84 interrupts = <103 IRQ_
85 resets = <&rstgen RST_
86 status = "disabled";
87 };
88
89 i2c3: i2c@7030008000 {
90 compatible = "snps,des
91 reg = <0x70 0x30008000
92 #address-cells = <1>;
93 #size-cells = <0>;
94 clocks = <&clkgen GATE
95 clock-names = "ref";
96 clock-frequency = <100
97 interrupts = <104 IRQ_
98 resets = <&rstgen RST_
99 status = "disabled";
100 };
101
102 gpio0: gpio@7030009000 {
103 compatible = "snps,dw-
104 reg = <0x70 0x30009000
105 #address-cells = <1>;
106 #size-cells = <0>;
107 clocks = <&clkgen GATE
108 <&clkgen GATE
109 clock-names = "bus", "
110
111 port0a: gpio-controlle
112 compatible = "
113 gpio-controlle
114 #gpio-cells =
115 ngpios = <32>;
116 reg = <0>;
117 interrupt-cont
118 #interrupt-cel
119 interrupt-pare
120 interrupts = <
121 };
122 };
123
124 gpio1: gpio@703000a000 {
125 compatible = "snps,dw-
126 reg = <0x70 0x3000a000
127 #address-cells = <1>;
128 #size-cells = <0>;
129 clocks = <&clkgen GATE
130 <&clkgen GATE
131 clock-names = "bus", "
132
133 port1a: gpio-controlle
134 compatible = "
135 gpio-controlle
136 #gpio-cells =
137 ngpios = <32>;
138 reg = <0>;
139 interrupt-cont
140 #interrupt-cel
141 interrupt-pare
142 interrupts = <
143 };
144 };
145
146 gpio2: gpio@703000b000 {
147 compatible = "snps,dw-
148 reg = <0x70 0x3000b000
149 #address-cells = <1>;
150 #size-cells = <0>;
151 clocks = <&clkgen GATE
152 <&clkgen GATE
153 clock-names = "bus", "
154
155 port2a: gpio-controlle
156 compatible = "
157 gpio-controlle
158 #gpio-cells =
159 ngpios = <32>;
160 reg = <0>;
161 interrupt-cont
162 #interrupt-cel
163 interrupt-pare
164 interrupts = <
165 };
166 };
167
168 pllclk: clock-controller@70300
169 compatible = "sophgo,s
170 reg = <0x70 0x300100c0
171 clocks = <&cgi_main>,
172 clock-names = "cgi_mai
173 #clock-cells = <1>;
174 };
175
176 rpgate: clock-controller@70300
177 compatible = "sophgo,s
178 reg = <0x70 0x30010368
179 clocks = <&clkgen GATE
180 clock-names = "rpgate"
181 #clock-cells = <1>;
182 };
183
184 clkgen: clock-controller@70300
185 compatible = "sophgo,s
186 reg = <0x70 0x30012000
187 clocks = <&pllclk MPLL
188 <&pllclk FPLL
189 <&pllclk DPLL
190 <&pllclk DPLL
191 clock-names = "mpll",
192 "fpll",
193 "dpll0",
194 "dpll1";
195 #clock-cells = <1>;
196 };
197
198 clint_mswi: interrupt-controll
199 compatible = "sophgo,s
200 reg = <0x00000070 0x94
201 interrupts-extended =
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
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255
256
257
258
259
260
261
262
263
264
265 };
266
267 clint_mtimer0: timer@70ac00400
268 compatible = "sophgo,s
269 reg = <0x00000070 0xac
270 reg-names = "mtimecmp"
271 interrupts-extended =
272
273
274
275 };
276
277 clint_mtimer1: timer@70ac01400
278 compatible = "sophgo,s
279 reg = <0x00000070 0xac
280 reg-names = "mtimecmp"
281 interrupts-extended =
282
283
284
285 };
286
287 clint_mtimer2: timer@70ac02400
288 compatible = "sophgo,s
289 reg = <0x00000070 0xac
290 reg-names = "mtimecmp"
291 interrupts-extended =
292
293
294
295 };
296
297 clint_mtimer3: timer@70ac03400
298 compatible = "sophgo,s
299 reg = <0x00000070 0xac
300 reg-names = "mtimecmp"
301 interrupts-extended =
302
303
304
305 };
306
307 clint_mtimer4: timer@70ac04400
308 compatible = "sophgo,s
309 reg = <0x00000070 0xac
310 reg-names = "mtimecmp"
311 interrupts-extended =
312
313
314
315 };
316
317 clint_mtimer5: timer@70ac05400
318 compatible = "sophgo,s
319 reg = <0x00000070 0xac
320 reg-names = "mtimecmp"
321 interrupts-extended =
322
323
324
325 };
326
327 clint_mtimer6: timer@70ac06400
328 compatible = "sophgo,s
329 reg = <0x00000070 0xac
330 reg-names = "mtimecmp"
331 interrupts-extended =
332
333
334
335 };
336
337 clint_mtimer7: timer@70ac07400
338 compatible = "sophgo,s
339 reg = <0x00000070 0xac
340 reg-names = "mtimecmp"
341 interrupts-extended =
342
343
344
345 };
346
347 clint_mtimer8: timer@70ac08400
348 compatible = "sophgo,s
349 reg = <0x00000070 0xac
350 reg-names = "mtimecmp"
351 interrupts-extended =
352
353
354
355 };
356
357 clint_mtimer9: timer@70ac09400
358 compatible = "sophgo,s
359 reg = <0x00000070 0xac
360 reg-names = "mtimecmp"
361 interrupts-extended =
362
363
364
365 };
366
367 clint_mtimer10: timer@70ac0a40
368 compatible = "sophgo,s
369 reg = <0x00000070 0xac
370 reg-names = "mtimecmp"
371 interrupts-extended =
372
373
374
375 };
376
377 clint_mtimer11: timer@70ac0b40
378 compatible = "sophgo,s
379 reg = <0x00000070 0xac
380 reg-names = "mtimecmp"
381 interrupts-extended =
382
383
384
385 };
386
387 clint_mtimer12: timer@70ac0c40
388 compatible = "sophgo,s
389 reg = <0x00000070 0xac
390 reg-names = "mtimecmp"
391 interrupts-extended =
392
393
394
395 };
396
397 clint_mtimer13: timer@70ac0d40
398 compatible = "sophgo,s
399 reg = <0x00000070 0xac
400 reg-names = "mtimecmp"
401 interrupts-extended =
402
403
404
405 };
406
407 clint_mtimer14: timer@70ac0e40
408 compatible = "sophgo,s
409 reg = <0x00000070 0xac
410 reg-names = "mtimecmp"
411 interrupts-extended =
412
413
414
415 };
416
417 clint_mtimer15: timer@70ac0f40
418 compatible = "sophgo,s
419 reg = <0x00000070 0xac
420 reg-names = "mtimecmp"
421 interrupts-extended =
422
423
424
425 };
426
427 intc: interrupt-controller@709
428 compatible = "sophgo,s
429 #address-cells = <0>;
430 #interrupt-cells = <2>
431 reg = <0x00000070 0x90
432 interrupt-controller;
433 interrupts-extended =
434 <&cpu0_intc 11
435 <&cpu1_intc 11
436 <&cpu2_intc 11
437 <&cpu3_intc 11
438 <&cpu4_intc 11
439 <&cpu5_intc 11
440 <&cpu6_intc 11
441 <&cpu7_intc 11
442 <&cpu8_intc 11
443 <&cpu9_intc 11
444 <&cpu10_intc 1
445 <&cpu11_intc 1
446 <&cpu12_intc 1
447 <&cpu13_intc 1
448 <&cpu14_intc 1
449 <&cpu15_intc 1
450 <&cpu16_intc 1
451 <&cpu17_intc 1
452 <&cpu18_intc 1
453 <&cpu19_intc 1
454 <&cpu20_intc 1
455 <&cpu21_intc 1
456 <&cpu22_intc 1
457 <&cpu23_intc 1
458 <&cpu24_intc 1
459 <&cpu25_intc 1
460 <&cpu26_intc 1
461 <&cpu27_intc 1
462 <&cpu28_intc 1
463 <&cpu29_intc 1
464 <&cpu30_intc 1
465 <&cpu31_intc 1
466 <&cpu32_intc 1
467 <&cpu33_intc 1
468 <&cpu34_intc 1
469 <&cpu35_intc 1
470 <&cpu36_intc 1
471 <&cpu37_intc 1
472 <&cpu38_intc 1
473 <&cpu39_intc 1
474 <&cpu40_intc 1
475 <&cpu41_intc 1
476 <&cpu42_intc 1
477 <&cpu43_intc 1
478 <&cpu44_intc 1
479 <&cpu45_intc 1
480 <&cpu46_intc 1
481 <&cpu47_intc 1
482 <&cpu48_intc 1
483 <&cpu49_intc 1
484 <&cpu50_intc 1
485 <&cpu51_intc 1
486 <&cpu52_intc 1
487 <&cpu53_intc 1
488 <&cpu54_intc 1
489 <&cpu55_intc 1
490 <&cpu56_intc 1
491 <&cpu57_intc 1
492 <&cpu58_intc 1
493 <&cpu59_intc 1
494 <&cpu60_intc 1
495 <&cpu61_intc 1
496 <&cpu62_intc 1
497 <&cpu63_intc 1
498 riscv,ndev = <224>;
499 };
500
501 rstgen: reset-controller@70300
502 compatible = "sophgo,s
503 reg = <0x00000070 0x30
504 #reset-cells = <1>;
505 };
506
507 uart0: serial@7040000000 {
508 compatible = "snps,dw-
509 reg = <0x00000070 0x40
510 interrupts = <112 IRQ_
511 clock-frequency = <500
512 clocks = <&clkgen GATE
513 <&clkgen GATE
514 clock-names = "baudclk
515 reg-shift = <2>;
516 reg-io-width = <4>;
517 resets = <&rstgen RST_
518 status = "disabled";
519 };
520
521 emmc: mmc@704002a000 {
522 compatible = "sophgo,s
523 reg = <0x70 0x4002a000
524 interrupt-parent = <&i
525 interrupts = <134 IRQ_
526 clocks = <&clkgen GATE
527 <&clkgen GATE
528 <&clkgen GATE
529 clock-names = "core",
530 "bus",
531 "timer";
532 status = "disabled";
533 };
534
535 sd: mmc@704002b000 {
536 compatible = "sophgo,s
537 reg = <0x70 0x4002b000
538 interrupt-parent = <&i
539 interrupts = <136 IRQ_
540 clocks = <&clkgen GATE
541 <&clkgen GATE
542 <&clkgen GATE
543 clock-names = "core",
544 "bus",
545 "timer";
546 status = "disabled";
547 };
548 };
549 };
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