Linux/scripts/dtc/include-prefixes/riscv/sophgo/sg2042.dtsi

Version: ~ [ linux-6.12-rc7 ] ~ [ linux-6.11.7 ] ~ [ linux-6.10.14 ] ~ [ linux-6.9.12 ] ~ [ linux-6.8.12 ] ~ [ linux-6.7.12 ] ~ [ linux-6.6.60 ] ~ [ linux-6.5.13 ] ~ [ linux-6.4.16 ] ~ [ linux-6.3.13 ] ~ [ linux-6.2.16 ] ~ [ linux-6.1.116 ] ~ [ linux-6.0.19 ] ~ [ linux-5.19.17 ] ~ [ linux-5.18.19 ] ~ [ linux-5.17.15 ] ~ [ linux-5.16.20 ] ~ [ linux-5.15.171 ] ~ [ linux-5.14.21 ] ~ [ linux-5.13.19 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.229 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.285 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.323 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.336 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.337 ] ~ [ linux-4.4.302 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.12 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

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1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 2 /* 3 * Copyright (C) 2022 Sophgo Technology Inc. A 3 * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved. 4 */ 4 */ 5 5 6 /dts-v1/; 6 /dts-v1/; 7 #include <dt-bindings/clock/sophgo,sg2042-clkg << 8 #include <dt-bindings/clock/sophgo,sg2042-pll. << 9 #include <dt-bindings/clock/sophgo,sg2042-rpga << 10 #include <dt-bindings/interrupt-controller/irq 7 #include <dt-bindings/interrupt-controller/irq.h> >> 8 11 #include <dt-bindings/reset/sophgo,sg2042-rese 9 #include <dt-bindings/reset/sophgo,sg2042-reset.h> 12 10 13 #include "sg2042-cpus.dtsi" 11 #include "sg2042-cpus.dtsi" 14 12 15 / { 13 / { 16 compatible = "sophgo,sg2042"; 14 compatible = "sophgo,sg2042"; 17 #address-cells = <2>; 15 #address-cells = <2>; 18 #size-cells = <2>; 16 #size-cells = <2>; 19 dma-noncoherent; 17 dma-noncoherent; 20 18 21 aliases { 19 aliases { 22 serial0 = &uart0; 20 serial0 = &uart0; 23 }; 21 }; 24 22 25 cgi_main: oscillator0 { << 26 compatible = "fixed-clock"; << 27 clock-output-names = "cgi_main << 28 #clock-cells = <0>; << 29 }; << 30 << 31 cgi_dpll0: oscillator1 { << 32 compatible = "fixed-clock"; << 33 clock-output-names = "cgi_dpll << 34 #clock-cells = <0>; << 35 }; << 36 << 37 cgi_dpll1: oscillator2 { << 38 compatible = "fixed-clock"; << 39 clock-output-names = "cgi_dpll << 40 #clock-cells = <0>; << 41 }; << 42 << 43 soc: soc { 23 soc: soc { 44 compatible = "simple-bus"; 24 compatible = "simple-bus"; 45 #address-cells = <2>; 25 #address-cells = <2>; 46 #size-cells = <2>; 26 #size-cells = <2>; 47 interrupt-parent = <&intc>; << 48 ranges; 27 ranges; 49 28 50 i2c0: i2c@7030005000 { << 51 compatible = "snps,des << 52 reg = <0x70 0x30005000 << 53 #address-cells = <1>; << 54 #size-cells = <0>; << 55 clocks = <&clkgen GATE << 56 clock-names = "ref"; << 57 clock-frequency = <100 << 58 interrupts = <101 IRQ_ << 59 resets = <&rstgen RST_ << 60 status = "disabled"; << 61 }; << 62 << 63 i2c1: i2c@7030006000 { << 64 compatible = "snps,des << 65 reg = <0x70 0x30006000 << 66 #address-cells = <1>; << 67 #size-cells = <0>; << 68 clocks = <&clkgen GATE << 69 clock-names = "ref"; << 70 clock-frequency = <100 << 71 interrupts = <102 IRQ_ << 72 resets = <&rstgen RST_ << 73 status = "disabled"; << 74 }; << 75 << 76 i2c2: i2c@7030007000 { << 77 compatible = "snps,des << 78 reg = <0x70 0x30007000 << 79 #address-cells = <1>; << 80 #size-cells = <0>; << 81 clocks = <&clkgen GATE << 82 clock-names = "ref"; << 83 clock-frequency = <100 << 84 interrupts = <103 IRQ_ << 85 resets = <&rstgen RST_ << 86 status = "disabled"; << 87 }; << 88 << 89 i2c3: i2c@7030008000 { << 90 compatible = "snps,des << 91 reg = <0x70 0x30008000 << 92 #address-cells = <1>; << 93 #size-cells = <0>; << 94 clocks = <&clkgen GATE << 95 clock-names = "ref"; << 96 clock-frequency = <100 << 97 interrupts = <104 IRQ_ << 98 resets = <&rstgen RST_ << 99 status = "disabled"; << 100 }; << 101 << 102 gpio0: gpio@7030009000 { << 103 compatible = "snps,dw- << 104 reg = <0x70 0x30009000 << 105 #address-cells = <1>; << 106 #size-cells = <0>; << 107 clocks = <&clkgen GATE << 108 <&clkgen GATE << 109 clock-names = "bus", " << 110 << 111 port0a: gpio-controlle << 112 compatible = " << 113 gpio-controlle << 114 #gpio-cells = << 115 ngpios = <32>; << 116 reg = <0>; << 117 interrupt-cont << 118 #interrupt-cel << 119 interrupt-pare << 120 interrupts = < << 121 }; << 122 }; << 123 << 124 gpio1: gpio@703000a000 { << 125 compatible = "snps,dw- << 126 reg = <0x70 0x3000a000 << 127 #address-cells = <1>; << 128 #size-cells = <0>; << 129 clocks = <&clkgen GATE << 130 <&clkgen GATE << 131 clock-names = "bus", " << 132 << 133 port1a: gpio-controlle << 134 compatible = " << 135 gpio-controlle << 136 #gpio-cells = << 137 ngpios = <32>; << 138 reg = <0>; << 139 interrupt-cont << 140 #interrupt-cel << 141 interrupt-pare << 142 interrupts = < << 143 }; << 144 }; << 145 << 146 gpio2: gpio@703000b000 { << 147 compatible = "snps,dw- << 148 reg = <0x70 0x3000b000 << 149 #address-cells = <1>; << 150 #size-cells = <0>; << 151 clocks = <&clkgen GATE << 152 <&clkgen GATE << 153 clock-names = "bus", " << 154 << 155 port2a: gpio-controlle << 156 compatible = " << 157 gpio-controlle << 158 #gpio-cells = << 159 ngpios = <32>; << 160 reg = <0>; << 161 interrupt-cont << 162 #interrupt-cel << 163 interrupt-pare << 164 interrupts = < << 165 }; << 166 }; << 167 << 168 pllclk: clock-controller@70300 << 169 compatible = "sophgo,s << 170 reg = <0x70 0x300100c0 << 171 clocks = <&cgi_main>, << 172 clock-names = "cgi_mai << 173 #clock-cells = <1>; << 174 }; << 175 << 176 rpgate: clock-controller@70300 << 177 compatible = "sophgo,s << 178 reg = <0x70 0x30010368 << 179 clocks = <&clkgen GATE << 180 clock-names = "rpgate" << 181 #clock-cells = <1>; << 182 }; << 183 << 184 clkgen: clock-controller@70300 << 185 compatible = "sophgo,s << 186 reg = <0x70 0x30012000 << 187 clocks = <&pllclk MPLL << 188 <&pllclk FPLL << 189 <&pllclk DPLL << 190 <&pllclk DPLL << 191 clock-names = "mpll", << 192 "fpll", << 193 "dpll0", << 194 "dpll1"; << 195 #clock-cells = <1>; << 196 }; << 197 << 198 clint_mswi: interrupt-controll 29 clint_mswi: interrupt-controller@7094000000 { 199 compatible = "sophgo,s 30 compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi"; 200 reg = <0x00000070 0x94 31 reg = <0x00000070 0x94000000 0x00000000 0x00004000>; 201 interrupts-extended = 32 interrupts-extended = <&cpu0_intc 3>, 202 33 <&cpu1_intc 3>, 203 34 <&cpu2_intc 3>, 204 35 <&cpu3_intc 3>, 205 36 <&cpu4_intc 3>, 206 37 <&cpu5_intc 3>, 207 38 <&cpu6_intc 3>, 208 39 <&cpu7_intc 3>, 209 40 <&cpu8_intc 3>, 210 41 <&cpu9_intc 3>, 211 42 <&cpu10_intc 3>, 212 43 <&cpu11_intc 3>, 213 44 <&cpu12_intc 3>, 214 45 <&cpu13_intc 3>, 215 46 <&cpu14_intc 3>, 216 47 <&cpu15_intc 3>, 217 48 <&cpu16_intc 3>, 218 49 <&cpu17_intc 3>, 219 50 <&cpu18_intc 3>, 220 51 <&cpu19_intc 3>, 221 52 <&cpu20_intc 3>, 222 53 <&cpu21_intc 3>, 223 54 <&cpu22_intc 3>, 224 55 <&cpu23_intc 3>, 225 56 <&cpu24_intc 3>, 226 57 <&cpu25_intc 3>, 227 58 <&cpu26_intc 3>, 228 59 <&cpu27_intc 3>, 229 60 <&cpu28_intc 3>, 230 61 <&cpu29_intc 3>, 231 62 <&cpu30_intc 3>, 232 63 <&cpu31_intc 3>, 233 64 <&cpu32_intc 3>, 234 65 <&cpu33_intc 3>, 235 66 <&cpu34_intc 3>, 236 67 <&cpu35_intc 3>, 237 68 <&cpu36_intc 3>, 238 69 <&cpu37_intc 3>, 239 70 <&cpu38_intc 3>, 240 71 <&cpu39_intc 3>, 241 72 <&cpu40_intc 3>, 242 73 <&cpu41_intc 3>, 243 74 <&cpu42_intc 3>, 244 75 <&cpu43_intc 3>, 245 76 <&cpu44_intc 3>, 246 77 <&cpu45_intc 3>, 247 78 <&cpu46_intc 3>, 248 79 <&cpu47_intc 3>, 249 80 <&cpu48_intc 3>, 250 81 <&cpu49_intc 3>, 251 82 <&cpu50_intc 3>, 252 83 <&cpu51_intc 3>, 253 84 <&cpu52_intc 3>, 254 85 <&cpu53_intc 3>, 255 86 <&cpu54_intc 3>, 256 87 <&cpu55_intc 3>, 257 88 <&cpu56_intc 3>, 258 89 <&cpu57_intc 3>, 259 90 <&cpu58_intc 3>, 260 91 <&cpu59_intc 3>, 261 92 <&cpu60_intc 3>, 262 93 <&cpu61_intc 3>, 263 94 <&cpu62_intc 3>, 264 95 <&cpu63_intc 3>; 265 }; 96 }; 266 97 267 clint_mtimer0: timer@70ac00400 98 clint_mtimer0: timer@70ac004000 { 268 compatible = "sophgo,s 99 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 269 reg = <0x00000070 0xac 100 reg = <0x00000070 0xac004000 0x00000000 0x0000c000>; 270 reg-names = "mtimecmp" 101 reg-names = "mtimecmp"; 271 interrupts-extended = 102 interrupts-extended = <&cpu0_intc 7>, 272 103 <&cpu1_intc 7>, 273 104 <&cpu2_intc 7>, 274 105 <&cpu3_intc 7>; 275 }; 106 }; 276 107 277 clint_mtimer1: timer@70ac01400 108 clint_mtimer1: timer@70ac014000 { 278 compatible = "sophgo,s 109 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 279 reg = <0x00000070 0xac 110 reg = <0x00000070 0xac014000 0x00000000 0x0000c000>; 280 reg-names = "mtimecmp" 111 reg-names = "mtimecmp"; 281 interrupts-extended = 112 interrupts-extended = <&cpu4_intc 7>, 282 113 <&cpu5_intc 7>, 283 114 <&cpu6_intc 7>, 284 115 <&cpu7_intc 7>; 285 }; 116 }; 286 117 287 clint_mtimer2: timer@70ac02400 118 clint_mtimer2: timer@70ac024000 { 288 compatible = "sophgo,s 119 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 289 reg = <0x00000070 0xac 120 reg = <0x00000070 0xac024000 0x00000000 0x0000c000>; 290 reg-names = "mtimecmp" 121 reg-names = "mtimecmp"; 291 interrupts-extended = 122 interrupts-extended = <&cpu8_intc 7>, 292 123 <&cpu9_intc 7>, 293 124 <&cpu10_intc 7>, 294 125 <&cpu11_intc 7>; 295 }; 126 }; 296 127 297 clint_mtimer3: timer@70ac03400 128 clint_mtimer3: timer@70ac034000 { 298 compatible = "sophgo,s 129 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 299 reg = <0x00000070 0xac 130 reg = <0x00000070 0xac034000 0x00000000 0x0000c000>; 300 reg-names = "mtimecmp" 131 reg-names = "mtimecmp"; 301 interrupts-extended = 132 interrupts-extended = <&cpu12_intc 7>, 302 133 <&cpu13_intc 7>, 303 134 <&cpu14_intc 7>, 304 135 <&cpu15_intc 7>; 305 }; 136 }; 306 137 307 clint_mtimer4: timer@70ac04400 138 clint_mtimer4: timer@70ac044000 { 308 compatible = "sophgo,s 139 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 309 reg = <0x00000070 0xac 140 reg = <0x00000070 0xac044000 0x00000000 0x0000c000>; 310 reg-names = "mtimecmp" 141 reg-names = "mtimecmp"; 311 interrupts-extended = 142 interrupts-extended = <&cpu16_intc 7>, 312 143 <&cpu17_intc 7>, 313 144 <&cpu18_intc 7>, 314 145 <&cpu19_intc 7>; 315 }; 146 }; 316 147 317 clint_mtimer5: timer@70ac05400 148 clint_mtimer5: timer@70ac054000 { 318 compatible = "sophgo,s 149 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 319 reg = <0x00000070 0xac 150 reg = <0x00000070 0xac054000 0x00000000 0x0000c000>; 320 reg-names = "mtimecmp" 151 reg-names = "mtimecmp"; 321 interrupts-extended = 152 interrupts-extended = <&cpu20_intc 7>, 322 153 <&cpu21_intc 7>, 323 154 <&cpu22_intc 7>, 324 155 <&cpu23_intc 7>; 325 }; 156 }; 326 157 327 clint_mtimer6: timer@70ac06400 158 clint_mtimer6: timer@70ac064000 { 328 compatible = "sophgo,s 159 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 329 reg = <0x00000070 0xac 160 reg = <0x00000070 0xac064000 0x00000000 0x0000c000>; 330 reg-names = "mtimecmp" 161 reg-names = "mtimecmp"; 331 interrupts-extended = 162 interrupts-extended = <&cpu24_intc 7>, 332 163 <&cpu25_intc 7>, 333 164 <&cpu26_intc 7>, 334 165 <&cpu27_intc 7>; 335 }; 166 }; 336 167 337 clint_mtimer7: timer@70ac07400 168 clint_mtimer7: timer@70ac074000 { 338 compatible = "sophgo,s 169 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 339 reg = <0x00000070 0xac 170 reg = <0x00000070 0xac074000 0x00000000 0x0000c000>; 340 reg-names = "mtimecmp" 171 reg-names = "mtimecmp"; 341 interrupts-extended = 172 interrupts-extended = <&cpu28_intc 7>, 342 173 <&cpu29_intc 7>, 343 174 <&cpu30_intc 7>, 344 175 <&cpu31_intc 7>; 345 }; 176 }; 346 177 347 clint_mtimer8: timer@70ac08400 178 clint_mtimer8: timer@70ac084000 { 348 compatible = "sophgo,s 179 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 349 reg = <0x00000070 0xac 180 reg = <0x00000070 0xac084000 0x00000000 0x0000c000>; 350 reg-names = "mtimecmp" 181 reg-names = "mtimecmp"; 351 interrupts-extended = 182 interrupts-extended = <&cpu32_intc 7>, 352 183 <&cpu33_intc 7>, 353 184 <&cpu34_intc 7>, 354 185 <&cpu35_intc 7>; 355 }; 186 }; 356 187 357 clint_mtimer9: timer@70ac09400 188 clint_mtimer9: timer@70ac094000 { 358 compatible = "sophgo,s 189 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 359 reg = <0x00000070 0xac 190 reg = <0x00000070 0xac094000 0x00000000 0x0000c000>; 360 reg-names = "mtimecmp" 191 reg-names = "mtimecmp"; 361 interrupts-extended = 192 interrupts-extended = <&cpu36_intc 7>, 362 193 <&cpu37_intc 7>, 363 194 <&cpu38_intc 7>, 364 195 <&cpu39_intc 7>; 365 }; 196 }; 366 197 367 clint_mtimer10: timer@70ac0a40 198 clint_mtimer10: timer@70ac0a4000 { 368 compatible = "sophgo,s 199 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 369 reg = <0x00000070 0xac 200 reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>; 370 reg-names = "mtimecmp" 201 reg-names = "mtimecmp"; 371 interrupts-extended = 202 interrupts-extended = <&cpu40_intc 7>, 372 203 <&cpu41_intc 7>, 373 204 <&cpu42_intc 7>, 374 205 <&cpu43_intc 7>; 375 }; 206 }; 376 207 377 clint_mtimer11: timer@70ac0b40 208 clint_mtimer11: timer@70ac0b4000 { 378 compatible = "sophgo,s 209 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 379 reg = <0x00000070 0xac 210 reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>; 380 reg-names = "mtimecmp" 211 reg-names = "mtimecmp"; 381 interrupts-extended = 212 interrupts-extended = <&cpu44_intc 7>, 382 213 <&cpu45_intc 7>, 383 214 <&cpu46_intc 7>, 384 215 <&cpu47_intc 7>; 385 }; 216 }; 386 217 387 clint_mtimer12: timer@70ac0c40 218 clint_mtimer12: timer@70ac0c4000 { 388 compatible = "sophgo,s 219 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 389 reg = <0x00000070 0xac 220 reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>; 390 reg-names = "mtimecmp" 221 reg-names = "mtimecmp"; 391 interrupts-extended = 222 interrupts-extended = <&cpu48_intc 7>, 392 223 <&cpu49_intc 7>, 393 224 <&cpu50_intc 7>, 394 225 <&cpu51_intc 7>; 395 }; 226 }; 396 227 397 clint_mtimer13: timer@70ac0d40 228 clint_mtimer13: timer@70ac0d4000 { 398 compatible = "sophgo,s 229 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 399 reg = <0x00000070 0xac 230 reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>; 400 reg-names = "mtimecmp" 231 reg-names = "mtimecmp"; 401 interrupts-extended = 232 interrupts-extended = <&cpu52_intc 7>, 402 233 <&cpu53_intc 7>, 403 234 <&cpu54_intc 7>, 404 235 <&cpu55_intc 7>; 405 }; 236 }; 406 237 407 clint_mtimer14: timer@70ac0e40 238 clint_mtimer14: timer@70ac0e4000 { 408 compatible = "sophgo,s 239 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 409 reg = <0x00000070 0xac 240 reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>; 410 reg-names = "mtimecmp" 241 reg-names = "mtimecmp"; 411 interrupts-extended = 242 interrupts-extended = <&cpu56_intc 7>, 412 243 <&cpu57_intc 7>, 413 244 <&cpu58_intc 7>, 414 245 <&cpu59_intc 7>; 415 }; 246 }; 416 247 417 clint_mtimer15: timer@70ac0f40 248 clint_mtimer15: timer@70ac0f4000 { 418 compatible = "sophgo,s 249 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer"; 419 reg = <0x00000070 0xac 250 reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>; 420 reg-names = "mtimecmp" 251 reg-names = "mtimecmp"; 421 interrupts-extended = 252 interrupts-extended = <&cpu60_intc 7>, 422 253 <&cpu61_intc 7>, 423 254 <&cpu62_intc 7>, 424 255 <&cpu63_intc 7>; 425 }; 256 }; 426 257 427 intc: interrupt-controller@709 258 intc: interrupt-controller@7090000000 { 428 compatible = "sophgo,s 259 compatible = "sophgo,sg2042-plic", "thead,c900-plic"; 429 #address-cells = <0>; 260 #address-cells = <0>; 430 #interrupt-cells = <2> 261 #interrupt-cells = <2>; 431 reg = <0x00000070 0x90 262 reg = <0x00000070 0x90000000 0x00000000 0x04000000>; 432 interrupt-controller; 263 interrupt-controller; 433 interrupts-extended = 264 interrupts-extended = 434 <&cpu0_intc 11 265 <&cpu0_intc 11>, <&cpu0_intc 9>, 435 <&cpu1_intc 11 266 <&cpu1_intc 11>, <&cpu1_intc 9>, 436 <&cpu2_intc 11 267 <&cpu2_intc 11>, <&cpu2_intc 9>, 437 <&cpu3_intc 11 268 <&cpu3_intc 11>, <&cpu3_intc 9>, 438 <&cpu4_intc 11 269 <&cpu4_intc 11>, <&cpu4_intc 9>, 439 <&cpu5_intc 11 270 <&cpu5_intc 11>, <&cpu5_intc 9>, 440 <&cpu6_intc 11 271 <&cpu6_intc 11>, <&cpu6_intc 9>, 441 <&cpu7_intc 11 272 <&cpu7_intc 11>, <&cpu7_intc 9>, 442 <&cpu8_intc 11 273 <&cpu8_intc 11>, <&cpu8_intc 9>, 443 <&cpu9_intc 11 274 <&cpu9_intc 11>, <&cpu9_intc 9>, 444 <&cpu10_intc 1 275 <&cpu10_intc 11>, <&cpu10_intc 9>, 445 <&cpu11_intc 1 276 <&cpu11_intc 11>, <&cpu11_intc 9>, 446 <&cpu12_intc 1 277 <&cpu12_intc 11>, <&cpu12_intc 9>, 447 <&cpu13_intc 1 278 <&cpu13_intc 11>, <&cpu13_intc 9>, 448 <&cpu14_intc 1 279 <&cpu14_intc 11>, <&cpu14_intc 9>, 449 <&cpu15_intc 1 280 <&cpu15_intc 11>, <&cpu15_intc 9>, 450 <&cpu16_intc 1 281 <&cpu16_intc 11>, <&cpu16_intc 9>, 451 <&cpu17_intc 1 282 <&cpu17_intc 11>, <&cpu17_intc 9>, 452 <&cpu18_intc 1 283 <&cpu18_intc 11>, <&cpu18_intc 9>, 453 <&cpu19_intc 1 284 <&cpu19_intc 11>, <&cpu19_intc 9>, 454 <&cpu20_intc 1 285 <&cpu20_intc 11>, <&cpu20_intc 9>, 455 <&cpu21_intc 1 286 <&cpu21_intc 11>, <&cpu21_intc 9>, 456 <&cpu22_intc 1 287 <&cpu22_intc 11>, <&cpu22_intc 9>, 457 <&cpu23_intc 1 288 <&cpu23_intc 11>, <&cpu23_intc 9>, 458 <&cpu24_intc 1 289 <&cpu24_intc 11>, <&cpu24_intc 9>, 459 <&cpu25_intc 1 290 <&cpu25_intc 11>, <&cpu25_intc 9>, 460 <&cpu26_intc 1 291 <&cpu26_intc 11>, <&cpu26_intc 9>, 461 <&cpu27_intc 1 292 <&cpu27_intc 11>, <&cpu27_intc 9>, 462 <&cpu28_intc 1 293 <&cpu28_intc 11>, <&cpu28_intc 9>, 463 <&cpu29_intc 1 294 <&cpu29_intc 11>, <&cpu29_intc 9>, 464 <&cpu30_intc 1 295 <&cpu30_intc 11>, <&cpu30_intc 9>, 465 <&cpu31_intc 1 296 <&cpu31_intc 11>, <&cpu31_intc 9>, 466 <&cpu32_intc 1 297 <&cpu32_intc 11>, <&cpu32_intc 9>, 467 <&cpu33_intc 1 298 <&cpu33_intc 11>, <&cpu33_intc 9>, 468 <&cpu34_intc 1 299 <&cpu34_intc 11>, <&cpu34_intc 9>, 469 <&cpu35_intc 1 300 <&cpu35_intc 11>, <&cpu35_intc 9>, 470 <&cpu36_intc 1 301 <&cpu36_intc 11>, <&cpu36_intc 9>, 471 <&cpu37_intc 1 302 <&cpu37_intc 11>, <&cpu37_intc 9>, 472 <&cpu38_intc 1 303 <&cpu38_intc 11>, <&cpu38_intc 9>, 473 <&cpu39_intc 1 304 <&cpu39_intc 11>, <&cpu39_intc 9>, 474 <&cpu40_intc 1 305 <&cpu40_intc 11>, <&cpu40_intc 9>, 475 <&cpu41_intc 1 306 <&cpu41_intc 11>, <&cpu41_intc 9>, 476 <&cpu42_intc 1 307 <&cpu42_intc 11>, <&cpu42_intc 9>, 477 <&cpu43_intc 1 308 <&cpu43_intc 11>, <&cpu43_intc 9>, 478 <&cpu44_intc 1 309 <&cpu44_intc 11>, <&cpu44_intc 9>, 479 <&cpu45_intc 1 310 <&cpu45_intc 11>, <&cpu45_intc 9>, 480 <&cpu46_intc 1 311 <&cpu46_intc 11>, <&cpu46_intc 9>, 481 <&cpu47_intc 1 312 <&cpu47_intc 11>, <&cpu47_intc 9>, 482 <&cpu48_intc 1 313 <&cpu48_intc 11>, <&cpu48_intc 9>, 483 <&cpu49_intc 1 314 <&cpu49_intc 11>, <&cpu49_intc 9>, 484 <&cpu50_intc 1 315 <&cpu50_intc 11>, <&cpu50_intc 9>, 485 <&cpu51_intc 1 316 <&cpu51_intc 11>, <&cpu51_intc 9>, 486 <&cpu52_intc 1 317 <&cpu52_intc 11>, <&cpu52_intc 9>, 487 <&cpu53_intc 1 318 <&cpu53_intc 11>, <&cpu53_intc 9>, 488 <&cpu54_intc 1 319 <&cpu54_intc 11>, <&cpu54_intc 9>, 489 <&cpu55_intc 1 320 <&cpu55_intc 11>, <&cpu55_intc 9>, 490 <&cpu56_intc 1 321 <&cpu56_intc 11>, <&cpu56_intc 9>, 491 <&cpu57_intc 1 322 <&cpu57_intc 11>, <&cpu57_intc 9>, 492 <&cpu58_intc 1 323 <&cpu58_intc 11>, <&cpu58_intc 9>, 493 <&cpu59_intc 1 324 <&cpu59_intc 11>, <&cpu59_intc 9>, 494 <&cpu60_intc 1 325 <&cpu60_intc 11>, <&cpu60_intc 9>, 495 <&cpu61_intc 1 326 <&cpu61_intc 11>, <&cpu61_intc 9>, 496 <&cpu62_intc 1 327 <&cpu62_intc 11>, <&cpu62_intc 9>, 497 <&cpu63_intc 1 328 <&cpu63_intc 11>, <&cpu63_intc 9>; 498 riscv,ndev = <224>; 329 riscv,ndev = <224>; 499 }; 330 }; 500 331 501 rstgen: reset-controller@70300 332 rstgen: reset-controller@7030013000 { 502 compatible = "sophgo,s 333 compatible = "sophgo,sg2042-reset"; 503 reg = <0x00000070 0x30 334 reg = <0x00000070 0x30013000 0x00000000 0x0000000c>; 504 #reset-cells = <1>; 335 #reset-cells = <1>; 505 }; 336 }; 506 337 507 uart0: serial@7040000000 { 338 uart0: serial@7040000000 { 508 compatible = "snps,dw- 339 compatible = "snps,dw-apb-uart"; 509 reg = <0x00000070 0x40 340 reg = <0x00000070 0x40000000 0x00000000 0x00001000>; >> 341 interrupt-parent = <&intc>; 510 interrupts = <112 IRQ_ 342 interrupts = <112 IRQ_TYPE_LEVEL_HIGH>; 511 clock-frequency = <500 343 clock-frequency = <500000000>; 512 clocks = <&clkgen GATE << 513 <&clkgen GATE << 514 clock-names = "baudclk << 515 reg-shift = <2>; 344 reg-shift = <2>; 516 reg-io-width = <4>; 345 reg-io-width = <4>; 517 resets = <&rstgen RST_ 346 resets = <&rstgen RST_UART0>; 518 status = "disabled"; << 519 }; << 520 << 521 emmc: mmc@704002a000 { << 522 compatible = "sophgo,s << 523 reg = <0x70 0x4002a000 << 524 interrupt-parent = <&i << 525 interrupts = <134 IRQ_ << 526 clocks = <&clkgen GATE << 527 <&clkgen GATE << 528 <&clkgen GATE << 529 clock-names = "core", << 530 "bus", << 531 "timer"; << 532 status = "disabled"; << 533 }; << 534 << 535 sd: mmc@704002b000 { << 536 compatible = "sophgo,s << 537 reg = <0x70 0x4002b000 << 538 interrupt-parent = <&i << 539 interrupts = <136 IRQ_ << 540 clocks = <&clkgen GATE << 541 <&clkgen GATE << 542 <&clkgen GATE << 543 clock-names = "core", << 544 "bus", << 545 "timer"; << 546 status = "disabled"; 347 status = "disabled"; 547 }; 348 }; 548 }; 349 }; 549 }; 350 };

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TOMOYO Linux Cross Reference
Linux/scripts/dtc/include-prefixes/riscv/sophgo/sg2042.dtsi

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Differences between /scripts/dtc/include-prefixes/riscv/sophgo/sg2042.dtsi (Version linux-6.12-rc7) and /scripts/dtc/include-prefixes/riscv/sophgo/sg2042.dtsi (Version linux-6.10.14)

TOMOYO Linux Cross Reference Linux/scripts/dtc/include-prefixes/riscv/sophgo/sg2042.dtsi

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Differences between /scripts/dtc/include-prefixes/riscv/sophgo/sg2042.dtsi (Version linux-6.12-rc7) and /scripts/dtc/include-prefixes/riscv/sophgo/sg2042.dtsi (Version linux-6.10.14)

TOMOYO Linux Cross Reference
Linux/scripts/dtc/include-prefixes/riscv/sophgo/sg2042.dtsi