1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* 2 /*
3 * Copyright (C) 2022 Sophgo Technology Inc. A 3 * Copyright (C) 2022 Sophgo Technology Inc. All rights reserved.
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 #include <dt-bindings/clock/sophgo,sg2042-clkg 7 #include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
8 #include <dt-bindings/clock/sophgo,sg2042-pll. 8 #include <dt-bindings/clock/sophgo,sg2042-pll.h>
9 #include <dt-bindings/clock/sophgo,sg2042-rpga 9 #include <dt-bindings/clock/sophgo,sg2042-rpgate.h>
10 #include <dt-bindings/interrupt-controller/irq 10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/reset/sophgo,sg2042-rese 11 #include <dt-bindings/reset/sophgo,sg2042-reset.h>
12 12
13 #include "sg2042-cpus.dtsi" 13 #include "sg2042-cpus.dtsi"
14 14
15 / { 15 / {
16 compatible = "sophgo,sg2042"; 16 compatible = "sophgo,sg2042";
17 #address-cells = <2>; 17 #address-cells = <2>;
18 #size-cells = <2>; 18 #size-cells = <2>;
19 dma-noncoherent; 19 dma-noncoherent;
20 20
21 aliases { 21 aliases {
22 serial0 = &uart0; 22 serial0 = &uart0;
23 }; 23 };
24 24
25 cgi_main: oscillator0 { 25 cgi_main: oscillator0 {
26 compatible = "fixed-clock"; 26 compatible = "fixed-clock";
27 clock-output-names = "cgi_main 27 clock-output-names = "cgi_main";
28 #clock-cells = <0>; 28 #clock-cells = <0>;
29 }; 29 };
30 30
31 cgi_dpll0: oscillator1 { 31 cgi_dpll0: oscillator1 {
32 compatible = "fixed-clock"; 32 compatible = "fixed-clock";
33 clock-output-names = "cgi_dpll 33 clock-output-names = "cgi_dpll0";
34 #clock-cells = <0>; 34 #clock-cells = <0>;
35 }; 35 };
36 36
37 cgi_dpll1: oscillator2 { 37 cgi_dpll1: oscillator2 {
38 compatible = "fixed-clock"; 38 compatible = "fixed-clock";
39 clock-output-names = "cgi_dpll 39 clock-output-names = "cgi_dpll1";
40 #clock-cells = <0>; 40 #clock-cells = <0>;
41 }; 41 };
42 42
43 soc: soc { 43 soc: soc {
44 compatible = "simple-bus"; 44 compatible = "simple-bus";
45 #address-cells = <2>; 45 #address-cells = <2>;
46 #size-cells = <2>; 46 #size-cells = <2>;
47 interrupt-parent = <&intc>; <<
48 ranges; 47 ranges;
49 48
50 i2c0: i2c@7030005000 { <<
51 compatible = "snps,des <<
52 reg = <0x70 0x30005000 <<
53 #address-cells = <1>; <<
54 #size-cells = <0>; <<
55 clocks = <&clkgen GATE <<
56 clock-names = "ref"; <<
57 clock-frequency = <100 <<
58 interrupts = <101 IRQ_ <<
59 resets = <&rstgen RST_ <<
60 status = "disabled"; <<
61 }; <<
62 <<
63 i2c1: i2c@7030006000 { <<
64 compatible = "snps,des <<
65 reg = <0x70 0x30006000 <<
66 #address-cells = <1>; <<
67 #size-cells = <0>; <<
68 clocks = <&clkgen GATE <<
69 clock-names = "ref"; <<
70 clock-frequency = <100 <<
71 interrupts = <102 IRQ_ <<
72 resets = <&rstgen RST_ <<
73 status = "disabled"; <<
74 }; <<
75 <<
76 i2c2: i2c@7030007000 { <<
77 compatible = "snps,des <<
78 reg = <0x70 0x30007000 <<
79 #address-cells = <1>; <<
80 #size-cells = <0>; <<
81 clocks = <&clkgen GATE <<
82 clock-names = "ref"; <<
83 clock-frequency = <100 <<
84 interrupts = <103 IRQ_ <<
85 resets = <&rstgen RST_ <<
86 status = "disabled"; <<
87 }; <<
88 <<
89 i2c3: i2c@7030008000 { <<
90 compatible = "snps,des <<
91 reg = <0x70 0x30008000 <<
92 #address-cells = <1>; <<
93 #size-cells = <0>; <<
94 clocks = <&clkgen GATE <<
95 clock-names = "ref"; <<
96 clock-frequency = <100 <<
97 interrupts = <104 IRQ_ <<
98 resets = <&rstgen RST_ <<
99 status = "disabled"; <<
100 }; <<
101 <<
102 gpio0: gpio@7030009000 { <<
103 compatible = "snps,dw- <<
104 reg = <0x70 0x30009000 <<
105 #address-cells = <1>; <<
106 #size-cells = <0>; <<
107 clocks = <&clkgen GATE <<
108 <&clkgen GATE <<
109 clock-names = "bus", " <<
110 <<
111 port0a: gpio-controlle <<
112 compatible = " <<
113 gpio-controlle <<
114 #gpio-cells = <<
115 ngpios = <32>; <<
116 reg = <0>; <<
117 interrupt-cont <<
118 #interrupt-cel <<
119 interrupt-pare <<
120 interrupts = < <<
121 }; <<
122 }; <<
123 <<
124 gpio1: gpio@703000a000 { <<
125 compatible = "snps,dw- <<
126 reg = <0x70 0x3000a000 <<
127 #address-cells = <1>; <<
128 #size-cells = <0>; <<
129 clocks = <&clkgen GATE <<
130 <&clkgen GATE <<
131 clock-names = "bus", " <<
132 <<
133 port1a: gpio-controlle <<
134 compatible = " <<
135 gpio-controlle <<
136 #gpio-cells = <<
137 ngpios = <32>; <<
138 reg = <0>; <<
139 interrupt-cont <<
140 #interrupt-cel <<
141 interrupt-pare <<
142 interrupts = < <<
143 }; <<
144 }; <<
145 <<
146 gpio2: gpio@703000b000 { <<
147 compatible = "snps,dw- <<
148 reg = <0x70 0x3000b000 <<
149 #address-cells = <1>; <<
150 #size-cells = <0>; <<
151 clocks = <&clkgen GATE <<
152 <&clkgen GATE <<
153 clock-names = "bus", " <<
154 <<
155 port2a: gpio-controlle <<
156 compatible = " <<
157 gpio-controlle <<
158 #gpio-cells = <<
159 ngpios = <32>; <<
160 reg = <0>; <<
161 interrupt-cont <<
162 #interrupt-cel <<
163 interrupt-pare <<
164 interrupts = < <<
165 }; <<
166 }; <<
167 <<
168 pllclk: clock-controller@70300 49 pllclk: clock-controller@70300100c0 {
169 compatible = "sophgo,s 50 compatible = "sophgo,sg2042-pll";
170 reg = <0x70 0x300100c0 51 reg = <0x70 0x300100c0 0x0 0x40>;
171 clocks = <&cgi_main>, 52 clocks = <&cgi_main>, <&cgi_dpll0>, <&cgi_dpll1>;
172 clock-names = "cgi_mai 53 clock-names = "cgi_main", "cgi_dpll0", "cgi_dpll1";
173 #clock-cells = <1>; 54 #clock-cells = <1>;
174 }; 55 };
175 56
176 rpgate: clock-controller@70300 57 rpgate: clock-controller@7030010368 {
177 compatible = "sophgo,s 58 compatible = "sophgo,sg2042-rpgate";
178 reg = <0x70 0x30010368 59 reg = <0x70 0x30010368 0x0 0x98>;
179 clocks = <&clkgen GATE 60 clocks = <&clkgen GATE_CLK_RP_CPU_NORMAL>;
180 clock-names = "rpgate" 61 clock-names = "rpgate";
181 #clock-cells = <1>; 62 #clock-cells = <1>;
182 }; 63 };
183 64
184 clkgen: clock-controller@70300 65 clkgen: clock-controller@7030012000 {
185 compatible = "sophgo,s 66 compatible = "sophgo,sg2042-clkgen";
186 reg = <0x70 0x30012000 67 reg = <0x70 0x30012000 0x0 0x1000>;
187 clocks = <&pllclk MPLL 68 clocks = <&pllclk MPLL_CLK>,
188 <&pllclk FPLL 69 <&pllclk FPLL_CLK>,
189 <&pllclk DPLL 70 <&pllclk DPLL0_CLK>,
190 <&pllclk DPLL 71 <&pllclk DPLL1_CLK>;
191 clock-names = "mpll", 72 clock-names = "mpll",
192 "fpll", 73 "fpll",
193 "dpll0", 74 "dpll0",
194 "dpll1"; 75 "dpll1";
195 #clock-cells = <1>; 76 #clock-cells = <1>;
196 }; 77 };
197 78
198 clint_mswi: interrupt-controll 79 clint_mswi: interrupt-controller@7094000000 {
199 compatible = "sophgo,s 80 compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
200 reg = <0x00000070 0x94 81 reg = <0x00000070 0x94000000 0x00000000 0x00004000>;
201 interrupts-extended = 82 interrupts-extended = <&cpu0_intc 3>,
202 83 <&cpu1_intc 3>,
203 84 <&cpu2_intc 3>,
204 85 <&cpu3_intc 3>,
205 86 <&cpu4_intc 3>,
206 87 <&cpu5_intc 3>,
207 88 <&cpu6_intc 3>,
208 89 <&cpu7_intc 3>,
209 90 <&cpu8_intc 3>,
210 91 <&cpu9_intc 3>,
211 92 <&cpu10_intc 3>,
212 93 <&cpu11_intc 3>,
213 94 <&cpu12_intc 3>,
214 95 <&cpu13_intc 3>,
215 96 <&cpu14_intc 3>,
216 97 <&cpu15_intc 3>,
217 98 <&cpu16_intc 3>,
218 99 <&cpu17_intc 3>,
219 100 <&cpu18_intc 3>,
220 101 <&cpu19_intc 3>,
221 102 <&cpu20_intc 3>,
222 103 <&cpu21_intc 3>,
223 104 <&cpu22_intc 3>,
224 105 <&cpu23_intc 3>,
225 106 <&cpu24_intc 3>,
226 107 <&cpu25_intc 3>,
227 108 <&cpu26_intc 3>,
228 109 <&cpu27_intc 3>,
229 110 <&cpu28_intc 3>,
230 111 <&cpu29_intc 3>,
231 112 <&cpu30_intc 3>,
232 113 <&cpu31_intc 3>,
233 114 <&cpu32_intc 3>,
234 115 <&cpu33_intc 3>,
235 116 <&cpu34_intc 3>,
236 117 <&cpu35_intc 3>,
237 118 <&cpu36_intc 3>,
238 119 <&cpu37_intc 3>,
239 120 <&cpu38_intc 3>,
240 121 <&cpu39_intc 3>,
241 122 <&cpu40_intc 3>,
242 123 <&cpu41_intc 3>,
243 124 <&cpu42_intc 3>,
244 125 <&cpu43_intc 3>,
245 126 <&cpu44_intc 3>,
246 127 <&cpu45_intc 3>,
247 128 <&cpu46_intc 3>,
248 129 <&cpu47_intc 3>,
249 130 <&cpu48_intc 3>,
250 131 <&cpu49_intc 3>,
251 132 <&cpu50_intc 3>,
252 133 <&cpu51_intc 3>,
253 134 <&cpu52_intc 3>,
254 135 <&cpu53_intc 3>,
255 136 <&cpu54_intc 3>,
256 137 <&cpu55_intc 3>,
257 138 <&cpu56_intc 3>,
258 139 <&cpu57_intc 3>,
259 140 <&cpu58_intc 3>,
260 141 <&cpu59_intc 3>,
261 142 <&cpu60_intc 3>,
262 143 <&cpu61_intc 3>,
263 144 <&cpu62_intc 3>,
264 145 <&cpu63_intc 3>;
265 }; 146 };
266 147
267 clint_mtimer0: timer@70ac00400 148 clint_mtimer0: timer@70ac004000 {
268 compatible = "sophgo,s 149 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
269 reg = <0x00000070 0xac 150 reg = <0x00000070 0xac004000 0x00000000 0x0000c000>;
270 reg-names = "mtimecmp" 151 reg-names = "mtimecmp";
271 interrupts-extended = 152 interrupts-extended = <&cpu0_intc 7>,
272 153 <&cpu1_intc 7>,
273 154 <&cpu2_intc 7>,
274 155 <&cpu3_intc 7>;
275 }; 156 };
276 157
277 clint_mtimer1: timer@70ac01400 158 clint_mtimer1: timer@70ac014000 {
278 compatible = "sophgo,s 159 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
279 reg = <0x00000070 0xac 160 reg = <0x00000070 0xac014000 0x00000000 0x0000c000>;
280 reg-names = "mtimecmp" 161 reg-names = "mtimecmp";
281 interrupts-extended = 162 interrupts-extended = <&cpu4_intc 7>,
282 163 <&cpu5_intc 7>,
283 164 <&cpu6_intc 7>,
284 165 <&cpu7_intc 7>;
285 }; 166 };
286 167
287 clint_mtimer2: timer@70ac02400 168 clint_mtimer2: timer@70ac024000 {
288 compatible = "sophgo,s 169 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
289 reg = <0x00000070 0xac 170 reg = <0x00000070 0xac024000 0x00000000 0x0000c000>;
290 reg-names = "mtimecmp" 171 reg-names = "mtimecmp";
291 interrupts-extended = 172 interrupts-extended = <&cpu8_intc 7>,
292 173 <&cpu9_intc 7>,
293 174 <&cpu10_intc 7>,
294 175 <&cpu11_intc 7>;
295 }; 176 };
296 177
297 clint_mtimer3: timer@70ac03400 178 clint_mtimer3: timer@70ac034000 {
298 compatible = "sophgo,s 179 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
299 reg = <0x00000070 0xac 180 reg = <0x00000070 0xac034000 0x00000000 0x0000c000>;
300 reg-names = "mtimecmp" 181 reg-names = "mtimecmp";
301 interrupts-extended = 182 interrupts-extended = <&cpu12_intc 7>,
302 183 <&cpu13_intc 7>,
303 184 <&cpu14_intc 7>,
304 185 <&cpu15_intc 7>;
305 }; 186 };
306 187
307 clint_mtimer4: timer@70ac04400 188 clint_mtimer4: timer@70ac044000 {
308 compatible = "sophgo,s 189 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
309 reg = <0x00000070 0xac 190 reg = <0x00000070 0xac044000 0x00000000 0x0000c000>;
310 reg-names = "mtimecmp" 191 reg-names = "mtimecmp";
311 interrupts-extended = 192 interrupts-extended = <&cpu16_intc 7>,
312 193 <&cpu17_intc 7>,
313 194 <&cpu18_intc 7>,
314 195 <&cpu19_intc 7>;
315 }; 196 };
316 197
317 clint_mtimer5: timer@70ac05400 198 clint_mtimer5: timer@70ac054000 {
318 compatible = "sophgo,s 199 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
319 reg = <0x00000070 0xac 200 reg = <0x00000070 0xac054000 0x00000000 0x0000c000>;
320 reg-names = "mtimecmp" 201 reg-names = "mtimecmp";
321 interrupts-extended = 202 interrupts-extended = <&cpu20_intc 7>,
322 203 <&cpu21_intc 7>,
323 204 <&cpu22_intc 7>,
324 205 <&cpu23_intc 7>;
325 }; 206 };
326 207
327 clint_mtimer6: timer@70ac06400 208 clint_mtimer6: timer@70ac064000 {
328 compatible = "sophgo,s 209 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
329 reg = <0x00000070 0xac 210 reg = <0x00000070 0xac064000 0x00000000 0x0000c000>;
330 reg-names = "mtimecmp" 211 reg-names = "mtimecmp";
331 interrupts-extended = 212 interrupts-extended = <&cpu24_intc 7>,
332 213 <&cpu25_intc 7>,
333 214 <&cpu26_intc 7>,
334 215 <&cpu27_intc 7>;
335 }; 216 };
336 217
337 clint_mtimer7: timer@70ac07400 218 clint_mtimer7: timer@70ac074000 {
338 compatible = "sophgo,s 219 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
339 reg = <0x00000070 0xac 220 reg = <0x00000070 0xac074000 0x00000000 0x0000c000>;
340 reg-names = "mtimecmp" 221 reg-names = "mtimecmp";
341 interrupts-extended = 222 interrupts-extended = <&cpu28_intc 7>,
342 223 <&cpu29_intc 7>,
343 224 <&cpu30_intc 7>,
344 225 <&cpu31_intc 7>;
345 }; 226 };
346 227
347 clint_mtimer8: timer@70ac08400 228 clint_mtimer8: timer@70ac084000 {
348 compatible = "sophgo,s 229 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
349 reg = <0x00000070 0xac 230 reg = <0x00000070 0xac084000 0x00000000 0x0000c000>;
350 reg-names = "mtimecmp" 231 reg-names = "mtimecmp";
351 interrupts-extended = 232 interrupts-extended = <&cpu32_intc 7>,
352 233 <&cpu33_intc 7>,
353 234 <&cpu34_intc 7>,
354 235 <&cpu35_intc 7>;
355 }; 236 };
356 237
357 clint_mtimer9: timer@70ac09400 238 clint_mtimer9: timer@70ac094000 {
358 compatible = "sophgo,s 239 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
359 reg = <0x00000070 0xac 240 reg = <0x00000070 0xac094000 0x00000000 0x0000c000>;
360 reg-names = "mtimecmp" 241 reg-names = "mtimecmp";
361 interrupts-extended = 242 interrupts-extended = <&cpu36_intc 7>,
362 243 <&cpu37_intc 7>,
363 244 <&cpu38_intc 7>,
364 245 <&cpu39_intc 7>;
365 }; 246 };
366 247
367 clint_mtimer10: timer@70ac0a40 248 clint_mtimer10: timer@70ac0a4000 {
368 compatible = "sophgo,s 249 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
369 reg = <0x00000070 0xac 250 reg = <0x00000070 0xac0a4000 0x00000000 0x0000c000>;
370 reg-names = "mtimecmp" 251 reg-names = "mtimecmp";
371 interrupts-extended = 252 interrupts-extended = <&cpu40_intc 7>,
372 253 <&cpu41_intc 7>,
373 254 <&cpu42_intc 7>,
374 255 <&cpu43_intc 7>;
375 }; 256 };
376 257
377 clint_mtimer11: timer@70ac0b40 258 clint_mtimer11: timer@70ac0b4000 {
378 compatible = "sophgo,s 259 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
379 reg = <0x00000070 0xac 260 reg = <0x00000070 0xac0b4000 0x00000000 0x0000c000>;
380 reg-names = "mtimecmp" 261 reg-names = "mtimecmp";
381 interrupts-extended = 262 interrupts-extended = <&cpu44_intc 7>,
382 263 <&cpu45_intc 7>,
383 264 <&cpu46_intc 7>,
384 265 <&cpu47_intc 7>;
385 }; 266 };
386 267
387 clint_mtimer12: timer@70ac0c40 268 clint_mtimer12: timer@70ac0c4000 {
388 compatible = "sophgo,s 269 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
389 reg = <0x00000070 0xac 270 reg = <0x00000070 0xac0c4000 0x00000000 0x0000c000>;
390 reg-names = "mtimecmp" 271 reg-names = "mtimecmp";
391 interrupts-extended = 272 interrupts-extended = <&cpu48_intc 7>,
392 273 <&cpu49_intc 7>,
393 274 <&cpu50_intc 7>,
394 275 <&cpu51_intc 7>;
395 }; 276 };
396 277
397 clint_mtimer13: timer@70ac0d40 278 clint_mtimer13: timer@70ac0d4000 {
398 compatible = "sophgo,s 279 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
399 reg = <0x00000070 0xac 280 reg = <0x00000070 0xac0d4000 0x00000000 0x0000c000>;
400 reg-names = "mtimecmp" 281 reg-names = "mtimecmp";
401 interrupts-extended = 282 interrupts-extended = <&cpu52_intc 7>,
402 283 <&cpu53_intc 7>,
403 284 <&cpu54_intc 7>,
404 285 <&cpu55_intc 7>;
405 }; 286 };
406 287
407 clint_mtimer14: timer@70ac0e40 288 clint_mtimer14: timer@70ac0e4000 {
408 compatible = "sophgo,s 289 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
409 reg = <0x00000070 0xac 290 reg = <0x00000070 0xac0e4000 0x00000000 0x0000c000>;
410 reg-names = "mtimecmp" 291 reg-names = "mtimecmp";
411 interrupts-extended = 292 interrupts-extended = <&cpu56_intc 7>,
412 293 <&cpu57_intc 7>,
413 294 <&cpu58_intc 7>,
414 295 <&cpu59_intc 7>;
415 }; 296 };
416 297
417 clint_mtimer15: timer@70ac0f40 298 clint_mtimer15: timer@70ac0f4000 {
418 compatible = "sophgo,s 299 compatible = "sophgo,sg2042-aclint-mtimer", "thead,c900-aclint-mtimer";
419 reg = <0x00000070 0xac 300 reg = <0x00000070 0xac0f4000 0x00000000 0x0000c000>;
420 reg-names = "mtimecmp" 301 reg-names = "mtimecmp";
421 interrupts-extended = 302 interrupts-extended = <&cpu60_intc 7>,
422 303 <&cpu61_intc 7>,
423 304 <&cpu62_intc 7>,
424 305 <&cpu63_intc 7>;
425 }; 306 };
426 307
427 intc: interrupt-controller@709 308 intc: interrupt-controller@7090000000 {
428 compatible = "sophgo,s 309 compatible = "sophgo,sg2042-plic", "thead,c900-plic";
429 #address-cells = <0>; 310 #address-cells = <0>;
430 #interrupt-cells = <2> 311 #interrupt-cells = <2>;
431 reg = <0x00000070 0x90 312 reg = <0x00000070 0x90000000 0x00000000 0x04000000>;
432 interrupt-controller; 313 interrupt-controller;
433 interrupts-extended = 314 interrupts-extended =
434 <&cpu0_intc 11 315 <&cpu0_intc 11>, <&cpu0_intc 9>,
435 <&cpu1_intc 11 316 <&cpu1_intc 11>, <&cpu1_intc 9>,
436 <&cpu2_intc 11 317 <&cpu2_intc 11>, <&cpu2_intc 9>,
437 <&cpu3_intc 11 318 <&cpu3_intc 11>, <&cpu3_intc 9>,
438 <&cpu4_intc 11 319 <&cpu4_intc 11>, <&cpu4_intc 9>,
439 <&cpu5_intc 11 320 <&cpu5_intc 11>, <&cpu5_intc 9>,
440 <&cpu6_intc 11 321 <&cpu6_intc 11>, <&cpu6_intc 9>,
441 <&cpu7_intc 11 322 <&cpu7_intc 11>, <&cpu7_intc 9>,
442 <&cpu8_intc 11 323 <&cpu8_intc 11>, <&cpu8_intc 9>,
443 <&cpu9_intc 11 324 <&cpu9_intc 11>, <&cpu9_intc 9>,
444 <&cpu10_intc 1 325 <&cpu10_intc 11>, <&cpu10_intc 9>,
445 <&cpu11_intc 1 326 <&cpu11_intc 11>, <&cpu11_intc 9>,
446 <&cpu12_intc 1 327 <&cpu12_intc 11>, <&cpu12_intc 9>,
447 <&cpu13_intc 1 328 <&cpu13_intc 11>, <&cpu13_intc 9>,
448 <&cpu14_intc 1 329 <&cpu14_intc 11>, <&cpu14_intc 9>,
449 <&cpu15_intc 1 330 <&cpu15_intc 11>, <&cpu15_intc 9>,
450 <&cpu16_intc 1 331 <&cpu16_intc 11>, <&cpu16_intc 9>,
451 <&cpu17_intc 1 332 <&cpu17_intc 11>, <&cpu17_intc 9>,
452 <&cpu18_intc 1 333 <&cpu18_intc 11>, <&cpu18_intc 9>,
453 <&cpu19_intc 1 334 <&cpu19_intc 11>, <&cpu19_intc 9>,
454 <&cpu20_intc 1 335 <&cpu20_intc 11>, <&cpu20_intc 9>,
455 <&cpu21_intc 1 336 <&cpu21_intc 11>, <&cpu21_intc 9>,
456 <&cpu22_intc 1 337 <&cpu22_intc 11>, <&cpu22_intc 9>,
457 <&cpu23_intc 1 338 <&cpu23_intc 11>, <&cpu23_intc 9>,
458 <&cpu24_intc 1 339 <&cpu24_intc 11>, <&cpu24_intc 9>,
459 <&cpu25_intc 1 340 <&cpu25_intc 11>, <&cpu25_intc 9>,
460 <&cpu26_intc 1 341 <&cpu26_intc 11>, <&cpu26_intc 9>,
461 <&cpu27_intc 1 342 <&cpu27_intc 11>, <&cpu27_intc 9>,
462 <&cpu28_intc 1 343 <&cpu28_intc 11>, <&cpu28_intc 9>,
463 <&cpu29_intc 1 344 <&cpu29_intc 11>, <&cpu29_intc 9>,
464 <&cpu30_intc 1 345 <&cpu30_intc 11>, <&cpu30_intc 9>,
465 <&cpu31_intc 1 346 <&cpu31_intc 11>, <&cpu31_intc 9>,
466 <&cpu32_intc 1 347 <&cpu32_intc 11>, <&cpu32_intc 9>,
467 <&cpu33_intc 1 348 <&cpu33_intc 11>, <&cpu33_intc 9>,
468 <&cpu34_intc 1 349 <&cpu34_intc 11>, <&cpu34_intc 9>,
469 <&cpu35_intc 1 350 <&cpu35_intc 11>, <&cpu35_intc 9>,
470 <&cpu36_intc 1 351 <&cpu36_intc 11>, <&cpu36_intc 9>,
471 <&cpu37_intc 1 352 <&cpu37_intc 11>, <&cpu37_intc 9>,
472 <&cpu38_intc 1 353 <&cpu38_intc 11>, <&cpu38_intc 9>,
473 <&cpu39_intc 1 354 <&cpu39_intc 11>, <&cpu39_intc 9>,
474 <&cpu40_intc 1 355 <&cpu40_intc 11>, <&cpu40_intc 9>,
475 <&cpu41_intc 1 356 <&cpu41_intc 11>, <&cpu41_intc 9>,
476 <&cpu42_intc 1 357 <&cpu42_intc 11>, <&cpu42_intc 9>,
477 <&cpu43_intc 1 358 <&cpu43_intc 11>, <&cpu43_intc 9>,
478 <&cpu44_intc 1 359 <&cpu44_intc 11>, <&cpu44_intc 9>,
479 <&cpu45_intc 1 360 <&cpu45_intc 11>, <&cpu45_intc 9>,
480 <&cpu46_intc 1 361 <&cpu46_intc 11>, <&cpu46_intc 9>,
481 <&cpu47_intc 1 362 <&cpu47_intc 11>, <&cpu47_intc 9>,
482 <&cpu48_intc 1 363 <&cpu48_intc 11>, <&cpu48_intc 9>,
483 <&cpu49_intc 1 364 <&cpu49_intc 11>, <&cpu49_intc 9>,
484 <&cpu50_intc 1 365 <&cpu50_intc 11>, <&cpu50_intc 9>,
485 <&cpu51_intc 1 366 <&cpu51_intc 11>, <&cpu51_intc 9>,
486 <&cpu52_intc 1 367 <&cpu52_intc 11>, <&cpu52_intc 9>,
487 <&cpu53_intc 1 368 <&cpu53_intc 11>, <&cpu53_intc 9>,
488 <&cpu54_intc 1 369 <&cpu54_intc 11>, <&cpu54_intc 9>,
489 <&cpu55_intc 1 370 <&cpu55_intc 11>, <&cpu55_intc 9>,
490 <&cpu56_intc 1 371 <&cpu56_intc 11>, <&cpu56_intc 9>,
491 <&cpu57_intc 1 372 <&cpu57_intc 11>, <&cpu57_intc 9>,
492 <&cpu58_intc 1 373 <&cpu58_intc 11>, <&cpu58_intc 9>,
493 <&cpu59_intc 1 374 <&cpu59_intc 11>, <&cpu59_intc 9>,
494 <&cpu60_intc 1 375 <&cpu60_intc 11>, <&cpu60_intc 9>,
495 <&cpu61_intc 1 376 <&cpu61_intc 11>, <&cpu61_intc 9>,
496 <&cpu62_intc 1 377 <&cpu62_intc 11>, <&cpu62_intc 9>,
497 <&cpu63_intc 1 378 <&cpu63_intc 11>, <&cpu63_intc 9>;
498 riscv,ndev = <224>; 379 riscv,ndev = <224>;
499 }; 380 };
500 381
501 rstgen: reset-controller@70300 382 rstgen: reset-controller@7030013000 {
502 compatible = "sophgo,s 383 compatible = "sophgo,sg2042-reset";
503 reg = <0x00000070 0x30 384 reg = <0x00000070 0x30013000 0x00000000 0x0000000c>;
504 #reset-cells = <1>; 385 #reset-cells = <1>;
505 }; 386 };
506 387
507 uart0: serial@7040000000 { 388 uart0: serial@7040000000 {
508 compatible = "snps,dw- 389 compatible = "snps,dw-apb-uart";
509 reg = <0x00000070 0x40 390 reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
>> 391 interrupt-parent = <&intc>;
510 interrupts = <112 IRQ_ 392 interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
511 clock-frequency = <500 393 clock-frequency = <500000000>;
512 clocks = <&clkgen GATE 394 clocks = <&clkgen GATE_CLK_UART_500M>,
513 <&clkgen GATE 395 <&clkgen GATE_CLK_APB_UART>;
514 clock-names = "baudclk 396 clock-names = "baudclk", "apb_pclk";
515 reg-shift = <2>; 397 reg-shift = <2>;
516 reg-io-width = <4>; 398 reg-io-width = <4>;
517 resets = <&rstgen RST_ 399 resets = <&rstgen RST_UART0>;
518 status = "disabled"; <<
519 }; <<
520 <<
521 emmc: mmc@704002a000 { <<
522 compatible = "sophgo,s <<
523 reg = <0x70 0x4002a000 <<
524 interrupt-parent = <&i <<
525 interrupts = <134 IRQ_ <<
526 clocks = <&clkgen GATE <<
527 <&clkgen GATE <<
528 <&clkgen GATE <<
529 clock-names = "core", <<
530 "bus", <<
531 "timer"; <<
532 status = "disabled"; <<
533 }; <<
534 <<
535 sd: mmc@704002b000 { <<
536 compatible = "sophgo,s <<
537 reg = <0x70 0x4002b000 <<
538 interrupt-parent = <&i <<
539 interrupts = <136 IRQ_ <<
540 clocks = <&clkgen GATE <<
541 <&clkgen GATE <<
542 <&clkgen GATE <<
543 clock-names = "core", <<
544 "bus", <<
545 "timer"; <<
546 status = "disabled"; 400 status = "disabled";
547 }; 401 };
548 }; 402 };
549 }; 403 };
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