1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /*
3 * Copyright (C) 2021 StarFive Technology Co.,
4 * Copyright (C) 2021 Emil Renner Berthing <ker
5 */
6
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h>
10
11 / {
12 compatible = "starfive,jh7100";
13 #address-cells = <2>;
14 #size-cells = <2>;
15
16 cpus: cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 U74_0: cpu@0 {
21 compatible = "sifive,u
22 reg = <0>;
23 d-cache-block-size = <
24 d-cache-sets = <64>;
25 d-cache-size = <32768>
26 d-tlb-sets = <1>;
27 d-tlb-size = <32>;
28 device_type = "cpu";
29 i-cache-block-size = <
30 i-cache-sets = <64>;
31 i-cache-size = <32768>
32 i-tlb-sets = <1>;
33 i-tlb-size = <32>;
34 mmu-type = "riscv,sv39
35 next-level-cache = <&c
36 riscv,isa = "rv64imafd
37 riscv,isa-base = "rv64
38 riscv,isa-extensions =
39
40 tlb-split;
41
42 cpu0_intc: interrupt-c
43 compatible = "
44 interrupt-cont
45 #interrupt-cel
46 };
47 };
48
49 U74_1: cpu@1 {
50 compatible = "sifive,u
51 reg = <1>;
52 d-cache-block-size = <
53 d-cache-sets = <64>;
54 d-cache-size = <32768>
55 d-tlb-sets = <1>;
56 d-tlb-size = <32>;
57 device_type = "cpu";
58 i-cache-block-size = <
59 i-cache-sets = <64>;
60 i-cache-size = <32768>
61 i-tlb-sets = <1>;
62 i-tlb-size = <32>;
63 mmu-type = "riscv,sv39
64 next-level-cache = <&c
65 riscv,isa = "rv64imafd
66 riscv,isa-base = "rv64
67 riscv,isa-extensions =
68
69 tlb-split;
70
71 cpu1_intc: interrupt-c
72 compatible = "
73 interrupt-cont
74 #interrupt-cel
75 };
76 };
77
78 cpu-map {
79 cluster0 {
80 core0 {
81 cpu =
82 };
83
84 core1 {
85 cpu =
86 };
87 };
88 };
89 };
90
91 thermal-zones {
92 cpu-thermal {
93 polling-delay-passive
94 polling-delay = <15000
95
96 thermal-sensors = <&sf
97
98 trips {
99 cpu-alert0 {
100 /* mil
101 temper
102 hyster
103 type =
104 };
105
106 cpu-crit {
107 /* mil
108 temper
109 hyster
110 type =
111 };
112 };
113 };
114 };
115
116 osc_sys: osc-sys {
117 compatible = "fixed-clock";
118 #clock-cells = <0>;
119 clock-output-names = "osc_sys"
120 /* This value must be overridd
121 clock-frequency = <0>;
122 };
123
124 osc_aud: osc-aud {
125 compatible = "fixed-clock";
126 #clock-cells = <0>;
127 clock-output-names = "osc_aud"
128 /* This value must be overridd
129 clock-frequency = <0>;
130 };
131
132 gmac_rmii_ref: gmac-rmii-ref {
133 compatible = "fixed-clock";
134 #clock-cells = <0>;
135 clock-output-names = "gmac_rmi
136 /* Should be overridden by the
137 clock-frequency = <0>;
138 };
139
140 gmac_gr_mii_rxclk: gmac-gr-mii-rxclk {
141 compatible = "fixed-clock";
142 #clock-cells = <0>;
143 clock-output-names = "gmac_gr_
144 /* Should be overridden by the
145 clock-frequency = <0>;
146 };
147
148 soc {
149 compatible = "simple-bus";
150 interrupt-parent = <&plic>;
151 #address-cells = <2>;
152 #size-cells = <2>;
153 dma-noncoherent;
154 ranges;
155
156 clint: clint@2000000 {
157 compatible = "starfive
158 reg = <0x0 0x2000000 0
159 interrupts-extended =
160
161 };
162
163 ccache: cache-controller@20100
164 compatible = "starfive
165 reg = <0x0 0x2010000 0
166 interrupts = <128>, <1
167 cache-block-size = <64
168 cache-level = <2>;
169 cache-sets = <2048>;
170 cache-size = <2097152>
171 cache-unified;
172 };
173
174 plic: interrupt-controller@c00
175 compatible = "starfive
176 reg = <0x0 0xc000000 0
177 interrupts-extended =
178
179 interrupt-controller;
180 #address-cells = <0>;
181 #interrupt-cells = <1>
182 riscv,ndev = <133>;
183 };
184
185 sdio0: mmc@10000000 {
186 compatible = "snps,dw-
187 reg = <0x0 0x10000000
188 clocks = <&clkgen JH71
189 <&clkgen JH71
190 clock-names = "biu", "
191 interrupts = <4>;
192 data-addr = <0>;
193 fifo-depth = <32>;
194 fifo-watermark-aligned
195 status = "disabled";
196 };
197
198 sdio1: mmc@10010000 {
199 compatible = "snps,dw-
200 reg = <0x0 0x10010000
201 clocks = <&clkgen JH71
202 <&clkgen JH71
203 clock-names = "biu", "
204 interrupts = <5>;
205 data-addr = <0>;
206 fifo-depth = <32>;
207 fifo-watermark-aligned
208 status = "disabled";
209 };
210
211 gmac: ethernet@10020000 {
212 compatible = "starfive
213 reg = <0x0 0x10020000
214 clocks = <&clkgen JH71
215 <&clkgen JH71
216 <&clkgen JH71
217 <&clkgen JH71
218 <&clkgen JH71
219 clock-names = "stmmace
220 resets = <&rstgen JH71
221 reset-names = "ahb";
222 interrupts = <6>, <7>;
223 interrupt-names = "mac
224 max-frame-size = <9000
225 snps,multicast-filter-
226 snps,perfect-filter-en
227 starfive,syscon = <&sy
228 rx-fifo-depth = <32768
229 tx-fifo-depth = <16384
230 snps,axi-config = <&st
231 snps,fixed-burst;
232 snps,force_thresh_dma_
233 status = "disabled";
234
235 stmmac_axi_setup: stmm
236 snps,wr_osr_lm
237 snps,rd_osr_lm
238 snps,blen = <2
239 };
240 };
241
242 clkgen: clock-controller@11800
243 compatible = "starfive
244 reg = <0x0 0x11800000
245 clocks = <&osc_sys>, <
246 clock-names = "osc_sys
247 #clock-cells = <1>;
248 };
249
250 rstgen: reset-controller@11840
251 compatible = "starfive
252 reg = <0x0 0x11840000
253 #reset-cells = <1>;
254 };
255
256 sysmain: syscon@11850000 {
257 compatible = "starfive
258 reg = <0x0 0x11850000
259 };
260
261 i2c0: i2c@118b0000 {
262 compatible = "snps,des
263 reg = <0x0 0x118b0000
264 clocks = <&clkgen JH71
265 <&clkgen JH71
266 clock-names = "ref", "
267 resets = <&rstgen JH71
268 interrupts = <96>;
269 #address-cells = <1>;
270 #size-cells = <0>;
271 status = "disabled";
272 };
273
274 i2c1: i2c@118c0000 {
275 compatible = "snps,des
276 reg = <0x0 0x118c0000
277 clocks = <&clkgen JH71
278 <&clkgen JH71
279 clock-names = "ref", "
280 resets = <&rstgen JH71
281 interrupts = <97>;
282 #address-cells = <1>;
283 #size-cells = <0>;
284 status = "disabled";
285 };
286
287 gpio: pinctrl@11910000 {
288 compatible = "starfive
289 reg = <0x0 0x11910000
290 <0x0 0x11858000
291 reg-names = "gpio", "p
292 clocks = <&clkgen JH71
293 resets = <&rstgen JH71
294 interrupts = <32>;
295 gpio-controller;
296 #gpio-cells = <2>;
297 interrupt-controller;
298 #interrupt-cells = <2>
299 };
300
301 uart2: serial@12430000 {
302 compatible = "starfive
303 reg = <0x0 0x12430000
304 clocks = <&clkgen JH71
305 <&clkgen JH71
306 clock-names = "baudclk
307 resets = <&rstgen JH71
308 interrupts = <72>;
309 reg-io-width = <4>;
310 reg-shift = <2>;
311 status = "disabled";
312 };
313
314 uart3: serial@12440000 {
315 compatible = "starfive
316 reg = <0x0 0x12440000
317 clocks = <&clkgen JH71
318 <&clkgen JH71
319 clock-names = "baudclk
320 resets = <&rstgen JH71
321 interrupts = <73>;
322 reg-io-width = <4>;
323 reg-shift = <2>;
324 status = "disabled";
325 };
326
327 i2c2: i2c@12450000 {
328 compatible = "snps,des
329 reg = <0x0 0x12450000
330 clocks = <&clkgen JH71
331 <&clkgen JH71
332 clock-names = "ref", "
333 resets = <&rstgen JH71
334 interrupts = <74>;
335 #address-cells = <1>;
336 #size-cells = <0>;
337 status = "disabled";
338 };
339
340 i2c3: i2c@12460000 {
341 compatible = "snps,des
342 reg = <0x0 0x12460000
343 clocks = <&clkgen JH71
344 <&clkgen JH71
345 clock-names = "ref", "
346 resets = <&rstgen JH71
347 interrupts = <75>;
348 #address-cells = <1>;
349 #size-cells = <0>;
350 status = "disabled";
351 };
352
353 watchdog@12480000 {
354 compatible = "starfive
355 reg = <0x0 0x12480000
356 clocks = <&clkgen JH71
357 <&clkgen JH71
358 clock-names = "apb", "
359 resets = <&rstgen JH71
360 <&rstgen JH71
361 };
362
363 pwm: pwm@12490000 {
364 compatible = "starfive
365 reg = <0x0 0x12490000
366 clocks = <&clkgen JH71
367 resets = <&rstgen JH71
368 #pwm-cells = <3>;
369 status = "disabled";
370 };
371
372 sfctemp: temperature-sensor@12
373 compatible = "starfive
374 reg = <0x0 0x124a0000
375 clocks = <&clkgen JH71
376 <&clkgen JH71
377 clock-names = "sense",
378 resets = <&rstgen JH71
379 <&rstgen JH71
380 reset-names = "sense",
381 #thermal-sensor-cells
382 };
383 };
384 };
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