1 // SPDX-License-Identifier: GPL-2.0 OR MIT 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /* 2 /*
3 * Copyright (C) 2021 StarFive Technology Co., 3 * Copyright (C) 2021 StarFive Technology Co., Ltd.
4 * Copyright (C) 2021 Emil Renner Berthing <ker 4 * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
5 */ 5 */
6 6
7 /dts-v1/; 7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h> 8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h> 9 #include <dt-bindings/reset/starfive-jh7100.h>
10 10
11 / { 11 / {
12 compatible = "starfive,jh7100"; 12 compatible = "starfive,jh7100";
13 #address-cells = <2>; 13 #address-cells = <2>;
14 #size-cells = <2>; 14 #size-cells = <2>;
15 15
16 cpus: cpus { !! 16 cpus {
17 #address-cells = <1>; 17 #address-cells = <1>;
18 #size-cells = <0>; 18 #size-cells = <0>;
19 19
20 U74_0: cpu@0 { 20 U74_0: cpu@0 {
21 compatible = "sifive,u 21 compatible = "sifive,u74-mc", "riscv";
22 reg = <0>; 22 reg = <0>;
23 d-cache-block-size = < 23 d-cache-block-size = <64>;
24 d-cache-sets = <64>; 24 d-cache-sets = <64>;
25 d-cache-size = <32768> 25 d-cache-size = <32768>;
26 d-tlb-sets = <1>; 26 d-tlb-sets = <1>;
27 d-tlb-size = <32>; 27 d-tlb-size = <32>;
28 device_type = "cpu"; 28 device_type = "cpu";
29 i-cache-block-size = < 29 i-cache-block-size = <64>;
30 i-cache-sets = <64>; 30 i-cache-sets = <64>;
31 i-cache-size = <32768> 31 i-cache-size = <32768>;
32 i-tlb-sets = <1>; 32 i-tlb-sets = <1>;
33 i-tlb-size = <32>; 33 i-tlb-size = <32>;
34 mmu-type = "riscv,sv39 34 mmu-type = "riscv,sv39";
35 next-level-cache = <&c <<
36 riscv,isa = "rv64imafd 35 riscv,isa = "rv64imafdc";
37 riscv,isa-base = "rv64 <<
38 riscv,isa-extensions = <<
39 <<
40 tlb-split; 36 tlb-split;
41 37
42 cpu0_intc: interrupt-c 38 cpu0_intc: interrupt-controller {
43 compatible = " 39 compatible = "riscv,cpu-intc";
44 interrupt-cont 40 interrupt-controller;
45 #interrupt-cel 41 #interrupt-cells = <1>;
46 }; 42 };
47 }; 43 };
48 44
49 U74_1: cpu@1 { 45 U74_1: cpu@1 {
50 compatible = "sifive,u 46 compatible = "sifive,u74-mc", "riscv";
51 reg = <1>; 47 reg = <1>;
52 d-cache-block-size = < 48 d-cache-block-size = <64>;
53 d-cache-sets = <64>; 49 d-cache-sets = <64>;
54 d-cache-size = <32768> 50 d-cache-size = <32768>;
55 d-tlb-sets = <1>; 51 d-tlb-sets = <1>;
56 d-tlb-size = <32>; 52 d-tlb-size = <32>;
57 device_type = "cpu"; 53 device_type = "cpu";
58 i-cache-block-size = < 54 i-cache-block-size = <64>;
59 i-cache-sets = <64>; 55 i-cache-sets = <64>;
60 i-cache-size = <32768> 56 i-cache-size = <32768>;
61 i-tlb-sets = <1>; 57 i-tlb-sets = <1>;
62 i-tlb-size = <32>; 58 i-tlb-size = <32>;
63 mmu-type = "riscv,sv39 59 mmu-type = "riscv,sv39";
64 next-level-cache = <&c <<
65 riscv,isa = "rv64imafd 60 riscv,isa = "rv64imafdc";
66 riscv,isa-base = "rv64 <<
67 riscv,isa-extensions = <<
68 <<
69 tlb-split; 61 tlb-split;
70 62
71 cpu1_intc: interrupt-c 63 cpu1_intc: interrupt-controller {
72 compatible = " 64 compatible = "riscv,cpu-intc";
73 interrupt-cont 65 interrupt-controller;
74 #interrupt-cel 66 #interrupt-cells = <1>;
75 }; 67 };
76 }; 68 };
77 69
78 cpu-map { 70 cpu-map {
79 cluster0 { 71 cluster0 {
80 core0 { 72 core0 {
81 cpu = 73 cpu = <&U74_0>;
82 }; 74 };
83 75
84 core1 { 76 core1 {
85 cpu = 77 cpu = <&U74_1>;
86 }; 78 };
87 }; 79 };
88 }; 80 };
89 }; 81 };
90 82
91 thermal-zones { 83 thermal-zones {
92 cpu-thermal { 84 cpu-thermal {
93 polling-delay-passive 85 polling-delay-passive = <250>;
94 polling-delay = <15000 86 polling-delay = <15000>;
95 87
96 thermal-sensors = <&sf 88 thermal-sensors = <&sfctemp>;
97 89
98 trips { 90 trips {
99 cpu-alert0 { !! 91 cpu_alert0 {
100 /* mil 92 /* milliCelsius */
101 temper 93 temperature = <75000>;
102 hyster 94 hysteresis = <2000>;
103 type = 95 type = "passive";
104 }; 96 };
105 97
106 cpu-crit { !! 98 cpu_crit {
107 /* mil 99 /* milliCelsius */
108 temper 100 temperature = <90000>;
109 hyster 101 hysteresis = <2000>;
110 type = 102 type = "critical";
111 }; 103 };
112 }; 104 };
113 }; 105 };
114 }; 106 };
115 107
116 osc_sys: osc-sys { !! 108 osc_sys: osc_sys {
117 compatible = "fixed-clock"; 109 compatible = "fixed-clock";
118 #clock-cells = <0>; 110 #clock-cells = <0>;
119 clock-output-names = "osc_sys" <<
120 /* This value must be overridd 111 /* This value must be overridden by the board */
121 clock-frequency = <0>; 112 clock-frequency = <0>;
122 }; 113 };
123 114
124 osc_aud: osc-aud { !! 115 osc_aud: osc_aud {
125 compatible = "fixed-clock"; 116 compatible = "fixed-clock";
126 #clock-cells = <0>; 117 #clock-cells = <0>;
127 clock-output-names = "osc_aud" <<
128 /* This value must be overridd 118 /* This value must be overridden by the board */
129 clock-frequency = <0>; 119 clock-frequency = <0>;
130 }; 120 };
131 121
132 gmac_rmii_ref: gmac-rmii-ref { !! 122 gmac_rmii_ref: gmac_rmii_ref {
133 compatible = "fixed-clock"; 123 compatible = "fixed-clock";
134 #clock-cells = <0>; 124 #clock-cells = <0>;
135 clock-output-names = "gmac_rmi <<
136 /* Should be overridden by the 125 /* Should be overridden by the board when needed */
137 clock-frequency = <0>; 126 clock-frequency = <0>;
138 }; 127 };
139 128
140 gmac_gr_mii_rxclk: gmac-gr-mii-rxclk { !! 129 gmac_gr_mii_rxclk: gmac_gr_mii_rxclk {
141 compatible = "fixed-clock"; 130 compatible = "fixed-clock";
142 #clock-cells = <0>; 131 #clock-cells = <0>;
143 clock-output-names = "gmac_gr_ <<
144 /* Should be overridden by the 132 /* Should be overridden by the board when needed */
145 clock-frequency = <0>; 133 clock-frequency = <0>;
146 }; 134 };
147 135
148 soc { 136 soc {
149 compatible = "simple-bus"; 137 compatible = "simple-bus";
150 interrupt-parent = <&plic>; 138 interrupt-parent = <&plic>;
151 #address-cells = <2>; 139 #address-cells = <2>;
152 #size-cells = <2>; 140 #size-cells = <2>;
153 dma-noncoherent; <<
154 ranges; 141 ranges;
155 142
156 clint: clint@2000000 { 143 clint: clint@2000000 {
157 compatible = "starfive 144 compatible = "starfive,jh7100-clint", "sifive,clint0";
158 reg = <0x0 0x2000000 0 145 reg = <0x0 0x2000000 0x0 0x10000>;
159 interrupts-extended = !! 146 interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
160 !! 147 &cpu1_intc 3 &cpu1_intc 7>;
161 }; <<
162 <<
163 ccache: cache-controller@20100 <<
164 compatible = "starfive <<
165 reg = <0x0 0x2010000 0 <<
166 interrupts = <128>, <1 <<
167 cache-block-size = <64 <<
168 cache-level = <2>; <<
169 cache-sets = <2048>; <<
170 cache-size = <2097152> <<
171 cache-unified; <<
172 }; 148 };
173 149
174 plic: interrupt-controller@c00 150 plic: interrupt-controller@c000000 {
175 compatible = "starfive 151 compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
176 reg = <0x0 0xc000000 0 152 reg = <0x0 0xc000000 0x0 0x4000000>;
177 interrupts-extended = !! 153 interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9
178 !! 154 &cpu1_intc 11 &cpu1_intc 9>;
179 interrupt-controller; 155 interrupt-controller;
180 #address-cells = <0>; 156 #address-cells = <0>;
181 #interrupt-cells = <1> 157 #interrupt-cells = <1>;
182 riscv,ndev = <133>; 158 riscv,ndev = <133>;
183 }; 159 };
184 160
185 sdio0: mmc@10000000 { <<
186 compatible = "snps,dw- <<
187 reg = <0x0 0x10000000 <<
188 clocks = <&clkgen JH71 <<
189 <&clkgen JH71 <<
190 clock-names = "biu", " <<
191 interrupts = <4>; <<
192 data-addr = <0>; <<
193 fifo-depth = <32>; <<
194 fifo-watermark-aligned <<
195 status = "disabled"; <<
196 }; <<
197 <<
198 sdio1: mmc@10010000 { <<
199 compatible = "snps,dw- <<
200 reg = <0x0 0x10010000 <<
201 clocks = <&clkgen JH71 <<
202 <&clkgen JH71 <<
203 clock-names = "biu", " <<
204 interrupts = <5>; <<
205 data-addr = <0>; <<
206 fifo-depth = <32>; <<
207 fifo-watermark-aligned <<
208 status = "disabled"; <<
209 }; <<
210 <<
211 gmac: ethernet@10020000 { <<
212 compatible = "starfive <<
213 reg = <0x0 0x10020000 <<
214 clocks = <&clkgen JH71 <<
215 <&clkgen JH71 <<
216 <&clkgen JH71 <<
217 <&clkgen JH71 <<
218 <&clkgen JH71 <<
219 clock-names = "stmmace <<
220 resets = <&rstgen JH71 <<
221 reset-names = "ahb"; <<
222 interrupts = <6>, <7>; <<
223 interrupt-names = "mac <<
224 max-frame-size = <9000 <<
225 snps,multicast-filter- <<
226 snps,perfect-filter-en <<
227 starfive,syscon = <&sy <<
228 rx-fifo-depth = <32768 <<
229 tx-fifo-depth = <16384 <<
230 snps,axi-config = <&st <<
231 snps,fixed-burst; <<
232 snps,force_thresh_dma_ <<
233 status = "disabled"; <<
234 <<
235 stmmac_axi_setup: stmm <<
236 snps,wr_osr_lm <<
237 snps,rd_osr_lm <<
238 snps,blen = <2 <<
239 }; <<
240 }; <<
241 <<
242 clkgen: clock-controller@11800 161 clkgen: clock-controller@11800000 {
243 compatible = "starfive 162 compatible = "starfive,jh7100-clkgen";
244 reg = <0x0 0x11800000 163 reg = <0x0 0x11800000 0x0 0x10000>;
245 clocks = <&osc_sys>, < 164 clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>;
246 clock-names = "osc_sys 165 clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk";
247 #clock-cells = <1>; 166 #clock-cells = <1>;
248 }; 167 };
249 168
250 rstgen: reset-controller@11840 169 rstgen: reset-controller@11840000 {
251 compatible = "starfive 170 compatible = "starfive,jh7100-reset";
252 reg = <0x0 0x11840000 171 reg = <0x0 0x11840000 0x0 0x10000>;
253 #reset-cells = <1>; 172 #reset-cells = <1>;
254 }; 173 };
255 174
256 sysmain: syscon@11850000 { <<
257 compatible = "starfive <<
258 reg = <0x0 0x11850000 <<
259 }; <<
260 <<
261 i2c0: i2c@118b0000 { 175 i2c0: i2c@118b0000 {
262 compatible = "snps,des 176 compatible = "snps,designware-i2c";
263 reg = <0x0 0x118b0000 177 reg = <0x0 0x118b0000 0x0 0x10000>;
264 clocks = <&clkgen JH71 178 clocks = <&clkgen JH7100_CLK_I2C0_CORE>,
265 <&clkgen JH71 179 <&clkgen JH7100_CLK_I2C0_APB>;
266 clock-names = "ref", " 180 clock-names = "ref", "pclk";
267 resets = <&rstgen JH71 181 resets = <&rstgen JH7100_RSTN_I2C0_APB>;
268 interrupts = <96>; 182 interrupts = <96>;
269 #address-cells = <1>; 183 #address-cells = <1>;
270 #size-cells = <0>; 184 #size-cells = <0>;
271 status = "disabled"; 185 status = "disabled";
272 }; 186 };
273 187
274 i2c1: i2c@118c0000 { 188 i2c1: i2c@118c0000 {
275 compatible = "snps,des 189 compatible = "snps,designware-i2c";
276 reg = <0x0 0x118c0000 190 reg = <0x0 0x118c0000 0x0 0x10000>;
277 clocks = <&clkgen JH71 191 clocks = <&clkgen JH7100_CLK_I2C1_CORE>,
278 <&clkgen JH71 192 <&clkgen JH7100_CLK_I2C1_APB>;
279 clock-names = "ref", " 193 clock-names = "ref", "pclk";
280 resets = <&rstgen JH71 194 resets = <&rstgen JH7100_RSTN_I2C1_APB>;
281 interrupts = <97>; 195 interrupts = <97>;
282 #address-cells = <1>; 196 #address-cells = <1>;
283 #size-cells = <0>; 197 #size-cells = <0>;
284 status = "disabled"; 198 status = "disabled";
285 }; 199 };
286 200
287 gpio: pinctrl@11910000 { 201 gpio: pinctrl@11910000 {
288 compatible = "starfive 202 compatible = "starfive,jh7100-pinctrl";
289 reg = <0x0 0x11910000 203 reg = <0x0 0x11910000 0x0 0x10000>,
290 <0x0 0x11858000 204 <0x0 0x11858000 0x0 0x1000>;
291 reg-names = "gpio", "p 205 reg-names = "gpio", "padctl";
292 clocks = <&clkgen JH71 206 clocks = <&clkgen JH7100_CLK_GPIO_APB>;
293 resets = <&rstgen JH71 207 resets = <&rstgen JH7100_RSTN_GPIO_APB>;
294 interrupts = <32>; 208 interrupts = <32>;
295 gpio-controller; 209 gpio-controller;
296 #gpio-cells = <2>; 210 #gpio-cells = <2>;
297 interrupt-controller; 211 interrupt-controller;
298 #interrupt-cells = <2> 212 #interrupt-cells = <2>;
299 }; 213 };
300 214
301 uart2: serial@12430000 { 215 uart2: serial@12430000 {
302 compatible = "starfive 216 compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
303 reg = <0x0 0x12430000 217 reg = <0x0 0x12430000 0x0 0x10000>;
304 clocks = <&clkgen JH71 218 clocks = <&clkgen JH7100_CLK_UART2_CORE>,
305 <&clkgen JH71 219 <&clkgen JH7100_CLK_UART2_APB>;
306 clock-names = "baudclk 220 clock-names = "baudclk", "apb_pclk";
307 resets = <&rstgen JH71 221 resets = <&rstgen JH7100_RSTN_UART2_APB>;
308 interrupts = <72>; 222 interrupts = <72>;
309 reg-io-width = <4>; 223 reg-io-width = <4>;
310 reg-shift = <2>; 224 reg-shift = <2>;
311 status = "disabled"; 225 status = "disabled";
312 }; 226 };
313 227
314 uart3: serial@12440000 { 228 uart3: serial@12440000 {
315 compatible = "starfive 229 compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
316 reg = <0x0 0x12440000 230 reg = <0x0 0x12440000 0x0 0x10000>;
317 clocks = <&clkgen JH71 231 clocks = <&clkgen JH7100_CLK_UART3_CORE>,
318 <&clkgen JH71 232 <&clkgen JH7100_CLK_UART3_APB>;
319 clock-names = "baudclk 233 clock-names = "baudclk", "apb_pclk";
320 resets = <&rstgen JH71 234 resets = <&rstgen JH7100_RSTN_UART3_APB>;
321 interrupts = <73>; 235 interrupts = <73>;
322 reg-io-width = <4>; 236 reg-io-width = <4>;
323 reg-shift = <2>; 237 reg-shift = <2>;
324 status = "disabled"; 238 status = "disabled";
325 }; 239 };
326 240
327 i2c2: i2c@12450000 { 241 i2c2: i2c@12450000 {
328 compatible = "snps,des 242 compatible = "snps,designware-i2c";
329 reg = <0x0 0x12450000 243 reg = <0x0 0x12450000 0x0 0x10000>;
330 clocks = <&clkgen JH71 244 clocks = <&clkgen JH7100_CLK_I2C2_CORE>,
331 <&clkgen JH71 245 <&clkgen JH7100_CLK_I2C2_APB>;
332 clock-names = "ref", " 246 clock-names = "ref", "pclk";
333 resets = <&rstgen JH71 247 resets = <&rstgen JH7100_RSTN_I2C2_APB>;
334 interrupts = <74>; 248 interrupts = <74>;
335 #address-cells = <1>; 249 #address-cells = <1>;
336 #size-cells = <0>; 250 #size-cells = <0>;
337 status = "disabled"; 251 status = "disabled";
338 }; 252 };
339 253
340 i2c3: i2c@12460000 { 254 i2c3: i2c@12460000 {
341 compatible = "snps,des 255 compatible = "snps,designware-i2c";
342 reg = <0x0 0x12460000 256 reg = <0x0 0x12460000 0x0 0x10000>;
343 clocks = <&clkgen JH71 257 clocks = <&clkgen JH7100_CLK_I2C3_CORE>,
344 <&clkgen JH71 258 <&clkgen JH7100_CLK_I2C3_APB>;
345 clock-names = "ref", " 259 clock-names = "ref", "pclk";
346 resets = <&rstgen JH71 260 resets = <&rstgen JH7100_RSTN_I2C3_APB>;
347 interrupts = <75>; 261 interrupts = <75>;
348 #address-cells = <1>; 262 #address-cells = <1>;
349 #size-cells = <0>; 263 #size-cells = <0>;
350 status = "disabled"; 264 status = "disabled";
351 }; 265 };
352 266
353 watchdog@12480000 { 267 watchdog@12480000 {
354 compatible = "starfive 268 compatible = "starfive,jh7100-wdt";
355 reg = <0x0 0x12480000 269 reg = <0x0 0x12480000 0x0 0x10000>;
356 clocks = <&clkgen JH71 270 clocks = <&clkgen JH7100_CLK_WDTIMER_APB>,
357 <&clkgen JH71 271 <&clkgen JH7100_CLK_WDT_CORE>;
358 clock-names = "apb", " 272 clock-names = "apb", "core";
359 resets = <&rstgen JH71 273 resets = <&rstgen JH7100_RSTN_WDTIMER_APB>,
360 <&rstgen JH71 274 <&rstgen JH7100_RSTN_WDT>;
361 }; <<
362 <<
363 pwm: pwm@12490000 { <<
364 compatible = "starfive <<
365 reg = <0x0 0x12490000 <<
366 clocks = <&clkgen JH71 <<
367 resets = <&rstgen JH71 <<
368 #pwm-cells = <3>; <<
369 status = "disabled"; <<
370 }; 275 };
371 276
372 sfctemp: temperature-sensor@12 277 sfctemp: temperature-sensor@124a0000 {
373 compatible = "starfive 278 compatible = "starfive,jh7100-temp";
374 reg = <0x0 0x124a0000 279 reg = <0x0 0x124a0000 0x0 0x10000>;
375 clocks = <&clkgen JH71 280 clocks = <&clkgen JH7100_CLK_TEMP_SENSE>,
376 <&clkgen JH71 281 <&clkgen JH7100_CLK_TEMP_APB>;
377 clock-names = "sense", 282 clock-names = "sense", "bus";
378 resets = <&rstgen JH71 283 resets = <&rstgen JH7100_RSTN_TEMP_SENSE>,
379 <&rstgen JH71 284 <&rstgen JH7100_RSTN_TEMP_APB>;
380 reset-names = "sense", 285 reset-names = "sense", "bus";
381 #thermal-sensor-cells 286 #thermal-sensor-cells = <0>;
382 }; 287 };
383 }; 288 };
384 }; 289 };
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