1 // SPDX-License-Identifier: GPL-2.0 OR MIT 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /* 2 /*
3 * Copyright (C) 2021 StarFive Technology Co., 3 * Copyright (C) 2021 StarFive Technology Co., Ltd.
4 * Copyright (C) 2021 Emil Renner Berthing <ker 4 * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
5 */ 5 */
6 6
7 /dts-v1/; 7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h> 8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h> 9 #include <dt-bindings/reset/starfive-jh7100.h>
10 10
11 / { 11 / {
12 compatible = "starfive,jh7100"; 12 compatible = "starfive,jh7100";
13 #address-cells = <2>; 13 #address-cells = <2>;
14 #size-cells = <2>; 14 #size-cells = <2>;
15 15
16 cpus: cpus { !! 16 cpus {
17 #address-cells = <1>; 17 #address-cells = <1>;
18 #size-cells = <0>; 18 #size-cells = <0>;
19 19
20 U74_0: cpu@0 { 20 U74_0: cpu@0 {
21 compatible = "sifive,u 21 compatible = "sifive,u74-mc", "riscv";
22 reg = <0>; 22 reg = <0>;
23 d-cache-block-size = < 23 d-cache-block-size = <64>;
24 d-cache-sets = <64>; 24 d-cache-sets = <64>;
25 d-cache-size = <32768> 25 d-cache-size = <32768>;
26 d-tlb-sets = <1>; 26 d-tlb-sets = <1>;
27 d-tlb-size = <32>; 27 d-tlb-size = <32>;
28 device_type = "cpu"; 28 device_type = "cpu";
29 i-cache-block-size = < 29 i-cache-block-size = <64>;
30 i-cache-sets = <64>; 30 i-cache-sets = <64>;
31 i-cache-size = <32768> 31 i-cache-size = <32768>;
32 i-tlb-sets = <1>; 32 i-tlb-sets = <1>;
33 i-tlb-size = <32>; 33 i-tlb-size = <32>;
34 mmu-type = "riscv,sv39 34 mmu-type = "riscv,sv39";
35 next-level-cache = <&c <<
36 riscv,isa = "rv64imafd 35 riscv,isa = "rv64imafdc";
37 riscv,isa-base = "rv64 36 riscv,isa-base = "rv64i";
38 riscv,isa-extensions = 37 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
39 38 "zifencei", "zihpm";
40 tlb-split; 39 tlb-split;
41 40
42 cpu0_intc: interrupt-c 41 cpu0_intc: interrupt-controller {
43 compatible = " 42 compatible = "riscv,cpu-intc";
44 interrupt-cont 43 interrupt-controller;
45 #interrupt-cel 44 #interrupt-cells = <1>;
46 }; 45 };
47 }; 46 };
48 47
49 U74_1: cpu@1 { 48 U74_1: cpu@1 {
50 compatible = "sifive,u 49 compatible = "sifive,u74-mc", "riscv";
51 reg = <1>; 50 reg = <1>;
52 d-cache-block-size = < 51 d-cache-block-size = <64>;
53 d-cache-sets = <64>; 52 d-cache-sets = <64>;
54 d-cache-size = <32768> 53 d-cache-size = <32768>;
55 d-tlb-sets = <1>; 54 d-tlb-sets = <1>;
56 d-tlb-size = <32>; 55 d-tlb-size = <32>;
57 device_type = "cpu"; 56 device_type = "cpu";
58 i-cache-block-size = < 57 i-cache-block-size = <64>;
59 i-cache-sets = <64>; 58 i-cache-sets = <64>;
60 i-cache-size = <32768> 59 i-cache-size = <32768>;
61 i-tlb-sets = <1>; 60 i-tlb-sets = <1>;
62 i-tlb-size = <32>; 61 i-tlb-size = <32>;
63 mmu-type = "riscv,sv39 62 mmu-type = "riscv,sv39";
64 next-level-cache = <&c <<
65 riscv,isa = "rv64imafd 63 riscv,isa = "rv64imafdc";
66 riscv,isa-base = "rv64 64 riscv,isa-base = "rv64i";
67 riscv,isa-extensions = 65 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
68 66 "zifencei", "zihpm";
69 tlb-split; 67 tlb-split;
70 68
71 cpu1_intc: interrupt-c 69 cpu1_intc: interrupt-controller {
72 compatible = " 70 compatible = "riscv,cpu-intc";
73 interrupt-cont 71 interrupt-controller;
74 #interrupt-cel 72 #interrupt-cells = <1>;
75 }; 73 };
76 }; 74 };
77 75
78 cpu-map { 76 cpu-map {
79 cluster0 { 77 cluster0 {
80 core0 { 78 core0 {
81 cpu = 79 cpu = <&U74_0>;
82 }; 80 };
83 81
84 core1 { 82 core1 {
85 cpu = 83 cpu = <&U74_1>;
86 }; 84 };
87 }; 85 };
88 }; 86 };
89 }; 87 };
90 88
91 thermal-zones { 89 thermal-zones {
92 cpu-thermal { 90 cpu-thermal {
93 polling-delay-passive 91 polling-delay-passive = <250>;
94 polling-delay = <15000 92 polling-delay = <15000>;
95 93
96 thermal-sensors = <&sf 94 thermal-sensors = <&sfctemp>;
97 95
98 trips { 96 trips {
99 cpu-alert0 { !! 97 cpu_alert0 {
100 /* mil 98 /* milliCelsius */
101 temper 99 temperature = <75000>;
102 hyster 100 hysteresis = <2000>;
103 type = 101 type = "passive";
104 }; 102 };
105 103
106 cpu-crit { !! 104 cpu_crit {
107 /* mil 105 /* milliCelsius */
108 temper 106 temperature = <90000>;
109 hyster 107 hysteresis = <2000>;
110 type = 108 type = "critical";
111 }; 109 };
112 }; 110 };
113 }; 111 };
114 }; 112 };
115 113
116 osc_sys: osc-sys { !! 114 osc_sys: osc_sys {
117 compatible = "fixed-clock"; 115 compatible = "fixed-clock";
118 #clock-cells = <0>; 116 #clock-cells = <0>;
119 clock-output-names = "osc_sys" <<
120 /* This value must be overridd 117 /* This value must be overridden by the board */
121 clock-frequency = <0>; 118 clock-frequency = <0>;
122 }; 119 };
123 120
124 osc_aud: osc-aud { !! 121 osc_aud: osc_aud {
125 compatible = "fixed-clock"; 122 compatible = "fixed-clock";
126 #clock-cells = <0>; 123 #clock-cells = <0>;
127 clock-output-names = "osc_aud" <<
128 /* This value must be overridd 124 /* This value must be overridden by the board */
129 clock-frequency = <0>; 125 clock-frequency = <0>;
130 }; 126 };
131 127
132 gmac_rmii_ref: gmac-rmii-ref { !! 128 gmac_rmii_ref: gmac_rmii_ref {
133 compatible = "fixed-clock"; 129 compatible = "fixed-clock";
134 #clock-cells = <0>; 130 #clock-cells = <0>;
135 clock-output-names = "gmac_rmi <<
136 /* Should be overridden by the 131 /* Should be overridden by the board when needed */
137 clock-frequency = <0>; 132 clock-frequency = <0>;
138 }; 133 };
139 134
140 gmac_gr_mii_rxclk: gmac-gr-mii-rxclk { !! 135 gmac_gr_mii_rxclk: gmac_gr_mii_rxclk {
141 compatible = "fixed-clock"; 136 compatible = "fixed-clock";
142 #clock-cells = <0>; 137 #clock-cells = <0>;
143 clock-output-names = "gmac_gr_ <<
144 /* Should be overridden by the 138 /* Should be overridden by the board when needed */
145 clock-frequency = <0>; 139 clock-frequency = <0>;
146 }; 140 };
147 141
148 soc { 142 soc {
149 compatible = "simple-bus"; 143 compatible = "simple-bus";
150 interrupt-parent = <&plic>; 144 interrupt-parent = <&plic>;
151 #address-cells = <2>; 145 #address-cells = <2>;
152 #size-cells = <2>; 146 #size-cells = <2>;
153 dma-noncoherent; <<
154 ranges; 147 ranges;
155 148
156 clint: clint@2000000 { 149 clint: clint@2000000 {
157 compatible = "starfive 150 compatible = "starfive,jh7100-clint", "sifive,clint0";
158 reg = <0x0 0x2000000 0 151 reg = <0x0 0x2000000 0x0 0x10000>;
159 interrupts-extended = !! 152 interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
160 !! 153 &cpu1_intc 3 &cpu1_intc 7>;
161 }; <<
162 <<
163 ccache: cache-controller@20100 <<
164 compatible = "starfive <<
165 reg = <0x0 0x2010000 0 <<
166 interrupts = <128>, <1 <<
167 cache-block-size = <64 <<
168 cache-level = <2>; <<
169 cache-sets = <2048>; <<
170 cache-size = <2097152> <<
171 cache-unified; <<
172 }; 154 };
173 155
174 plic: interrupt-controller@c00 156 plic: interrupt-controller@c000000 {
175 compatible = "starfive 157 compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
176 reg = <0x0 0xc000000 0 158 reg = <0x0 0xc000000 0x0 0x4000000>;
177 interrupts-extended = !! 159 interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9
178 !! 160 &cpu1_intc 11 &cpu1_intc 9>;
179 interrupt-controller; 161 interrupt-controller;
180 #address-cells = <0>; 162 #address-cells = <0>;
181 #interrupt-cells = <1> 163 #interrupt-cells = <1>;
182 riscv,ndev = <133>; 164 riscv,ndev = <133>;
183 }; 165 };
184 166
185 sdio0: mmc@10000000 { <<
186 compatible = "snps,dw- <<
187 reg = <0x0 0x10000000 <<
188 clocks = <&clkgen JH71 <<
189 <&clkgen JH71 <<
190 clock-names = "biu", " <<
191 interrupts = <4>; <<
192 data-addr = <0>; <<
193 fifo-depth = <32>; <<
194 fifo-watermark-aligned <<
195 status = "disabled"; <<
196 }; <<
197 <<
198 sdio1: mmc@10010000 { <<
199 compatible = "snps,dw- <<
200 reg = <0x0 0x10010000 <<
201 clocks = <&clkgen JH71 <<
202 <&clkgen JH71 <<
203 clock-names = "biu", " <<
204 interrupts = <5>; <<
205 data-addr = <0>; <<
206 fifo-depth = <32>; <<
207 fifo-watermark-aligned <<
208 status = "disabled"; <<
209 }; <<
210 <<
211 gmac: ethernet@10020000 { <<
212 compatible = "starfive <<
213 reg = <0x0 0x10020000 <<
214 clocks = <&clkgen JH71 <<
215 <&clkgen JH71 <<
216 <&clkgen JH71 <<
217 <&clkgen JH71 <<
218 <&clkgen JH71 <<
219 clock-names = "stmmace <<
220 resets = <&rstgen JH71 <<
221 reset-names = "ahb"; <<
222 interrupts = <6>, <7>; <<
223 interrupt-names = "mac <<
224 max-frame-size = <9000 <<
225 snps,multicast-filter- <<
226 snps,perfect-filter-en <<
227 starfive,syscon = <&sy <<
228 rx-fifo-depth = <32768 <<
229 tx-fifo-depth = <16384 <<
230 snps,axi-config = <&st <<
231 snps,fixed-burst; <<
232 snps,force_thresh_dma_ <<
233 status = "disabled"; <<
234 <<
235 stmmac_axi_setup: stmm <<
236 snps,wr_osr_lm <<
237 snps,rd_osr_lm <<
238 snps,blen = <2 <<
239 }; <<
240 }; <<
241 <<
242 clkgen: clock-controller@11800 167 clkgen: clock-controller@11800000 {
243 compatible = "starfive 168 compatible = "starfive,jh7100-clkgen";
244 reg = <0x0 0x11800000 169 reg = <0x0 0x11800000 0x0 0x10000>;
245 clocks = <&osc_sys>, < 170 clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>;
246 clock-names = "osc_sys 171 clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk";
247 #clock-cells = <1>; 172 #clock-cells = <1>;
248 }; 173 };
249 174
250 rstgen: reset-controller@11840 175 rstgen: reset-controller@11840000 {
251 compatible = "starfive 176 compatible = "starfive,jh7100-reset";
252 reg = <0x0 0x11840000 177 reg = <0x0 0x11840000 0x0 0x10000>;
253 #reset-cells = <1>; 178 #reset-cells = <1>;
254 }; 179 };
255 180
256 sysmain: syscon@11850000 { <<
257 compatible = "starfive <<
258 reg = <0x0 0x11850000 <<
259 }; <<
260 <<
261 i2c0: i2c@118b0000 { 181 i2c0: i2c@118b0000 {
262 compatible = "snps,des 182 compatible = "snps,designware-i2c";
263 reg = <0x0 0x118b0000 183 reg = <0x0 0x118b0000 0x0 0x10000>;
264 clocks = <&clkgen JH71 184 clocks = <&clkgen JH7100_CLK_I2C0_CORE>,
265 <&clkgen JH71 185 <&clkgen JH7100_CLK_I2C0_APB>;
266 clock-names = "ref", " 186 clock-names = "ref", "pclk";
267 resets = <&rstgen JH71 187 resets = <&rstgen JH7100_RSTN_I2C0_APB>;
268 interrupts = <96>; 188 interrupts = <96>;
269 #address-cells = <1>; 189 #address-cells = <1>;
270 #size-cells = <0>; 190 #size-cells = <0>;
271 status = "disabled"; 191 status = "disabled";
272 }; 192 };
273 193
274 i2c1: i2c@118c0000 { 194 i2c1: i2c@118c0000 {
275 compatible = "snps,des 195 compatible = "snps,designware-i2c";
276 reg = <0x0 0x118c0000 196 reg = <0x0 0x118c0000 0x0 0x10000>;
277 clocks = <&clkgen JH71 197 clocks = <&clkgen JH7100_CLK_I2C1_CORE>,
278 <&clkgen JH71 198 <&clkgen JH7100_CLK_I2C1_APB>;
279 clock-names = "ref", " 199 clock-names = "ref", "pclk";
280 resets = <&rstgen JH71 200 resets = <&rstgen JH7100_RSTN_I2C1_APB>;
281 interrupts = <97>; 201 interrupts = <97>;
282 #address-cells = <1>; 202 #address-cells = <1>;
283 #size-cells = <0>; 203 #size-cells = <0>;
284 status = "disabled"; 204 status = "disabled";
285 }; 205 };
286 206
287 gpio: pinctrl@11910000 { 207 gpio: pinctrl@11910000 {
288 compatible = "starfive 208 compatible = "starfive,jh7100-pinctrl";
289 reg = <0x0 0x11910000 209 reg = <0x0 0x11910000 0x0 0x10000>,
290 <0x0 0x11858000 210 <0x0 0x11858000 0x0 0x1000>;
291 reg-names = "gpio", "p 211 reg-names = "gpio", "padctl";
292 clocks = <&clkgen JH71 212 clocks = <&clkgen JH7100_CLK_GPIO_APB>;
293 resets = <&rstgen JH71 213 resets = <&rstgen JH7100_RSTN_GPIO_APB>;
294 interrupts = <32>; 214 interrupts = <32>;
295 gpio-controller; 215 gpio-controller;
296 #gpio-cells = <2>; 216 #gpio-cells = <2>;
297 interrupt-controller; 217 interrupt-controller;
298 #interrupt-cells = <2> 218 #interrupt-cells = <2>;
299 }; 219 };
300 220
301 uart2: serial@12430000 { 221 uart2: serial@12430000 {
302 compatible = "starfive 222 compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
303 reg = <0x0 0x12430000 223 reg = <0x0 0x12430000 0x0 0x10000>;
304 clocks = <&clkgen JH71 224 clocks = <&clkgen JH7100_CLK_UART2_CORE>,
305 <&clkgen JH71 225 <&clkgen JH7100_CLK_UART2_APB>;
306 clock-names = "baudclk 226 clock-names = "baudclk", "apb_pclk";
307 resets = <&rstgen JH71 227 resets = <&rstgen JH7100_RSTN_UART2_APB>;
308 interrupts = <72>; 228 interrupts = <72>;
309 reg-io-width = <4>; 229 reg-io-width = <4>;
310 reg-shift = <2>; 230 reg-shift = <2>;
311 status = "disabled"; 231 status = "disabled";
312 }; 232 };
313 233
314 uart3: serial@12440000 { 234 uart3: serial@12440000 {
315 compatible = "starfive 235 compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
316 reg = <0x0 0x12440000 236 reg = <0x0 0x12440000 0x0 0x10000>;
317 clocks = <&clkgen JH71 237 clocks = <&clkgen JH7100_CLK_UART3_CORE>,
318 <&clkgen JH71 238 <&clkgen JH7100_CLK_UART3_APB>;
319 clock-names = "baudclk 239 clock-names = "baudclk", "apb_pclk";
320 resets = <&rstgen JH71 240 resets = <&rstgen JH7100_RSTN_UART3_APB>;
321 interrupts = <73>; 241 interrupts = <73>;
322 reg-io-width = <4>; 242 reg-io-width = <4>;
323 reg-shift = <2>; 243 reg-shift = <2>;
324 status = "disabled"; 244 status = "disabled";
325 }; 245 };
326 246
327 i2c2: i2c@12450000 { 247 i2c2: i2c@12450000 {
328 compatible = "snps,des 248 compatible = "snps,designware-i2c";
329 reg = <0x0 0x12450000 249 reg = <0x0 0x12450000 0x0 0x10000>;
330 clocks = <&clkgen JH71 250 clocks = <&clkgen JH7100_CLK_I2C2_CORE>,
331 <&clkgen JH71 251 <&clkgen JH7100_CLK_I2C2_APB>;
332 clock-names = "ref", " 252 clock-names = "ref", "pclk";
333 resets = <&rstgen JH71 253 resets = <&rstgen JH7100_RSTN_I2C2_APB>;
334 interrupts = <74>; 254 interrupts = <74>;
335 #address-cells = <1>; 255 #address-cells = <1>;
336 #size-cells = <0>; 256 #size-cells = <0>;
337 status = "disabled"; 257 status = "disabled";
338 }; 258 };
339 259
340 i2c3: i2c@12460000 { 260 i2c3: i2c@12460000 {
341 compatible = "snps,des 261 compatible = "snps,designware-i2c";
342 reg = <0x0 0x12460000 262 reg = <0x0 0x12460000 0x0 0x10000>;
343 clocks = <&clkgen JH71 263 clocks = <&clkgen JH7100_CLK_I2C3_CORE>,
344 <&clkgen JH71 264 <&clkgen JH7100_CLK_I2C3_APB>;
345 clock-names = "ref", " 265 clock-names = "ref", "pclk";
346 resets = <&rstgen JH71 266 resets = <&rstgen JH7100_RSTN_I2C3_APB>;
347 interrupts = <75>; 267 interrupts = <75>;
348 #address-cells = <1>; 268 #address-cells = <1>;
349 #size-cells = <0>; 269 #size-cells = <0>;
350 status = "disabled"; 270 status = "disabled";
351 }; 271 };
352 272
353 watchdog@12480000 { 273 watchdog@12480000 {
354 compatible = "starfive 274 compatible = "starfive,jh7100-wdt";
355 reg = <0x0 0x12480000 275 reg = <0x0 0x12480000 0x0 0x10000>;
356 clocks = <&clkgen JH71 276 clocks = <&clkgen JH7100_CLK_WDTIMER_APB>,
357 <&clkgen JH71 277 <&clkgen JH7100_CLK_WDT_CORE>;
358 clock-names = "apb", " 278 clock-names = "apb", "core";
359 resets = <&rstgen JH71 279 resets = <&rstgen JH7100_RSTN_WDTIMER_APB>,
360 <&rstgen JH71 280 <&rstgen JH7100_RSTN_WDT>;
361 }; <<
362 <<
363 pwm: pwm@12490000 { <<
364 compatible = "starfive <<
365 reg = <0x0 0x12490000 <<
366 clocks = <&clkgen JH71 <<
367 resets = <&rstgen JH71 <<
368 #pwm-cells = <3>; <<
369 status = "disabled"; <<
370 }; 281 };
371 282
372 sfctemp: temperature-sensor@12 283 sfctemp: temperature-sensor@124a0000 {
373 compatible = "starfive 284 compatible = "starfive,jh7100-temp";
374 reg = <0x0 0x124a0000 285 reg = <0x0 0x124a0000 0x0 0x10000>;
375 clocks = <&clkgen JH71 286 clocks = <&clkgen JH7100_CLK_TEMP_SENSE>,
376 <&clkgen JH71 287 <&clkgen JH7100_CLK_TEMP_APB>;
377 clock-names = "sense", 288 clock-names = "sense", "bus";
378 resets = <&rstgen JH71 289 resets = <&rstgen JH7100_RSTN_TEMP_SENSE>,
379 <&rstgen JH71 290 <&rstgen JH7100_RSTN_TEMP_APB>;
380 reset-names = "sense", 291 reset-names = "sense", "bus";
381 #thermal-sensor-cells 292 #thermal-sensor-cells = <0>;
382 }; 293 };
383 }; 294 };
384 }; 295 };
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