1 // SPDX-License-Identifier: GPL-2.0 OR MIT 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /* 2 /*
3 * Copyright (C) 2023 Jisheng Zhang <jszhang@ke 3 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 #include "jh7110-common.dtsi" 7 #include "jh7110-common.dtsi"
8 8
9 / { 9 / {
10 model = "Milk-V Mars"; 10 model = "Milk-V Mars";
11 compatible = "milkv,mars", "starfive,j 11 compatible = "milkv,mars", "starfive,jh7110";
12 }; 12 };
13 13
14 &gmac0 { 14 &gmac0 {
15 starfive,tx-use-rgmii-clk; 15 starfive,tx-use-rgmii-clk;
16 assigned-clocks = <&aoncrg JH7110_AONC 16 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
17 assigned-clock-parents = <&aoncrg JH71 17 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
18 }; 18 };
19 19
20 &pcie0 { 20 &pcie0 {
21 status = "okay"; 21 status = "okay";
22 }; 22 };
23 23
24 &pcie1 { 24 &pcie1 {
25 status = "okay"; 25 status = "okay";
26 }; 26 };
27 27
28 &phy0 { 28 &phy0 {
29 motorcomm,tx-clk-adj-enabled; 29 motorcomm,tx-clk-adj-enabled;
30 motorcomm,tx-clk-10-inverted; 30 motorcomm,tx-clk-10-inverted;
31 motorcomm,tx-clk-100-inverted; 31 motorcomm,tx-clk-100-inverted;
32 motorcomm,tx-clk-1000-inverted; 32 motorcomm,tx-clk-1000-inverted;
33 motorcomm,rx-clk-drv-microamp = <3970> 33 motorcomm,rx-clk-drv-microamp = <3970>;
34 motorcomm,rx-data-drv-microamp = <2910 34 motorcomm,rx-data-drv-microamp = <2910>;
35 rx-internal-delay-ps = <1500>; 35 rx-internal-delay-ps = <1500>;
36 tx-internal-delay-ps = <1500>; 36 tx-internal-delay-ps = <1500>;
37 }; 37 };
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