1 /* SPDX-License-Identifier: GPL-2.0 */ 1 2 #ifndef __ASM_ARCH_REGS_AC97_H 3 #define __ASM_ARCH_REGS_AC97_H 4 5 /* 6 * AC97 Controller registers 7 */ 8 9 #define POCR (0x0000) /* PCM 10 #define POCR_FEIE (1 << 3) /* FIF 11 #define POCR_FSRIE (1 << 1) /* FIF 12 13 #define PICR (0x0004) /* PCM 14 #define PICR_FEIE (1 << 3) /* FIF 15 #define PICR_FSRIE (1 << 1) /* FIF 16 17 #define MCCR (0x0008) /* Mic 18 #define MCCR_FEIE (1 << 3) /* FIF 19 #define MCCR_FSRIE (1 << 1) /* FIF 20 21 #define GCR (0x000C) /* Gl 22 #ifdef CONFIG_PXA3xx 23 #define GCR_CLKBPB (1 << 31) /* Int 24 #endif 25 #define GCR_nDMAEN (1 << 24) /* non 26 #define GCR_CDONE_IE (1 << 19) /* Com 27 #define GCR_SDONE_IE (1 << 18) /* Sta 28 #define GCR_SECRDY_IEN (1 << 9) /* Sec 29 #define GCR_PRIRDY_IEN (1 << 8) /* Pri 30 #define GCR_SECRES_IEN (1 << 5) /* Sec 31 #define GCR_PRIRES_IEN (1 << 4) /* Pri 32 #define GCR_ACLINK_OFF (1 << 3) /* AC- 33 #define GCR_WARM_RST (1 << 2) /* AC9 34 #define GCR_COLD_RST (1 << 1) /* AC' 35 #define GCR_GIE (1 << 0) /* Cod 36 37 #define POSR (0x0010) /* PCM 38 #define POSR_FIFOE (1 << 4) /* FIF 39 #define POSR_FSR (1 << 2) /* FIF 40 41 #define PISR (0x0014) /* PCM 42 #define PISR_FIFOE (1 << 4) /* FIF 43 #define PISR_EOC (1 << 3) /* DMA 44 #define PISR_FSR (1 << 2) /* FIF 45 46 #define MCSR (0x0018) /* Mic 47 #define MCSR_FIFOE (1 << 4) /* FIF 48 #define MCSR_EOC (1 << 3) /* DMA 49 #define MCSR_FSR (1 << 2) /* FIF 50 51 #define GSR (0x001C) /* Glo 52 #define GSR_CDONE (1 << 19) /* Com 53 #define GSR_SDONE (1 << 18) /* Sta 54 #define GSR_RDCS (1 << 15) /* Rea 55 #define GSR_BIT3SLT12 (1 << 14) /* Bit 56 #define GSR_BIT2SLT12 (1 << 13) /* Bit 57 #define GSR_BIT1SLT12 (1 << 12) /* Bit 58 #define GSR_SECRES (1 << 11) /* Sec 59 #define GSR_PRIRES (1 << 10) /* Pri 60 #define GSR_SCR (1 << 9) /* Sec 61 #define GSR_PCR (1 << 8) /* Pr 62 #define GSR_MCINT (1 << 7) /* Mic 63 #define GSR_POINT (1 << 6) /* PCM 64 #define GSR_PIINT (1 << 5) /* PCM 65 #define GSR_ACOFFD (1 << 3) /* AC- 66 #define GSR_MOINT (1 << 2) /* Mod 67 #define GSR_MIINT (1 << 1) /* Mod 68 #define GSR_GSCI (1 << 0) /* Cod 69 70 #define CAR (0x0020) /* COD 71 #define CAR_CAIP (1 << 0) /* Cod 72 73 #define PCDR (0x0040) /* PCM 74 #define MCDR (0x0060) /* Mic 75 76 #define MOCR (0x0100) /* Mod 77 #define MOCR_FEIE (1 << 3) /* FIF 78 #define MOCR_FSRIE (1 << 1) /* FIF 79 80 #define MICR (0x0108) /* Mod 81 #define MICR_FEIE (1 << 3) /* FIF 82 #define MICR_FSRIE (1 << 1) /* FIF 83 84 #define MOSR (0x0110) /* Mod 85 #define MOSR_FIFOE (1 << 4) /* FIF 86 #define MOSR_FSR (1 << 2) /* FIF 87 88 #define MISR (0x0118) /* Mod 89 #define MISR_FIFOE (1 << 4) /* FIF 90 #define MISR_EOC (1 << 3) /* DMA 91 #define MISR_FSR (1 << 2) /* FIF 92 93 #define MODR (0x0140) /* Mod 94 95 #define PAC_REG_BASE (0x0200) /* Pri 96 #define SAC_REG_BASE (0x0300) /* Sec 97 #define PMC_REG_BASE (0x0400) /* Pri 98 #define SMC_REG_BASE (0x0500) /* Sec 99 100 #endif /* __ASM_ARCH_REGS_AC97_H */ 101
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