1 // SPDX-License-Identifier: GPL-2.0-only 1
2 /*
3 * HD-audio stream operations
4 */
5
6 #include <linux/kernel.h>
7 #include <linux/delay.h>
8 #include <linux/export.h>
9 #include <linux/clocksource.h>
10 #include <sound/compress_driver.h>
11 #include <sound/core.h>
12 #include <sound/pcm.h>
13 #include <sound/hdaudio.h>
14 #include <sound/hda_register.h>
15 #include "trace.h"
16
17 /*
18 * the hdac_stream library is intended to be u
19 * transitions. The states are not formally de
20 * inspired by boolean variables. Note that th
21 * in this library but by the callers during t
22 *
23 * |
24 * stream_init() |
25 * v
26 * +--+-------+
27 * | unused |
28 * +--+----+--+
29 * | ^
30 * stream_assign() | | stream_re
31 * v |
32 * +--+----+--+
33 * | opened |
34 * +--+----+--+
35 * | ^
36 * stream_reset() | |
37 * stream_setup() | | stream_cl
38 * v |
39 * +--+----+--+
40 * | prepared |
41 * +--+----+--+
42 * | ^
43 * stream_start() | | stream_st
44 * v |
45 * +--+----+--+
46 * | running |
47 * +----------+
48 */
49
50 /**
51 * snd_hdac_get_stream_stripe_ctl - get stripe
52 * @bus: HD-audio core bus
53 * @substream: PCM substream
54 */
55 int snd_hdac_get_stream_stripe_ctl(struct hdac
56 struct snd_
57 {
58 struct snd_pcm_runtime *runtime = subs
59 unsigned int channels = runtime->chann
60 rate = runtime->rate,
61 bits_per_sample = runtime
62 max_sdo_lines, value, sdo
63
64 /* T_AZA_GCAP_NSDO is 1:2 bitfields in
65 max_sdo_lines = snd_hdac_chip_readl(bu
66
67 /* following is from HD audio spec */
68 for (sdo_line = max_sdo_lines; sdo_lin
69 if (rate > 48000)
70 value = (channels * bi
71 (rate
72 else
73 value = (channels * bi
74
75 if (value >= bus->sdo_limit)
76 break;
77 }
78
79 /* stripe value: 0 for 1SDO, 1 for 2SD
80 return sdo_line >> 1;
81 }
82 EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_c
83
84 /**
85 * snd_hdac_stream_init - initialize each stre
86 * @bus: HD-audio core bus
87 * @azx_dev: HD-audio core stream object to in
88 * @idx: stream index number
89 * @direction: stream direction (SNDRV_PCM_STR
90 * @tag: the tag id to assign
91 *
92 * Assign the starting bdl address to each str
93 */
94 void snd_hdac_stream_init(struct hdac_bus *bus
95 int idx, int directi
96 {
97 azx_dev->bus = bus;
98 /* offset: SDI0=0x80, SDI1=0xa0, ... S
99 azx_dev->sd_addr = bus->remap_addr + (
100 /* int mask: SDI0=0x01, SDI1=0x02, ...
101 azx_dev->sd_int_sta_mask = 1 << idx;
102 azx_dev->index = idx;
103 azx_dev->direction = direction;
104 azx_dev->stream_tag = tag;
105 snd_hdac_dsp_lock_init(azx_dev);
106 list_add_tail(&azx_dev->list, &bus->st
107
108 if (bus->spbcap) {
109 azx_dev->spib_addr = bus->spbc
110 AZX_SP
111 AZX_SP
112
113 azx_dev->fifo_addr = bus->spbc
114 AZX_SP
115 AZX_SP
116 }
117
118 if (bus->drsmcap)
119 azx_dev->dpibr_addr = bus->drs
120 AZX_DR
121 }
122 EXPORT_SYMBOL_GPL(snd_hdac_stream_init);
123
124 /**
125 * snd_hdac_stream_start - start a stream
126 * @azx_dev: HD-audio core stream to start
127 *
128 * Start a stream, set start_wallclk and set t
129 */
130 void snd_hdac_stream_start(struct hdac_stream
131 {
132 struct hdac_bus *bus = azx_dev->bus;
133 int stripe_ctl;
134
135 trace_snd_hdac_stream_start(bus, azx_d
136
137 azx_dev->start_wallclk = snd_hdac_chip
138
139 /* enable SIE */
140 snd_hdac_chip_updatel(bus, INTCTL,
141 1 << azx_dev->in
142 1 << azx_dev->in
143 /* set stripe control */
144 if (azx_dev->stripe) {
145 if (azx_dev->substream)
146 stripe_ctl = snd_hdac_
147 else
148 stripe_ctl = 0;
149 snd_hdac_stream_updateb(azx_de
150 stripe
151 }
152 /* set DMA start and interrupt mask */
153 if (bus->access_sdnctl_in_dword)
154 snd_hdac_stream_updatel(azx_de
155 0, SD_CTL_DMA_
156 else
157 snd_hdac_stream_updateb(azx_de
158 0, SD_CTL_DMA_
159 azx_dev->running = true;
160 }
161 EXPORT_SYMBOL_GPL(snd_hdac_stream_start);
162
163 /**
164 * snd_hdac_stream_clear - helper to clear str
165 * @azx_dev: HD-audio core stream to stop
166 */
167 static void snd_hdac_stream_clear(struct hdac_
168 {
169 snd_hdac_stream_updateb(azx_dev, SD_CT
170 SD_CTL_DMA_STA
171 snd_hdac_stream_writeb(azx_dev, SD_STS
172 if (azx_dev->stripe)
173 snd_hdac_stream_updateb(azx_de
174 azx_dev->running = false;
175 }
176
177 /**
178 * snd_hdac_stream_stop - stop a stream
179 * @azx_dev: HD-audio core stream to stop
180 *
181 * Stop a stream DMA and disable stream interr
182 */
183 void snd_hdac_stream_stop(struct hdac_stream *
184 {
185 trace_snd_hdac_stream_stop(azx_dev->bu
186
187 snd_hdac_stream_clear(azx_dev);
188 /* disable SIE */
189 snd_hdac_chip_updatel(azx_dev->bus, IN
190 }
191 EXPORT_SYMBOL_GPL(snd_hdac_stream_stop);
192
193 /**
194 * snd_hdac_stop_streams - stop all streams
195 * @bus: HD-audio core bus
196 */
197 void snd_hdac_stop_streams(struct hdac_bus *bu
198 {
199 struct hdac_stream *stream;
200
201 list_for_each_entry(stream, &bus->stre
202 snd_hdac_stream_stop(stream);
203 }
204 EXPORT_SYMBOL_GPL(snd_hdac_stop_streams);
205
206 /**
207 * snd_hdac_stop_streams_and_chip - stop all s
208 * @bus: HD-audio core bus
209 */
210 void snd_hdac_stop_streams_and_chip(struct hda
211 {
212
213 if (bus->chip_init) {
214 snd_hdac_stop_streams(bus);
215 snd_hdac_bus_stop_chip(bus);
216 }
217 }
218 EXPORT_SYMBOL_GPL(snd_hdac_stop_streams_and_ch
219
220 /**
221 * snd_hdac_stream_reset - reset a stream
222 * @azx_dev: HD-audio core stream to reset
223 */
224 void snd_hdac_stream_reset(struct hdac_stream
225 {
226 unsigned char val;
227 int dma_run_state;
228
229 snd_hdac_stream_clear(azx_dev);
230
231 dma_run_state = snd_hdac_stream_readb(
232
233 snd_hdac_stream_updateb(azx_dev, SD_CT
234
235 /* wait for hardware to report that th
236 snd_hdac_stream_readb_poll(azx_dev, SD
237
238 if (azx_dev->bus->dma_stop_delay && dm
239 udelay(azx_dev->bus->dma_stop_
240
241 snd_hdac_stream_updateb(azx_dev, SD_CT
242
243 /* wait for hardware to report that th
244 snd_hdac_stream_readb_poll(azx_dev, SD
245
246 /* reset first position - may not be s
247 if (azx_dev->posbuf)
248 *azx_dev->posbuf = 0;
249 }
250 EXPORT_SYMBOL_GPL(snd_hdac_stream_reset);
251
252 /**
253 * snd_hdac_stream_setup - set up the SD for
254 * @azx_dev: HD-audio core stream to set up
255 * @code_loading: Whether the stream is for PC
256 */
257 int snd_hdac_stream_setup(struct hdac_stream *
258 {
259 struct hdac_bus *bus = azx_dev->bus;
260 struct snd_pcm_runtime *runtime;
261 unsigned int val;
262 u16 reg;
263 int ret;
264
265 if (azx_dev->substream)
266 runtime = azx_dev->substream->
267 else
268 runtime = NULL;
269 /* make sure the run bit is zero for S
270 snd_hdac_stream_clear(azx_dev);
271 /* program the stream_tag */
272 val = snd_hdac_stream_readl(azx_dev, S
273 val = (val & ~SD_CTL_STREAM_TAG_MASK)
274 (azx_dev->stream_tag << SD_CTL
275 if (!bus->snoop)
276 val |= SD_CTL_TRAFFIC_PRIO;
277 snd_hdac_stream_writel(azx_dev, SD_CTL
278
279 /* program the length of samples in cy
280 snd_hdac_stream_writel(azx_dev, SD_CBL
281
282 /* program the stream format */
283 /* this value needs to be the same as
284 snd_hdac_stream_writew(azx_dev, SD_FOR
285
286 /* program the stream LVI (last valid
287 snd_hdac_stream_writew(azx_dev, SD_LVI
288
289 /* program the BDL address */
290 /* lower BDL address */
291 snd_hdac_stream_writel(azx_dev, SD_BDL
292 /* upper BDL address */
293 snd_hdac_stream_writel(azx_dev, SD_BDL
294 upper_32_bits(a
295
296 /* enable the position buffer */
297 if (bus->use_posbuf && bus->posbuf.add
298 if (!(snd_hdac_chip_readl(bus,
299 snd_hdac_chip_writel(b
300 (u32)bus->posb
301 }
302
303 /* set the interrupt enable bits in th
304 snd_hdac_stream_updatel(azx_dev, SD_CT
305
306 if (!code_loading) {
307 /* Once SDxFMT is set, the con
308 ret = snd_hdac_stream_readw_po
309
310 if (ret)
311 dev_dbg(bus->dev, "pol
312 AZX_REG_SD_FIF
313 azx_dev->fifo_size = reg;
314 }
315
316 /* when LPIB delay correction gives a
317 * we ignore it; currently set the thr
318 * 64 frames
319 */
320 if (runtime && runtime->period_size >
321 azx_dev->delay_negative_thresh
322 -frames_to_bytes(runti
323 else
324 azx_dev->delay_negative_thresh
325
326 /* wallclk has 24Mhz clock source */
327 if (runtime)
328 azx_dev->period_wallclk = (((r
329 runtime->r
330
331 return 0;
332 }
333 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup);
334
335 /**
336 * snd_hdac_stream_cleanup - cleanup a stream
337 * @azx_dev: HD-audio core stream to clean up
338 */
339 void snd_hdac_stream_cleanup(struct hdac_strea
340 {
341 snd_hdac_stream_writel(azx_dev, SD_BDL
342 snd_hdac_stream_writel(azx_dev, SD_BDL
343 snd_hdac_stream_writel(azx_dev, SD_CTL
344 azx_dev->bufsize = 0;
345 azx_dev->period_bytes = 0;
346 azx_dev->format_val = 0;
347 }
348 EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup);
349
350 /**
351 * snd_hdac_stream_assign - assign a stream fo
352 * @bus: HD-audio core bus
353 * @substream: PCM substream to assign
354 *
355 * Look for an unused stream for the given PCM
356 * and return the stream object. If no stream
357 * The function tries to keep using the same s
358 * beforehand. Also, when bus->reverse_assign
359 * or matching entry is returned. This is nee
360 */
361 struct hdac_stream *snd_hdac_stream_assign(str
362 str
363 {
364 struct hdac_stream *azx_dev;
365 struct hdac_stream *res = NULL;
366
367 /* make a non-zero unique key for the
368 int key = (substream->number << 2) | (
369
370 if (substream->pcm)
371 key |= (substream->pcm->device
372
373 spin_lock_irq(&bus->reg_lock);
374 list_for_each_entry(azx_dev, &bus->str
375 if (azx_dev->direction != subs
376 continue;
377 if (azx_dev->opened)
378 continue;
379 if (azx_dev->assigned_key == k
380 res = azx_dev;
381 break;
382 }
383 if (!res || bus->reverse_assig
384 res = azx_dev;
385 }
386 if (res) {
387 res->opened = 1;
388 res->running = 0;
389 res->assigned_key = key;
390 res->substream = substream;
391 }
392 spin_unlock_irq(&bus->reg_lock);
393 return res;
394 }
395 EXPORT_SYMBOL_GPL(snd_hdac_stream_assign);
396
397 /**
398 * snd_hdac_stream_release_locked - release th
399 * @azx_dev: HD-audio core stream to release
400 *
401 * Release the stream that has been assigned b
402 * The bus->reg_lock needs to be taken at a hi
403 */
404 void snd_hdac_stream_release_locked(struct hda
405 {
406 azx_dev->opened = 0;
407 azx_dev->running = 0;
408 azx_dev->substream = NULL;
409 }
410 EXPORT_SYMBOL_GPL(snd_hdac_stream_release_lock
411
412 /**
413 * snd_hdac_stream_release - release the assig
414 * @azx_dev: HD-audio core stream to release
415 *
416 * Release the stream that has been assigned b
417 */
418 void snd_hdac_stream_release(struct hdac_strea
419 {
420 struct hdac_bus *bus = azx_dev->bus;
421
422 spin_lock_irq(&bus->reg_lock);
423 snd_hdac_stream_release_locked(azx_dev
424 spin_unlock_irq(&bus->reg_lock);
425 }
426 EXPORT_SYMBOL_GPL(snd_hdac_stream_release);
427
428 /**
429 * snd_hdac_get_stream - return hdac_stream ba
430 * direction
431 *
432 * @bus: HD-audio core bus
433 * @dir: direction for the stream to be found
434 * @stream_tag: stream tag for stream to be fo
435 */
436 struct hdac_stream *snd_hdac_get_stream(struct
437 int di
438 {
439 struct hdac_stream *s;
440
441 list_for_each_entry(s, &bus->stream_li
442 if (s->direction == dir && s->
443 return s;
444 }
445
446 return NULL;
447 }
448 EXPORT_SYMBOL_GPL(snd_hdac_get_stream);
449
450 /*
451 * set up a BDL entry
452 */
453 static int setup_bdle(struct hdac_bus *bus,
454 struct snd_dma_buffer *d
455 struct hdac_stream *azx_
456 int ofs, int size, int w
457 {
458 __le32 *bdl = *bdlp;
459
460 while (size > 0) {
461 dma_addr_t addr;
462 int chunk;
463
464 if (azx_dev->frags >= AZX_MAX_
465 return -EINVAL;
466
467 addr = snd_sgbuf_get_addr(dmab
468 /* program the address field o
469 bdl[0] = cpu_to_le32((u32)addr
470 bdl[1] = cpu_to_le32(upper_32_
471 /* program the size field of t
472 chunk = snd_sgbuf_get_chunk_si
473 /* one BDLE cannot cross 4K bo
474 if (bus->align_bdle_4k) {
475 u32 remain = 0x1000 -
476
477 if (chunk > remain)
478 chunk = remain
479 }
480 bdl[2] = cpu_to_le32(chunk);
481 /* program the IOC to enable i
482 * only when the whole fragmen
483 */
484 size -= chunk;
485 bdl[3] = (size || !with_ioc) ?
486 bdl += 4;
487 azx_dev->frags++;
488 ofs += chunk;
489 }
490 *bdlp = bdl;
491 return ofs;
492 }
493
494 /**
495 * snd_hdac_stream_setup_periods - set up BDL
496 * @azx_dev: HD-audio core stream to set up
497 *
498 * Set up the buffer descriptor table of the g
499 * period and buffer sizes of the assigned PCM
500 */
501 int snd_hdac_stream_setup_periods(struct hdac_
502 {
503 struct hdac_bus *bus = azx_dev->bus;
504 struct snd_pcm_substream *substream =
505 struct snd_compr_stream *cstream = azx
506 struct snd_pcm_runtime *runtime = NULL
507 struct snd_dma_buffer *dmab;
508 __le32 *bdl;
509 int i, ofs, periods, period_bytes;
510 int pos_adj, pos_align;
511
512 if (substream) {
513 runtime = substream->runtime;
514 dmab = snd_pcm_get_dma_buf(sub
515 } else if (cstream) {
516 dmab = snd_pcm_get_dma_buf(cst
517 } else {
518 WARN(1, "No substream or cstre
519 return -EINVAL;
520 }
521
522 /* reset BDL address */
523 snd_hdac_stream_writel(azx_dev, SD_BDL
524 snd_hdac_stream_writel(azx_dev, SD_BDL
525
526 period_bytes = azx_dev->period_bytes;
527 periods = azx_dev->bufsize / period_by
528
529 /* program the initial BDL entries */
530 bdl = (__le32 *)azx_dev->bdl.area;
531 ofs = 0;
532 azx_dev->frags = 0;
533
534 pos_adj = bus->bdl_pos_adj;
535 if (runtime && !azx_dev->no_period_wak
536 pos_align = pos_adj;
537 pos_adj = DIV_ROUND_UP(pos_adj
538 if (!pos_adj)
539 pos_adj = pos_align;
540 else
541 pos_adj = roundup(pos_
542 pos_adj = frames_to_bytes(runt
543 if (pos_adj >= period_bytes) {
544 dev_warn(bus->dev, "To
545 pos_adj);
546 pos_adj = 0;
547 } else {
548 ofs = setup_bdle(bus,
549 &bdl,
550 if (ofs < 0)
551 goto error;
552 }
553 } else
554 pos_adj = 0;
555
556 for (i = 0; i < periods; i++) {
557 if (i == periods - 1 && pos_ad
558 ofs = setup_bdle(bus,
559 &bdl,
560 else
561 ofs = setup_bdle(bus,
562 &bdl,
563 !azx_
564 if (ofs < 0)
565 goto error;
566 }
567 return 0;
568
569 error:
570 dev_dbg(bus->dev, "Too many BDL entrie
571 azx_dev->bufsize, period_bytes
572 return -EINVAL;
573 }
574 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_period
575
576 /**
577 * snd_hdac_stream_set_params - set stream par
578 * @azx_dev: HD-audio core stream for which pa
579 * @format_val: format value parameter
580 *
581 * Setup the HD-audio core stream parameters f
582 * and passed format value
583 */
584 int snd_hdac_stream_set_params(struct hdac_str
585 unsigned int
586 {
587 struct snd_pcm_substream *substream =
588 struct snd_compr_stream *cstream = azx
589 unsigned int bufsize, period_bytes;
590 unsigned int no_period_wakeup;
591 int err;
592
593 if (substream) {
594 bufsize = snd_pcm_lib_buffer_b
595 period_bytes = snd_pcm_lib_per
596 no_period_wakeup = substream->
597 } else if (cstream) {
598 bufsize = cstream->runtime->bu
599 period_bytes = cstream->runtim
600 no_period_wakeup = 0;
601 } else {
602 return -EINVAL;
603 }
604
605 if (bufsize != azx_dev->bufsize ||
606 period_bytes != azx_dev->period_by
607 format_val != azx_dev->format_val
608 no_period_wakeup != azx_dev->no_pe
609 azx_dev->bufsize = bufsize;
610 azx_dev->period_bytes = period
611 azx_dev->format_val = format_v
612 azx_dev->no_period_wakeup = no
613 err = snd_hdac_stream_setup_pe
614 if (err < 0)
615 return err;
616 }
617 return 0;
618 }
619 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params);
620
621 static u64 azx_cc_read(const struct cyclecount
622 {
623 struct hdac_stream *azx_dev = containe
624
625 return snd_hdac_chip_readl(azx_dev->bu
626 }
627
628 static void azx_timecounter_init(struct hdac_s
629 bool force, u
630 {
631 struct timecounter *tc = &azx_dev->tc;
632 struct cyclecounter *cc = &azx_dev->cc
633 u64 nsec;
634
635 cc->read = azx_cc_read;
636 cc->mask = CLOCKSOURCE_MASK(32);
637
638 /*
639 * Calculate the optimal mult/shift va
640 * around after ~178.9 seconds.
641 */
642 clocks_calc_mult_shift(&cc->mult, &cc-
643 NSEC_PER_SEC, 1
644
645 nsec = 0; /* audio time is elapsed tim
646 timecounter_init(tc, cc, nsec);
647 if (force) {
648 /*
649 * force timecounter to use pr
650 * used for synchronized start
651 */
652 tc->cycle_last = last;
653 }
654 }
655
656 /**
657 * snd_hdac_stream_timecounter_init - initiali
658 * @azx_dev: HD-audio core stream (master stre
659 * @streams: bit flags of streams to set up
660 * @start: true for PCM trigger start, false f
661 *
662 * Initializes the time counter of streams mar
663 * bit corresponds to the stream index).
664 * The trigger timestamp of PCM substream assi
665 * updated accordingly, too.
666 */
667 void snd_hdac_stream_timecounter_init(struct h
668 unsigned
669 {
670 struct hdac_bus *bus = azx_dev->bus;
671 struct snd_pcm_runtime *runtime = azx_
672 struct hdac_stream *s;
673 bool inited = false;
674 u64 cycle_last = 0;
675
676 if (!start)
677 goto skip;
678
679 list_for_each_entry(s, &bus->stream_li
680 if ((streams & (1 << s->index)
681 azx_timecounter_init(s
682 if (!inited) {
683 inited = true;
684 cycle_last = s
685 }
686 }
687 }
688
689 skip:
690 snd_pcm_gettime(runtime, &runtime->tri
691 runtime->trigger_tstamp_latched = true
692 }
693 EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_
694
695 /**
696 * snd_hdac_stream_sync_trigger - turn on/off
697 * @azx_dev: HD-audio core stream (master stre
698 * @set: true = set, false = clear
699 * @streams: bit flags of streams to sync
700 * @reg: the stream sync register address
701 */
702 void snd_hdac_stream_sync_trigger(struct hdac_
703 unsigned int
704 {
705 struct hdac_bus *bus = azx_dev->bus;
706 unsigned int val;
707
708 if (!reg)
709 reg = AZX_REG_SSYNC;
710 val = _snd_hdac_chip_readl(bus, reg);
711 if (set)
712 val |= streams;
713 else
714 val &= ~streams;
715 _snd_hdac_chip_writel(bus, reg, val);
716 }
717 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger
718
719 /**
720 * snd_hdac_stream_sync - sync with start/stop
721 * @azx_dev: HD-audio core stream (master stre
722 * @start: true = start, false = stop
723 * @streams: bit flags of streams to sync
724 *
725 * For @start = true, wait until all FIFOs get
726 * For @start = false, wait until all RUN bits
727 */
728 void snd_hdac_stream_sync(struct hdac_stream *
729 unsigned int streams
730 {
731 struct hdac_bus *bus = azx_dev->bus;
732 int nwait, timeout;
733 struct hdac_stream *s;
734
735 for (timeout = 5000; timeout; timeout-
736 nwait = 0;
737 list_for_each_entry(s, &bus->s
738 if (!(streams & (1 <<
739 continue;
740
741 if (start) {
742 /* check FIFO
743 if (!(snd_hdac
744 SD_STS_F
745 nwait+
746 } else {
747 /* check RUN b
748 if (snd_hdac_s
749 SD_CTL_DMA
750 nwait+
751 /*
752 * Per
753 * bit
754 */
755 if (ti
756
757 }
758 }
759 }
760 if (!nwait)
761 break;
762 cpu_relax();
763 }
764 }
765 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync);
766
767 /**
768 * snd_hdac_stream_spbcap_enable - enable SPIB
769 * @bus: HD-audio core bus
770 * @enable: flag to enable/disable SPIB
771 * @index: stream index for which SPIB need to
772 */
773 void snd_hdac_stream_spbcap_enable(struct hdac
774 bool enable
775 {
776 u32 mask = 0;
777
778 if (!bus->spbcap) {
779 dev_err(bus->dev, "Address of
780 return;
781 }
782
783 mask |= (1 << index);
784
785 if (enable)
786 snd_hdac_updatel(bus->spbcap,
787 else
788 snd_hdac_updatel(bus->spbcap,
789 }
790 EXPORT_SYMBOL_GPL(snd_hdac_stream_spbcap_enabl
791
792 /**
793 * snd_hdac_stream_set_spib - sets the spib va
794 * @bus: HD-audio core bus
795 * @azx_dev: hdac_stream
796 * @value: spib value to set
797 */
798 int snd_hdac_stream_set_spib(struct hdac_bus *
799 struct hdac_strea
800 {
801 if (!bus->spbcap) {
802 dev_err(bus->dev, "Address of
803 return -EINVAL;
804 }
805
806 writel(value, azx_dev->spib_addr);
807
808 return 0;
809 }
810 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_spib);
811
812 /**
813 * snd_hdac_stream_get_spbmaxfifo - gets the s
814 * @bus: HD-audio core bus
815 * @azx_dev: hdac_stream
816 *
817 * Return maxfifo for the stream
818 */
819 int snd_hdac_stream_get_spbmaxfifo(struct hdac
820 struct hdac
821 {
822 if (!bus->spbcap) {
823 dev_err(bus->dev, "Address of
824 return -EINVAL;
825 }
826
827 return readl(azx_dev->fifo_addr);
828 }
829 EXPORT_SYMBOL_GPL(snd_hdac_stream_get_spbmaxfi
830
831 /**
832 * snd_hdac_stream_drsm_enable - enable DMA re
833 * @bus: HD-audio core bus
834 * @enable: flag to enable/disable DRSM
835 * @index: stream index for which DRSM need to
836 */
837 void snd_hdac_stream_drsm_enable(struct hdac_b
838 bool enable,
839 {
840 u32 mask = 0;
841
842 if (!bus->drsmcap) {
843 dev_err(bus->dev, "Address of
844 return;
845 }
846
847 mask |= (1 << index);
848
849 if (enable)
850 snd_hdac_updatel(bus->drsmcap,
851 else
852 snd_hdac_updatel(bus->drsmcap,
853 }
854 EXPORT_SYMBOL_GPL(snd_hdac_stream_drsm_enable)
855
856 /*
857 * snd_hdac_stream_wait_drsm - wait for HW to
858 * @azx_dev: HD-audio core stream to await RSM
859 *
860 * Returns 0 on success and -ETIMEDOUT upon a
861 */
862 int snd_hdac_stream_wait_drsm(struct hdac_stre
863 {
864 struct hdac_bus *bus = azx_dev->bus;
865 u32 mask, reg;
866 int ret;
867
868 mask = 1 << azx_dev->index;
869
870 ret = read_poll_timeout(snd_hdac_reg_r
871 bus->drsmcap +
872 if (ret)
873 dev_dbg(bus->dev, "polling RSM
874 return ret;
875 }
876 EXPORT_SYMBOL_GPL(snd_hdac_stream_wait_drsm);
877
878 /**
879 * snd_hdac_stream_set_dpibr - sets the dpibr
880 * @bus: HD-audio core bus
881 * @azx_dev: hdac_stream
882 * @value: dpib value to set
883 */
884 int snd_hdac_stream_set_dpibr(struct hdac_bus
885 struct hdac_stre
886 {
887 if (!bus->drsmcap) {
888 dev_err(bus->dev, "Address of
889 return -EINVAL;
890 }
891
892 writel(value, azx_dev->dpibr_addr);
893
894 return 0;
895 }
896 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_dpibr);
897
898 /**
899 * snd_hdac_stream_set_lpib - sets the lpib va
900 * @azx_dev: hdac_stream
901 * @value: lpib value to set
902 */
903 int snd_hdac_stream_set_lpib(struct hdac_strea
904 {
905 snd_hdac_stream_writel(azx_dev, SD_LPI
906
907 return 0;
908 }
909 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_lpib);
910
911 #ifdef CONFIG_SND_HDA_DSP_LOADER
912 /**
913 * snd_hdac_dsp_prepare - prepare for DSP load
914 * @azx_dev: HD-audio core stream used for DSP
915 * @format: HD-audio stream format
916 * @byte_size: data chunk byte size
917 * @bufp: allocated buffer
918 *
919 * Allocate the buffer for the given size and
920 * DSP loading. Returns the stream tag (>= 0)
921 */
922 int snd_hdac_dsp_prepare(struct hdac_stream *a
923 unsigned int byte_siz
924 {
925 struct hdac_bus *bus = azx_dev->bus;
926 __le32 *bdl;
927 int err;
928
929 snd_hdac_dsp_lock(azx_dev);
930 spin_lock_irq(&bus->reg_lock);
931 if (azx_dev->running || azx_dev->locke
932 spin_unlock_irq(&bus->reg_lock
933 err = -EBUSY;
934 goto unlock;
935 }
936 azx_dev->locked = true;
937 spin_unlock_irq(&bus->reg_lock);
938
939 err = snd_dma_alloc_pages(SNDRV_DMA_TY
940 byte_size, b
941 if (err < 0)
942 goto err_alloc;
943
944 azx_dev->substream = NULL;
945 azx_dev->bufsize = byte_size;
946 azx_dev->period_bytes = byte_size;
947 azx_dev->format_val = format;
948
949 snd_hdac_stream_reset(azx_dev);
950
951 /* reset BDL address */
952 snd_hdac_stream_writel(azx_dev, SD_BDL
953 snd_hdac_stream_writel(azx_dev, SD_BDL
954
955 azx_dev->frags = 0;
956 bdl = (__le32 *)azx_dev->bdl.area;
957 err = setup_bdle(bus, bufp, azx_dev, &
958 if (err < 0)
959 goto error;
960
961 snd_hdac_stream_setup(azx_dev, true);
962 snd_hdac_dsp_unlock(azx_dev);
963 return azx_dev->stream_tag;
964
965 error:
966 snd_dma_free_pages(bufp);
967 err_alloc:
968 spin_lock_irq(&bus->reg_lock);
969 azx_dev->locked = false;
970 spin_unlock_irq(&bus->reg_lock);
971 unlock:
972 snd_hdac_dsp_unlock(azx_dev);
973 return err;
974 }
975 EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare);
976
977 /**
978 * snd_hdac_dsp_trigger - start / stop DSP loa
979 * @azx_dev: HD-audio core stream used for DSP
980 * @start: trigger start or stop
981 */
982 void snd_hdac_dsp_trigger(struct hdac_stream *
983 {
984 if (start)
985 snd_hdac_stream_start(azx_dev)
986 else
987 snd_hdac_stream_stop(azx_dev);
988 }
989 EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger);
990
991 /**
992 * snd_hdac_dsp_cleanup - clean up the stream
993 * @azx_dev: HD-audio core stream used for DSP
994 * @dmab: buffer used by DSP loading
995 */
996 void snd_hdac_dsp_cleanup(struct hdac_stream *
997 struct snd_dma_buffe
998 {
999 struct hdac_bus *bus = azx_dev->bus;
1000
1001 if (!dmab->area || !azx_dev->locked)
1002 return;
1003
1004 snd_hdac_dsp_lock(azx_dev);
1005 /* reset BDL address */
1006 snd_hdac_stream_writel(azx_dev, SD_BD
1007 snd_hdac_stream_writel(azx_dev, SD_BD
1008 snd_hdac_stream_writel(azx_dev, SD_CT
1009 azx_dev->bufsize = 0;
1010 azx_dev->period_bytes = 0;
1011 azx_dev->format_val = 0;
1012
1013 snd_dma_free_pages(dmab);
1014 dmab->area = NULL;
1015
1016 spin_lock_irq(&bus->reg_lock);
1017 azx_dev->locked = false;
1018 spin_unlock_irq(&bus->reg_lock);
1019 snd_hdac_dsp_unlock(azx_dev);
1020 }
1021 EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup);
1022 #endif /* CONFIG_SND_HDA_DSP_LOADER */
1023
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