1 // SPDX-License-Identifier: GPL-2.0-only <<
2 /* 1 /*
3 * HD-audio stream operations 2 * HD-audio stream operations
4 */ 3 */
5 4
6 #include <linux/kernel.h> 5 #include <linux/kernel.h>
7 #include <linux/delay.h> 6 #include <linux/delay.h>
8 #include <linux/export.h> 7 #include <linux/export.h>
9 #include <linux/clocksource.h> 8 #include <linux/clocksource.h>
10 #include <sound/compress_driver.h> <<
11 #include <sound/core.h> 9 #include <sound/core.h>
12 #include <sound/pcm.h> 10 #include <sound/pcm.h>
13 #include <sound/hdaudio.h> 11 #include <sound/hdaudio.h>
14 #include <sound/hda_register.h> 12 #include <sound/hda_register.h>
15 #include "trace.h" 13 #include "trace.h"
16 14
17 /* <<
18 * the hdac_stream library is intended to be u <<
19 * transitions. The states are not formally de <<
20 * inspired by boolean variables. Note that th <<
21 * in this library but by the callers during t <<
22 * <<
23 * | <<
24 * stream_init() | <<
25 * v <<
26 * +--+-------+ <<
27 * | unused | <<
28 * +--+----+--+ <<
29 * | ^ <<
30 * stream_assign() | | stream_re <<
31 * v | <<
32 * +--+----+--+ <<
33 * | opened | <<
34 * +--+----+--+ <<
35 * | ^ <<
36 * stream_reset() | | <<
37 * stream_setup() | | stream_cl <<
38 * v | <<
39 * +--+----+--+ <<
40 * | prepared | <<
41 * +--+----+--+ <<
42 * | ^ <<
43 * stream_start() | | stream_st <<
44 * v | <<
45 * +--+----+--+ <<
46 * | running | <<
47 * +----------+ <<
48 */ <<
49 <<
50 /** <<
51 * snd_hdac_get_stream_stripe_ctl - get stripe <<
52 * @bus: HD-audio core bus <<
53 * @substream: PCM substream <<
54 */ <<
55 int snd_hdac_get_stream_stripe_ctl(struct hdac <<
56 struct snd_ <<
57 { <<
58 struct snd_pcm_runtime *runtime = subs <<
59 unsigned int channels = runtime->chann <<
60 rate = runtime->rate, <<
61 bits_per_sample = runtime <<
62 max_sdo_lines, value, sdo <<
63 <<
64 /* T_AZA_GCAP_NSDO is 1:2 bitfields in <<
65 max_sdo_lines = snd_hdac_chip_readl(bu <<
66 <<
67 /* following is from HD audio spec */ <<
68 for (sdo_line = max_sdo_lines; sdo_lin <<
69 if (rate > 48000) <<
70 value = (channels * bi <<
71 (rate <<
72 else <<
73 value = (channels * bi <<
74 <<
75 if (value >= bus->sdo_limit) <<
76 break; <<
77 } <<
78 <<
79 /* stripe value: 0 for 1SDO, 1 for 2SD <<
80 return sdo_line >> 1; <<
81 } <<
82 EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_c <<
83 <<
84 /** 15 /**
85 * snd_hdac_stream_init - initialize each stre 16 * snd_hdac_stream_init - initialize each stream (aka device)
86 * @bus: HD-audio core bus 17 * @bus: HD-audio core bus
87 * @azx_dev: HD-audio core stream object to in 18 * @azx_dev: HD-audio core stream object to initialize
88 * @idx: stream index number 19 * @idx: stream index number
89 * @direction: stream direction (SNDRV_PCM_STR 20 * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE)
90 * @tag: the tag id to assign 21 * @tag: the tag id to assign
91 * 22 *
92 * Assign the starting bdl address to each str 23 * Assign the starting bdl address to each stream (device) and initialize.
93 */ 24 */
94 void snd_hdac_stream_init(struct hdac_bus *bus 25 void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
95 int idx, int directi 26 int idx, int direction, int tag)
96 { 27 {
97 azx_dev->bus = bus; 28 azx_dev->bus = bus;
98 /* offset: SDI0=0x80, SDI1=0xa0, ... S 29 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
99 azx_dev->sd_addr = bus->remap_addr + ( 30 azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80);
100 /* int mask: SDI0=0x01, SDI1=0x02, ... 31 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
101 azx_dev->sd_int_sta_mask = 1 << idx; 32 azx_dev->sd_int_sta_mask = 1 << idx;
102 azx_dev->index = idx; 33 azx_dev->index = idx;
103 azx_dev->direction = direction; 34 azx_dev->direction = direction;
104 azx_dev->stream_tag = tag; 35 azx_dev->stream_tag = tag;
105 snd_hdac_dsp_lock_init(azx_dev); 36 snd_hdac_dsp_lock_init(azx_dev);
106 list_add_tail(&azx_dev->list, &bus->st 37 list_add_tail(&azx_dev->list, &bus->stream_list);
107 <<
108 if (bus->spbcap) { <<
109 azx_dev->spib_addr = bus->spbc <<
110 AZX_SP <<
111 AZX_SP <<
112 <<
113 azx_dev->fifo_addr = bus->spbc <<
114 AZX_SP <<
115 AZX_SP <<
116 } <<
117 <<
118 if (bus->drsmcap) <<
119 azx_dev->dpibr_addr = bus->drs <<
120 AZX_DR <<
121 } 38 }
122 EXPORT_SYMBOL_GPL(snd_hdac_stream_init); 39 EXPORT_SYMBOL_GPL(snd_hdac_stream_init);
123 40
124 /** 41 /**
125 * snd_hdac_stream_start - start a stream 42 * snd_hdac_stream_start - start a stream
126 * @azx_dev: HD-audio core stream to start 43 * @azx_dev: HD-audio core stream to start
>> 44 * @fresh_start: false = wallclock timestamp relative to period wallclock
127 * 45 *
128 * Start a stream, set start_wallclk and set t 46 * Start a stream, set start_wallclk and set the running flag.
129 */ 47 */
130 void snd_hdac_stream_start(struct hdac_stream !! 48 void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start)
131 { 49 {
132 struct hdac_bus *bus = azx_dev->bus; 50 struct hdac_bus *bus = azx_dev->bus;
133 int stripe_ctl; <<
134 51
135 trace_snd_hdac_stream_start(bus, azx_d 52 trace_snd_hdac_stream_start(bus, azx_dev);
136 53
137 azx_dev->start_wallclk = snd_hdac_chip 54 azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK);
>> 55 if (!fresh_start)
>> 56 azx_dev->start_wallclk -= azx_dev->period_wallclk;
138 57
139 /* enable SIE */ 58 /* enable SIE */
140 snd_hdac_chip_updatel(bus, INTCTL, !! 59 snd_hdac_chip_updatel(bus, INTCTL, 0, 1 << azx_dev->index);
141 1 << azx_dev->in <<
142 1 << azx_dev->in <<
143 /* set stripe control */ <<
144 if (azx_dev->stripe) { <<
145 if (azx_dev->substream) <<
146 stripe_ctl = snd_hdac_ <<
147 else <<
148 stripe_ctl = 0; <<
149 snd_hdac_stream_updateb(azx_de <<
150 stripe <<
151 } <<
152 /* set DMA start and interrupt mask */ 60 /* set DMA start and interrupt mask */
153 if (bus->access_sdnctl_in_dword) !! 61 snd_hdac_stream_updateb(azx_dev, SD_CTL,
154 snd_hdac_stream_updatel(azx_de <<
155 0, SD_CTL_DMA_ <<
156 else <<
157 snd_hdac_stream_updateb(azx_de <<
158 0, SD_CTL_DMA_ 62 0, SD_CTL_DMA_START | SD_INT_MASK);
159 azx_dev->running = true; 63 azx_dev->running = true;
160 } 64 }
161 EXPORT_SYMBOL_GPL(snd_hdac_stream_start); 65 EXPORT_SYMBOL_GPL(snd_hdac_stream_start);
162 66
163 /** 67 /**
164 * snd_hdac_stream_clear - helper to clear str !! 68 * snd_hdac_stream_clear - stop a stream DMA
165 * @azx_dev: HD-audio core stream to stop 69 * @azx_dev: HD-audio core stream to stop
166 */ 70 */
167 static void snd_hdac_stream_clear(struct hdac_ !! 71 void snd_hdac_stream_clear(struct hdac_stream *azx_dev)
168 { 72 {
169 snd_hdac_stream_updateb(azx_dev, SD_CT 73 snd_hdac_stream_updateb(azx_dev, SD_CTL,
170 SD_CTL_DMA_STA 74 SD_CTL_DMA_START | SD_INT_MASK, 0);
171 snd_hdac_stream_writeb(azx_dev, SD_STS 75 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
172 if (azx_dev->stripe) <<
173 snd_hdac_stream_updateb(azx_de <<
174 azx_dev->running = false; 76 azx_dev->running = false;
175 } 77 }
>> 78 EXPORT_SYMBOL_GPL(snd_hdac_stream_clear);
176 79
177 /** 80 /**
178 * snd_hdac_stream_stop - stop a stream 81 * snd_hdac_stream_stop - stop a stream
179 * @azx_dev: HD-audio core stream to stop 82 * @azx_dev: HD-audio core stream to stop
180 * 83 *
181 * Stop a stream DMA and disable stream interr 84 * Stop a stream DMA and disable stream interrupt
182 */ 85 */
183 void snd_hdac_stream_stop(struct hdac_stream * 86 void snd_hdac_stream_stop(struct hdac_stream *azx_dev)
184 { 87 {
185 trace_snd_hdac_stream_stop(azx_dev->bu 88 trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev);
186 89
187 snd_hdac_stream_clear(azx_dev); 90 snd_hdac_stream_clear(azx_dev);
188 /* disable SIE */ 91 /* disable SIE */
189 snd_hdac_chip_updatel(azx_dev->bus, IN 92 snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0);
190 } 93 }
191 EXPORT_SYMBOL_GPL(snd_hdac_stream_stop); 94 EXPORT_SYMBOL_GPL(snd_hdac_stream_stop);
192 95
193 /** 96 /**
194 * snd_hdac_stop_streams - stop all streams <<
195 * @bus: HD-audio core bus <<
196 */ <<
197 void snd_hdac_stop_streams(struct hdac_bus *bu <<
198 { <<
199 struct hdac_stream *stream; <<
200 <<
201 list_for_each_entry(stream, &bus->stre <<
202 snd_hdac_stream_stop(stream); <<
203 } <<
204 EXPORT_SYMBOL_GPL(snd_hdac_stop_streams); <<
205 <<
206 /** <<
207 * snd_hdac_stop_streams_and_chip - stop all s <<
208 * @bus: HD-audio core bus <<
209 */ <<
210 void snd_hdac_stop_streams_and_chip(struct hda <<
211 { <<
212 <<
213 if (bus->chip_init) { <<
214 snd_hdac_stop_streams(bus); <<
215 snd_hdac_bus_stop_chip(bus); <<
216 } <<
217 } <<
218 EXPORT_SYMBOL_GPL(snd_hdac_stop_streams_and_ch <<
219 <<
220 /** <<
221 * snd_hdac_stream_reset - reset a stream 97 * snd_hdac_stream_reset - reset a stream
222 * @azx_dev: HD-audio core stream to reset 98 * @azx_dev: HD-audio core stream to reset
223 */ 99 */
224 void snd_hdac_stream_reset(struct hdac_stream 100 void snd_hdac_stream_reset(struct hdac_stream *azx_dev)
225 { 101 {
226 unsigned char val; 102 unsigned char val;
227 int dma_run_state; !! 103 int timeout;
228 104
229 snd_hdac_stream_clear(azx_dev); 105 snd_hdac_stream_clear(azx_dev);
230 106
231 dma_run_state = snd_hdac_stream_readb( <<
232 <<
233 snd_hdac_stream_updateb(azx_dev, SD_CT 107 snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET);
234 !! 108 udelay(3);
235 /* wait for hardware to report that th !! 109 timeout = 300;
236 snd_hdac_stream_readb_poll(azx_dev, SD !! 110 do {
237 !! 111 val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
238 if (azx_dev->bus->dma_stop_delay && dm !! 112 SD_CTL_STREAM_RESET;
239 udelay(azx_dev->bus->dma_stop_ !! 113 if (val)
240 !! 114 break;
241 snd_hdac_stream_updateb(azx_dev, SD_CT !! 115 } while (--timeout);
242 !! 116 val &= ~SD_CTL_STREAM_RESET;
243 /* wait for hardware to report that th !! 117 snd_hdac_stream_writeb(azx_dev, SD_CTL, val);
244 snd_hdac_stream_readb_poll(azx_dev, SD !! 118 udelay(3);
>> 119
>> 120 timeout = 300;
>> 121 /* waiting for hardware to report that the stream is out of reset */
>> 122 do {
>> 123 val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
>> 124 SD_CTL_STREAM_RESET;
>> 125 if (!val)
>> 126 break;
>> 127 } while (--timeout);
245 128
246 /* reset first position - may not be s 129 /* reset first position - may not be synced with hw at this time */
247 if (azx_dev->posbuf) 130 if (azx_dev->posbuf)
248 *azx_dev->posbuf = 0; 131 *azx_dev->posbuf = 0;
249 } 132 }
250 EXPORT_SYMBOL_GPL(snd_hdac_stream_reset); 133 EXPORT_SYMBOL_GPL(snd_hdac_stream_reset);
251 134
252 /** 135 /**
253 * snd_hdac_stream_setup - set up the SD for 136 * snd_hdac_stream_setup - set up the SD for streaming
254 * @azx_dev: HD-audio core stream to set up 137 * @azx_dev: HD-audio core stream to set up
255 * @code_loading: Whether the stream is for PC <<
256 */ 138 */
257 int snd_hdac_stream_setup(struct hdac_stream * !! 139 int snd_hdac_stream_setup(struct hdac_stream *azx_dev)
258 { 140 {
259 struct hdac_bus *bus = azx_dev->bus; 141 struct hdac_bus *bus = azx_dev->bus;
260 struct snd_pcm_runtime *runtime; 142 struct snd_pcm_runtime *runtime;
261 unsigned int val; 143 unsigned int val;
262 u16 reg; <<
263 int ret; <<
264 144
265 if (azx_dev->substream) 145 if (azx_dev->substream)
266 runtime = azx_dev->substream-> 146 runtime = azx_dev->substream->runtime;
267 else 147 else
268 runtime = NULL; 148 runtime = NULL;
269 /* make sure the run bit is zero for S 149 /* make sure the run bit is zero for SD */
270 snd_hdac_stream_clear(azx_dev); 150 snd_hdac_stream_clear(azx_dev);
271 /* program the stream_tag */ 151 /* program the stream_tag */
272 val = snd_hdac_stream_readl(azx_dev, S 152 val = snd_hdac_stream_readl(azx_dev, SD_CTL);
273 val = (val & ~SD_CTL_STREAM_TAG_MASK) 153 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
274 (azx_dev->stream_tag << SD_CTL 154 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
275 if (!bus->snoop) 155 if (!bus->snoop)
276 val |= SD_CTL_TRAFFIC_PRIO; 156 val |= SD_CTL_TRAFFIC_PRIO;
277 snd_hdac_stream_writel(azx_dev, SD_CTL 157 snd_hdac_stream_writel(azx_dev, SD_CTL, val);
278 158
279 /* program the length of samples in cy 159 /* program the length of samples in cyclic buffer */
280 snd_hdac_stream_writel(azx_dev, SD_CBL 160 snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize);
281 161
282 /* program the stream format */ 162 /* program the stream format */
283 /* this value needs to be the same as 163 /* this value needs to be the same as the one programmed */
284 snd_hdac_stream_writew(azx_dev, SD_FOR 164 snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
285 165
286 /* program the stream LVI (last valid 166 /* program the stream LVI (last valid index) of the BDL */
287 snd_hdac_stream_writew(azx_dev, SD_LVI 167 snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
288 168
289 /* program the BDL address */ 169 /* program the BDL address */
290 /* lower BDL address */ 170 /* lower BDL address */
291 snd_hdac_stream_writel(azx_dev, SD_BDL 171 snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
292 /* upper BDL address */ 172 /* upper BDL address */
293 snd_hdac_stream_writel(azx_dev, SD_BDL 173 snd_hdac_stream_writel(azx_dev, SD_BDLPU,
294 upper_32_bits(a 174 upper_32_bits(azx_dev->bdl.addr));
295 175
296 /* enable the position buffer */ 176 /* enable the position buffer */
297 if (bus->use_posbuf && bus->posbuf.add 177 if (bus->use_posbuf && bus->posbuf.addr) {
298 if (!(snd_hdac_chip_readl(bus, 178 if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE))
299 snd_hdac_chip_writel(b 179 snd_hdac_chip_writel(bus, DPLBASE,
300 (u32)bus->posb 180 (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE);
301 } 181 }
302 182
303 /* set the interrupt enable bits in th 183 /* set the interrupt enable bits in the descriptor control register */
304 snd_hdac_stream_updatel(azx_dev, SD_CT 184 snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK);
305 185
306 if (!code_loading) { !! 186 if (azx_dev->direction == SNDRV_PCM_STREAM_PLAYBACK)
307 /* Once SDxFMT is set, the con !! 187 azx_dev->fifo_size =
308 ret = snd_hdac_stream_readw_po !! 188 snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1;
309 !! 189 else
310 if (ret) !! 190 azx_dev->fifo_size = 0;
311 dev_dbg(bus->dev, "pol <<
312 AZX_REG_SD_FIF <<
313 azx_dev->fifo_size = reg; <<
314 } <<
315 191
316 /* when LPIB delay correction gives a 192 /* when LPIB delay correction gives a small negative value,
317 * we ignore it; currently set the thr 193 * we ignore it; currently set the threshold statically to
318 * 64 frames 194 * 64 frames
319 */ 195 */
320 if (runtime && runtime->period_size > 196 if (runtime && runtime->period_size > 64)
321 azx_dev->delay_negative_thresh 197 azx_dev->delay_negative_threshold =
322 -frames_to_bytes(runti 198 -frames_to_bytes(runtime, 64);
323 else 199 else
324 azx_dev->delay_negative_thresh 200 azx_dev->delay_negative_threshold = 0;
325 201
326 /* wallclk has 24Mhz clock source */ 202 /* wallclk has 24Mhz clock source */
327 if (runtime) 203 if (runtime)
328 azx_dev->period_wallclk = (((r 204 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
329 runtime->r 205 runtime->rate) * 1000);
330 206
331 return 0; 207 return 0;
332 } 208 }
333 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup); 209 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup);
334 210
335 /** 211 /**
336 * snd_hdac_stream_cleanup - cleanup a stream 212 * snd_hdac_stream_cleanup - cleanup a stream
337 * @azx_dev: HD-audio core stream to clean up 213 * @azx_dev: HD-audio core stream to clean up
338 */ 214 */
339 void snd_hdac_stream_cleanup(struct hdac_strea 215 void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev)
340 { 216 {
341 snd_hdac_stream_writel(azx_dev, SD_BDL 217 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
342 snd_hdac_stream_writel(azx_dev, SD_BDL 218 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
343 snd_hdac_stream_writel(azx_dev, SD_CTL 219 snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
344 azx_dev->bufsize = 0; 220 azx_dev->bufsize = 0;
345 azx_dev->period_bytes = 0; 221 azx_dev->period_bytes = 0;
346 azx_dev->format_val = 0; 222 azx_dev->format_val = 0;
347 } 223 }
348 EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup); 224 EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup);
349 225
350 /** 226 /**
351 * snd_hdac_stream_assign - assign a stream fo 227 * snd_hdac_stream_assign - assign a stream for the PCM
352 * @bus: HD-audio core bus 228 * @bus: HD-audio core bus
353 * @substream: PCM substream to assign 229 * @substream: PCM substream to assign
354 * 230 *
355 * Look for an unused stream for the given PCM 231 * Look for an unused stream for the given PCM substream, assign it
356 * and return the stream object. If no stream 232 * and return the stream object. If no stream is free, returns NULL.
357 * The function tries to keep using the same s 233 * The function tries to keep using the same stream object when it's used
358 * beforehand. Also, when bus->reverse_assign 234 * beforehand. Also, when bus->reverse_assign flag is set, the last free
359 * or matching entry is returned. This is nee 235 * or matching entry is returned. This is needed for some strange codecs.
360 */ 236 */
361 struct hdac_stream *snd_hdac_stream_assign(str 237 struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
362 str 238 struct snd_pcm_substream *substream)
363 { 239 {
364 struct hdac_stream *azx_dev; 240 struct hdac_stream *azx_dev;
365 struct hdac_stream *res = NULL; 241 struct hdac_stream *res = NULL;
366 242
367 /* make a non-zero unique key for the 243 /* make a non-zero unique key for the substream */
368 int key = (substream->number << 2) | ( !! 244 int key = (substream->pcm->device << 16) | (substream->number << 2) |
369 !! 245 (substream->stream + 1);
370 if (substream->pcm) <<
371 key |= (substream->pcm->device <<
372 246
373 spin_lock_irq(&bus->reg_lock); <<
374 list_for_each_entry(azx_dev, &bus->str 247 list_for_each_entry(azx_dev, &bus->stream_list, list) {
375 if (azx_dev->direction != subs 248 if (azx_dev->direction != substream->stream)
376 continue; 249 continue;
377 if (azx_dev->opened) 250 if (azx_dev->opened)
378 continue; 251 continue;
379 if (azx_dev->assigned_key == k 252 if (azx_dev->assigned_key == key) {
380 res = azx_dev; 253 res = azx_dev;
381 break; 254 break;
382 } 255 }
383 if (!res || bus->reverse_assig 256 if (!res || bus->reverse_assign)
384 res = azx_dev; 257 res = azx_dev;
385 } 258 }
386 if (res) { 259 if (res) {
>> 260 spin_lock_irq(&bus->reg_lock);
387 res->opened = 1; 261 res->opened = 1;
388 res->running = 0; 262 res->running = 0;
389 res->assigned_key = key; 263 res->assigned_key = key;
390 res->substream = substream; 264 res->substream = substream;
>> 265 spin_unlock_irq(&bus->reg_lock);
391 } 266 }
392 spin_unlock_irq(&bus->reg_lock); <<
393 return res; 267 return res;
394 } 268 }
395 EXPORT_SYMBOL_GPL(snd_hdac_stream_assign); 269 EXPORT_SYMBOL_GPL(snd_hdac_stream_assign);
396 270
397 /** 271 /**
398 * snd_hdac_stream_release_locked - release th <<
399 * @azx_dev: HD-audio core stream to release <<
400 * <<
401 * Release the stream that has been assigned b <<
402 * The bus->reg_lock needs to be taken at a hi <<
403 */ <<
404 void snd_hdac_stream_release_locked(struct hda <<
405 { <<
406 azx_dev->opened = 0; <<
407 azx_dev->running = 0; <<
408 azx_dev->substream = NULL; <<
409 } <<
410 EXPORT_SYMBOL_GPL(snd_hdac_stream_release_lock <<
411 <<
412 /** <<
413 * snd_hdac_stream_release - release the assig 272 * snd_hdac_stream_release - release the assigned stream
414 * @azx_dev: HD-audio core stream to release 273 * @azx_dev: HD-audio core stream to release
415 * 274 *
416 * Release the stream that has been assigned b 275 * Release the stream that has been assigned by snd_hdac_stream_assign().
417 */ 276 */
418 void snd_hdac_stream_release(struct hdac_strea 277 void snd_hdac_stream_release(struct hdac_stream *azx_dev)
419 { 278 {
420 struct hdac_bus *bus = azx_dev->bus; 279 struct hdac_bus *bus = azx_dev->bus;
421 280
422 spin_lock_irq(&bus->reg_lock); 281 spin_lock_irq(&bus->reg_lock);
423 snd_hdac_stream_release_locked(azx_dev !! 282 azx_dev->opened = 0;
>> 283 azx_dev->running = 0;
>> 284 azx_dev->substream = NULL;
424 spin_unlock_irq(&bus->reg_lock); 285 spin_unlock_irq(&bus->reg_lock);
425 } 286 }
426 EXPORT_SYMBOL_GPL(snd_hdac_stream_release); 287 EXPORT_SYMBOL_GPL(snd_hdac_stream_release);
427 288
428 /** 289 /**
429 * snd_hdac_get_stream - return hdac_stream ba 290 * snd_hdac_get_stream - return hdac_stream based on stream_tag and
430 * direction 291 * direction
431 * 292 *
432 * @bus: HD-audio core bus 293 * @bus: HD-audio core bus
433 * @dir: direction for the stream to be found 294 * @dir: direction for the stream to be found
434 * @stream_tag: stream tag for stream to be fo 295 * @stream_tag: stream tag for stream to be found
435 */ 296 */
436 struct hdac_stream *snd_hdac_get_stream(struct 297 struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
437 int di 298 int dir, int stream_tag)
438 { 299 {
439 struct hdac_stream *s; 300 struct hdac_stream *s;
440 301
441 list_for_each_entry(s, &bus->stream_li 302 list_for_each_entry(s, &bus->stream_list, list) {
442 if (s->direction == dir && s-> 303 if (s->direction == dir && s->stream_tag == stream_tag)
443 return s; 304 return s;
444 } 305 }
445 306
446 return NULL; 307 return NULL;
447 } 308 }
448 EXPORT_SYMBOL_GPL(snd_hdac_get_stream); 309 EXPORT_SYMBOL_GPL(snd_hdac_get_stream);
449 310
450 /* 311 /*
451 * set up a BDL entry 312 * set up a BDL entry
452 */ 313 */
453 static int setup_bdle(struct hdac_bus *bus, 314 static int setup_bdle(struct hdac_bus *bus,
454 struct snd_dma_buffer *d 315 struct snd_dma_buffer *dmab,
455 struct hdac_stream *azx_ 316 struct hdac_stream *azx_dev, __le32 **bdlp,
456 int ofs, int size, int w 317 int ofs, int size, int with_ioc)
457 { 318 {
458 __le32 *bdl = *bdlp; 319 __le32 *bdl = *bdlp;
459 320
460 while (size > 0) { 321 while (size > 0) {
461 dma_addr_t addr; 322 dma_addr_t addr;
462 int chunk; 323 int chunk;
463 324
464 if (azx_dev->frags >= AZX_MAX_ 325 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
465 return -EINVAL; 326 return -EINVAL;
466 327
467 addr = snd_sgbuf_get_addr(dmab 328 addr = snd_sgbuf_get_addr(dmab, ofs);
468 /* program the address field o 329 /* program the address field of the BDL entry */
469 bdl[0] = cpu_to_le32((u32)addr 330 bdl[0] = cpu_to_le32((u32)addr);
470 bdl[1] = cpu_to_le32(upper_32_ 331 bdl[1] = cpu_to_le32(upper_32_bits(addr));
471 /* program the size field of t 332 /* program the size field of the BDL entry */
472 chunk = snd_sgbuf_get_chunk_si 333 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
473 /* one BDLE cannot cross 4K bo 334 /* one BDLE cannot cross 4K boundary on CTHDA chips */
474 if (bus->align_bdle_4k) { 335 if (bus->align_bdle_4k) {
475 u32 remain = 0x1000 - 336 u32 remain = 0x1000 - (ofs & 0xfff);
476 337
477 if (chunk > remain) 338 if (chunk > remain)
478 chunk = remain 339 chunk = remain;
479 } 340 }
480 bdl[2] = cpu_to_le32(chunk); 341 bdl[2] = cpu_to_le32(chunk);
481 /* program the IOC to enable i 342 /* program the IOC to enable interrupt
482 * only when the whole fragmen 343 * only when the whole fragment is processed
483 */ 344 */
484 size -= chunk; 345 size -= chunk;
485 bdl[3] = (size || !with_ioc) ? 346 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
486 bdl += 4; 347 bdl += 4;
487 azx_dev->frags++; 348 azx_dev->frags++;
488 ofs += chunk; 349 ofs += chunk;
489 } 350 }
490 *bdlp = bdl; 351 *bdlp = bdl;
491 return ofs; 352 return ofs;
492 } 353 }
493 354
494 /** 355 /**
495 * snd_hdac_stream_setup_periods - set up BDL 356 * snd_hdac_stream_setup_periods - set up BDL entries
496 * @azx_dev: HD-audio core stream to set up 357 * @azx_dev: HD-audio core stream to set up
497 * 358 *
498 * Set up the buffer descriptor table of the g 359 * Set up the buffer descriptor table of the given stream based on the
499 * period and buffer sizes of the assigned PCM 360 * period and buffer sizes of the assigned PCM substream.
500 */ 361 */
501 int snd_hdac_stream_setup_periods(struct hdac_ 362 int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)
502 { 363 {
503 struct hdac_bus *bus = azx_dev->bus; 364 struct hdac_bus *bus = azx_dev->bus;
504 struct snd_pcm_substream *substream = 365 struct snd_pcm_substream *substream = azx_dev->substream;
505 struct snd_compr_stream *cstream = azx !! 366 struct snd_pcm_runtime *runtime = substream->runtime;
506 struct snd_pcm_runtime *runtime = NULL <<
507 struct snd_dma_buffer *dmab; <<
508 __le32 *bdl; 367 __le32 *bdl;
509 int i, ofs, periods, period_bytes; 368 int i, ofs, periods, period_bytes;
510 int pos_adj, pos_align; 369 int pos_adj, pos_align;
511 370
512 if (substream) { <<
513 runtime = substream->runtime; <<
514 dmab = snd_pcm_get_dma_buf(sub <<
515 } else if (cstream) { <<
516 dmab = snd_pcm_get_dma_buf(cst <<
517 } else { <<
518 WARN(1, "No substream or cstre <<
519 return -EINVAL; <<
520 } <<
521 <<
522 /* reset BDL address */ 371 /* reset BDL address */
523 snd_hdac_stream_writel(azx_dev, SD_BDL 372 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
524 snd_hdac_stream_writel(azx_dev, SD_BDL 373 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
525 374
526 period_bytes = azx_dev->period_bytes; 375 period_bytes = azx_dev->period_bytes;
527 periods = azx_dev->bufsize / period_by 376 periods = azx_dev->bufsize / period_bytes;
528 377
529 /* program the initial BDL entries */ 378 /* program the initial BDL entries */
530 bdl = (__le32 *)azx_dev->bdl.area; 379 bdl = (__le32 *)azx_dev->bdl.area;
531 ofs = 0; 380 ofs = 0;
532 azx_dev->frags = 0; 381 azx_dev->frags = 0;
533 382
534 pos_adj = bus->bdl_pos_adj; 383 pos_adj = bus->bdl_pos_adj;
535 if (runtime && !azx_dev->no_period_wak !! 384 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
536 pos_align = pos_adj; 385 pos_align = pos_adj;
537 pos_adj = DIV_ROUND_UP(pos_adj !! 386 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
538 if (!pos_adj) 387 if (!pos_adj)
539 pos_adj = pos_align; 388 pos_adj = pos_align;
540 else 389 else
541 pos_adj = roundup(pos_ !! 390 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
>> 391 pos_align;
542 pos_adj = frames_to_bytes(runt 392 pos_adj = frames_to_bytes(runtime, pos_adj);
543 if (pos_adj >= period_bytes) { 393 if (pos_adj >= period_bytes) {
544 dev_warn(bus->dev, "To 394 dev_warn(bus->dev, "Too big adjustment %d\n",
545 pos_adj); 395 pos_adj);
546 pos_adj = 0; 396 pos_adj = 0;
547 } else { 397 } else {
548 ofs = setup_bdle(bus, !! 398 ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
>> 399 azx_dev,
549 &bdl, 400 &bdl, ofs, pos_adj, true);
550 if (ofs < 0) 401 if (ofs < 0)
551 goto error; 402 goto error;
552 } 403 }
553 } else 404 } else
554 pos_adj = 0; 405 pos_adj = 0;
555 406
556 for (i = 0; i < periods; i++) { 407 for (i = 0; i < periods; i++) {
557 if (i == periods - 1 && pos_ad 408 if (i == periods - 1 && pos_adj)
558 ofs = setup_bdle(bus, !! 409 ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
559 &bdl, !! 410 azx_dev, &bdl, ofs,
>> 411 period_bytes - pos_adj, 0);
560 else 412 else
561 ofs = setup_bdle(bus, !! 413 ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
562 &bdl, !! 414 azx_dev, &bdl, ofs,
>> 415 period_bytes,
563 !azx_ 416 !azx_dev->no_period_wakeup);
564 if (ofs < 0) 417 if (ofs < 0)
565 goto error; 418 goto error;
566 } 419 }
567 return 0; 420 return 0;
568 421
569 error: 422 error:
570 dev_dbg(bus->dev, "Too many BDL entrie !! 423 dev_err(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n",
571 azx_dev->bufsize, period_bytes 424 azx_dev->bufsize, period_bytes);
572 return -EINVAL; 425 return -EINVAL;
573 } 426 }
574 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_period 427 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods);
575 428
576 /** 429 /**
577 * snd_hdac_stream_set_params - set stream par 430 * snd_hdac_stream_set_params - set stream parameters
578 * @azx_dev: HD-audio core stream for which pa 431 * @azx_dev: HD-audio core stream for which parameters are to be set
579 * @format_val: format value parameter 432 * @format_val: format value parameter
580 * 433 *
581 * Setup the HD-audio core stream parameters f 434 * Setup the HD-audio core stream parameters from substream of the stream
582 * and passed format value 435 * and passed format value
583 */ 436 */
584 int snd_hdac_stream_set_params(struct hdac_str 437 int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
585 unsigned int 438 unsigned int format_val)
586 { 439 {
587 struct snd_pcm_substream *substream = !! 440
588 struct snd_compr_stream *cstream = azx <<
589 unsigned int bufsize, period_bytes; 441 unsigned int bufsize, period_bytes;
590 unsigned int no_period_wakeup; !! 442 struct snd_pcm_substream *substream = azx_dev->substream;
>> 443 struct snd_pcm_runtime *runtime;
591 int err; 444 int err;
592 445
593 if (substream) { !! 446 if (!substream)
594 bufsize = snd_pcm_lib_buffer_b <<
595 period_bytes = snd_pcm_lib_per <<
596 no_period_wakeup = substream-> <<
597 } else if (cstream) { <<
598 bufsize = cstream->runtime->bu <<
599 period_bytes = cstream->runtim <<
600 no_period_wakeup = 0; <<
601 } else { <<
602 return -EINVAL; 447 return -EINVAL;
603 } !! 448 runtime = substream->runtime;
>> 449 bufsize = snd_pcm_lib_buffer_bytes(substream);
>> 450 period_bytes = snd_pcm_lib_period_bytes(substream);
604 451
605 if (bufsize != azx_dev->bufsize || 452 if (bufsize != azx_dev->bufsize ||
606 period_bytes != azx_dev->period_by 453 period_bytes != azx_dev->period_bytes ||
607 format_val != azx_dev->format_val 454 format_val != azx_dev->format_val ||
608 no_period_wakeup != azx_dev->no_pe !! 455 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
609 azx_dev->bufsize = bufsize; 456 azx_dev->bufsize = bufsize;
610 azx_dev->period_bytes = period 457 azx_dev->period_bytes = period_bytes;
611 azx_dev->format_val = format_v 458 azx_dev->format_val = format_val;
612 azx_dev->no_period_wakeup = no !! 459 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
613 err = snd_hdac_stream_setup_pe 460 err = snd_hdac_stream_setup_periods(azx_dev);
614 if (err < 0) 461 if (err < 0)
615 return err; 462 return err;
616 } 463 }
617 return 0; 464 return 0;
618 } 465 }
619 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params); 466 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params);
620 467
621 static u64 azx_cc_read(const struct cyclecount 468 static u64 azx_cc_read(const struct cyclecounter *cc)
622 { 469 {
623 struct hdac_stream *azx_dev = containe 470 struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc);
624 471
625 return snd_hdac_chip_readl(azx_dev->bu 472 return snd_hdac_chip_readl(azx_dev->bus, WALLCLK);
626 } 473 }
627 474
628 static void azx_timecounter_init(struct hdac_s 475 static void azx_timecounter_init(struct hdac_stream *azx_dev,
629 bool force, u 476 bool force, u64 last)
630 { 477 {
631 struct timecounter *tc = &azx_dev->tc; 478 struct timecounter *tc = &azx_dev->tc;
632 struct cyclecounter *cc = &azx_dev->cc 479 struct cyclecounter *cc = &azx_dev->cc;
633 u64 nsec; 480 u64 nsec;
634 481
635 cc->read = azx_cc_read; 482 cc->read = azx_cc_read;
636 cc->mask = CLOCKSOURCE_MASK(32); 483 cc->mask = CLOCKSOURCE_MASK(32);
637 484
638 /* 485 /*
639 * Calculate the optimal mult/shift va !! 486 * Converting from 24 MHz to ns means applying a 125/3 factor.
640 * around after ~178.9 seconds. !! 487 * To avoid any saturation issues in intermediate operations,
>> 488 * the 125 factor is applied first. The division is applied
>> 489 * last after reading the timecounter value.
>> 490 * Applying the 1/3 factor as part of the multiplication
>> 491 * requires at least 20 bits for a decent precision, however
>> 492 * overflows occur after about 4 hours or less, not a option.
641 */ 493 */
642 clocks_calc_mult_shift(&cc->mult, &cc- !! 494
643 NSEC_PER_SEC, 1 !! 495 cc->mult = 125; /* saturation after 195 years */
>> 496 cc->shift = 0;
644 497
645 nsec = 0; /* audio time is elapsed tim 498 nsec = 0; /* audio time is elapsed time since trigger */
646 timecounter_init(tc, cc, nsec); 499 timecounter_init(tc, cc, nsec);
647 if (force) { 500 if (force) {
648 /* 501 /*
649 * force timecounter to use pr 502 * force timecounter to use predefined value,
650 * used for synchronized start 503 * used for synchronized starts
651 */ 504 */
652 tc->cycle_last = last; 505 tc->cycle_last = last;
653 } 506 }
654 } 507 }
655 508
656 /** 509 /**
657 * snd_hdac_stream_timecounter_init - initiali 510 * snd_hdac_stream_timecounter_init - initialize time counter
658 * @azx_dev: HD-audio core stream (master stre 511 * @azx_dev: HD-audio core stream (master stream)
659 * @streams: bit flags of streams to set up 512 * @streams: bit flags of streams to set up
660 * @start: true for PCM trigger start, false f <<
661 * 513 *
662 * Initializes the time counter of streams mar 514 * Initializes the time counter of streams marked by the bit flags (each
663 * bit corresponds to the stream index). 515 * bit corresponds to the stream index).
664 * The trigger timestamp of PCM substream assi 516 * The trigger timestamp of PCM substream assigned to the given stream is
665 * updated accordingly, too. 517 * updated accordingly, too.
666 */ 518 */
667 void snd_hdac_stream_timecounter_init(struct h 519 void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
668 unsigned !! 520 unsigned int streams)
669 { 521 {
670 struct hdac_bus *bus = azx_dev->bus; 522 struct hdac_bus *bus = azx_dev->bus;
671 struct snd_pcm_runtime *runtime = azx_ 523 struct snd_pcm_runtime *runtime = azx_dev->substream->runtime;
672 struct hdac_stream *s; 524 struct hdac_stream *s;
673 bool inited = false; 525 bool inited = false;
674 u64 cycle_last = 0; 526 u64 cycle_last = 0;
675 !! 527 int i = 0;
676 if (!start) <<
677 goto skip; <<
678 528
679 list_for_each_entry(s, &bus->stream_li 529 list_for_each_entry(s, &bus->stream_list, list) {
680 if ((streams & (1 << s->index) !! 530 if (streams & (1 << i)) {
681 azx_timecounter_init(s 531 azx_timecounter_init(s, inited, cycle_last);
682 if (!inited) { 532 if (!inited) {
683 inited = true; 533 inited = true;
684 cycle_last = s 534 cycle_last = s->tc.cycle_last;
685 } 535 }
686 } 536 }
>> 537 i++;
687 } 538 }
688 539
689 skip: <<
690 snd_pcm_gettime(runtime, &runtime->tri 540 snd_pcm_gettime(runtime, &runtime->trigger_tstamp);
691 runtime->trigger_tstamp_latched = true 541 runtime->trigger_tstamp_latched = true;
692 } 542 }
693 EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_ 543 EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init);
694 544
695 /** 545 /**
696 * snd_hdac_stream_sync_trigger - turn on/off 546 * snd_hdac_stream_sync_trigger - turn on/off stream sync register
697 * @azx_dev: HD-audio core stream (master stre 547 * @azx_dev: HD-audio core stream (master stream)
698 * @set: true = set, false = clear <<
699 * @streams: bit flags of streams to sync 548 * @streams: bit flags of streams to sync
700 * @reg: the stream sync register address <<
701 */ 549 */
702 void snd_hdac_stream_sync_trigger(struct hdac_ 550 void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
703 unsigned int 551 unsigned int streams, unsigned int reg)
704 { 552 {
705 struct hdac_bus *bus = azx_dev->bus; 553 struct hdac_bus *bus = azx_dev->bus;
706 unsigned int val; 554 unsigned int val;
707 555
708 if (!reg) 556 if (!reg)
709 reg = AZX_REG_SSYNC; 557 reg = AZX_REG_SSYNC;
710 val = _snd_hdac_chip_readl(bus, reg); 558 val = _snd_hdac_chip_readl(bus, reg);
711 if (set) 559 if (set)
712 val |= streams; 560 val |= streams;
713 else 561 else
714 val &= ~streams; 562 val &= ~streams;
715 _snd_hdac_chip_writel(bus, reg, val); 563 _snd_hdac_chip_writel(bus, reg, val);
716 } 564 }
717 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger 565 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger);
718 566
719 /** 567 /**
720 * snd_hdac_stream_sync - sync with start/stop !! 568 * snd_hdac_stream_sync - sync with start/strop trigger operation
721 * @azx_dev: HD-audio core stream (master stre 569 * @azx_dev: HD-audio core stream (master stream)
722 * @start: true = start, false = stop 570 * @start: true = start, false = stop
723 * @streams: bit flags of streams to sync 571 * @streams: bit flags of streams to sync
724 * 572 *
725 * For @start = true, wait until all FIFOs get 573 * For @start = true, wait until all FIFOs get ready.
726 * For @start = false, wait until all RUN bits 574 * For @start = false, wait until all RUN bits are cleared.
727 */ 575 */
728 void snd_hdac_stream_sync(struct hdac_stream * 576 void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
729 unsigned int streams 577 unsigned int streams)
730 { 578 {
731 struct hdac_bus *bus = azx_dev->bus; 579 struct hdac_bus *bus = azx_dev->bus;
732 int nwait, timeout; !! 580 int i, nwait, timeout;
733 struct hdac_stream *s; 581 struct hdac_stream *s;
734 582
735 for (timeout = 5000; timeout; timeout- 583 for (timeout = 5000; timeout; timeout--) {
736 nwait = 0; 584 nwait = 0;
>> 585 i = 0;
737 list_for_each_entry(s, &bus->s 586 list_for_each_entry(s, &bus->stream_list, list) {
738 if (!(streams & (1 << !! 587 if (streams & (1 << i)) {
739 continue; !! 588 if (start) {
740 !! 589 /* check FIFO gets ready */
741 if (start) { !! 590 if (!(snd_hdac_stream_readb(s, SD_STS) &
742 /* check FIFO !! 591 SD_STS_FIFO_READY))
743 if (!(snd_hdac !! 592 nwait++;
744 SD_STS_F !! 593 } else {
745 nwait+ !! 594 /* check RUN bit is cleared */
746 } else { !! 595 if (snd_hdac_stream_readb(s, SD_CTL) &
747 /* check RUN b !! 596 SD_CTL_DMA_START)
748 if (snd_hdac_s !! 597 nwait++;
749 SD_CTL_DMA <<
750 nwait+ <<
751 /* <<
752 * Per <<
753 * bit <<
754 */ <<
755 if (ti <<
756 <<
757 } 598 }
758 } 599 }
>> 600 i++;
759 } 601 }
760 if (!nwait) 602 if (!nwait)
761 break; 603 break;
762 cpu_relax(); 604 cpu_relax();
763 } 605 }
764 } 606 }
765 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync); 607 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync);
766 608
767 /** <<
768 * snd_hdac_stream_spbcap_enable - enable SPIB <<
769 * @bus: HD-audio core bus <<
770 * @enable: flag to enable/disable SPIB <<
771 * @index: stream index for which SPIB need to <<
772 */ <<
773 void snd_hdac_stream_spbcap_enable(struct hdac <<
774 bool enable <<
775 { <<
776 u32 mask = 0; <<
777 <<
778 if (!bus->spbcap) { <<
779 dev_err(bus->dev, "Address of <<
780 return; <<
781 } <<
782 <<
783 mask |= (1 << index); <<
784 <<
785 if (enable) <<
786 snd_hdac_updatel(bus->spbcap, <<
787 else <<
788 snd_hdac_updatel(bus->spbcap, <<
789 } <<
790 EXPORT_SYMBOL_GPL(snd_hdac_stream_spbcap_enabl <<
791 <<
792 /** <<
793 * snd_hdac_stream_set_spib - sets the spib va <<
794 * @bus: HD-audio core bus <<
795 * @azx_dev: hdac_stream <<
796 * @value: spib value to set <<
797 */ <<
798 int snd_hdac_stream_set_spib(struct hdac_bus * <<
799 struct hdac_strea <<
800 { <<
801 if (!bus->spbcap) { <<
802 dev_err(bus->dev, "Address of <<
803 return -EINVAL; <<
804 } <<
805 <<
806 writel(value, azx_dev->spib_addr); <<
807 <<
808 return 0; <<
809 } <<
810 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_spib); <<
811 <<
812 /** <<
813 * snd_hdac_stream_get_spbmaxfifo - gets the s <<
814 * @bus: HD-audio core bus <<
815 * @azx_dev: hdac_stream <<
816 * <<
817 * Return maxfifo for the stream <<
818 */ <<
819 int snd_hdac_stream_get_spbmaxfifo(struct hdac <<
820 struct hdac <<
821 { <<
822 if (!bus->spbcap) { <<
823 dev_err(bus->dev, "Address of <<
824 return -EINVAL; <<
825 } <<
826 <<
827 return readl(azx_dev->fifo_addr); <<
828 } <<
829 EXPORT_SYMBOL_GPL(snd_hdac_stream_get_spbmaxfi <<
830 <<
831 /** <<
832 * snd_hdac_stream_drsm_enable - enable DMA re <<
833 * @bus: HD-audio core bus <<
834 * @enable: flag to enable/disable DRSM <<
835 * @index: stream index for which DRSM need to <<
836 */ <<
837 void snd_hdac_stream_drsm_enable(struct hdac_b <<
838 bool enable, <<
839 { <<
840 u32 mask = 0; <<
841 <<
842 if (!bus->drsmcap) { <<
843 dev_err(bus->dev, "Address of <<
844 return; <<
845 } <<
846 <<
847 mask |= (1 << index); <<
848 <<
849 if (enable) <<
850 snd_hdac_updatel(bus->drsmcap, <<
851 else <<
852 snd_hdac_updatel(bus->drsmcap, <<
853 } <<
854 EXPORT_SYMBOL_GPL(snd_hdac_stream_drsm_enable) <<
855 <<
856 /* <<
857 * snd_hdac_stream_wait_drsm - wait for HW to <<
858 * @azx_dev: HD-audio core stream to await RSM <<
859 * <<
860 * Returns 0 on success and -ETIMEDOUT upon a <<
861 */ <<
862 int snd_hdac_stream_wait_drsm(struct hdac_stre <<
863 { <<
864 struct hdac_bus *bus = azx_dev->bus; <<
865 u32 mask, reg; <<
866 int ret; <<
867 <<
868 mask = 1 << azx_dev->index; <<
869 <<
870 ret = read_poll_timeout(snd_hdac_reg_r <<
871 bus->drsmcap + <<
872 if (ret) <<
873 dev_dbg(bus->dev, "polling RSM <<
874 return ret; <<
875 } <<
876 EXPORT_SYMBOL_GPL(snd_hdac_stream_wait_drsm); <<
877 <<
878 /** <<
879 * snd_hdac_stream_set_dpibr - sets the dpibr <<
880 * @bus: HD-audio core bus <<
881 * @azx_dev: hdac_stream <<
882 * @value: dpib value to set <<
883 */ <<
884 int snd_hdac_stream_set_dpibr(struct hdac_bus <<
885 struct hdac_stre <<
886 { <<
887 if (!bus->drsmcap) { <<
888 dev_err(bus->dev, "Address of <<
889 return -EINVAL; <<
890 } <<
891 <<
892 writel(value, azx_dev->dpibr_addr); <<
893 <<
894 return 0; <<
895 } <<
896 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_dpibr); <<
897 <<
898 /** <<
899 * snd_hdac_stream_set_lpib - sets the lpib va <<
900 * @azx_dev: hdac_stream <<
901 * @value: lpib value to set <<
902 */ <<
903 int snd_hdac_stream_set_lpib(struct hdac_strea <<
904 { <<
905 snd_hdac_stream_writel(azx_dev, SD_LPI <<
906 <<
907 return 0; <<
908 } <<
909 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_lpib); <<
910 <<
911 #ifdef CONFIG_SND_HDA_DSP_LOADER 609 #ifdef CONFIG_SND_HDA_DSP_LOADER
912 /** 610 /**
913 * snd_hdac_dsp_prepare - prepare for DSP load 611 * snd_hdac_dsp_prepare - prepare for DSP loading
914 * @azx_dev: HD-audio core stream used for DSP 612 * @azx_dev: HD-audio core stream used for DSP loading
915 * @format: HD-audio stream format 613 * @format: HD-audio stream format
916 * @byte_size: data chunk byte size 614 * @byte_size: data chunk byte size
917 * @bufp: allocated buffer 615 * @bufp: allocated buffer
918 * 616 *
919 * Allocate the buffer for the given size and 617 * Allocate the buffer for the given size and set up the given stream for
920 * DSP loading. Returns the stream tag (>= 0) 618 * DSP loading. Returns the stream tag (>= 0), or a negative error code.
921 */ 619 */
922 int snd_hdac_dsp_prepare(struct hdac_stream *a 620 int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
923 unsigned int byte_siz 621 unsigned int byte_size, struct snd_dma_buffer *bufp)
924 { 622 {
925 struct hdac_bus *bus = azx_dev->bus; 623 struct hdac_bus *bus = azx_dev->bus;
926 __le32 *bdl; !! 624 u32 *bdl;
927 int err; 625 int err;
928 626
929 snd_hdac_dsp_lock(azx_dev); 627 snd_hdac_dsp_lock(azx_dev);
930 spin_lock_irq(&bus->reg_lock); 628 spin_lock_irq(&bus->reg_lock);
931 if (azx_dev->running || azx_dev->locke 629 if (azx_dev->running || azx_dev->locked) {
932 spin_unlock_irq(&bus->reg_lock 630 spin_unlock_irq(&bus->reg_lock);
933 err = -EBUSY; 631 err = -EBUSY;
934 goto unlock; 632 goto unlock;
935 } 633 }
936 azx_dev->locked = true; 634 azx_dev->locked = true;
937 spin_unlock_irq(&bus->reg_lock); 635 spin_unlock_irq(&bus->reg_lock);
938 636
939 err = snd_dma_alloc_pages(SNDRV_DMA_TY !! 637 err = bus->io_ops->dma_alloc_pages(bus, SNDRV_DMA_TYPE_DEV_SG,
940 byte_size, b !! 638 byte_size, bufp);
941 if (err < 0) 639 if (err < 0)
942 goto err_alloc; 640 goto err_alloc;
943 641
944 azx_dev->substream = NULL; 642 azx_dev->substream = NULL;
945 azx_dev->bufsize = byte_size; 643 azx_dev->bufsize = byte_size;
946 azx_dev->period_bytes = byte_size; 644 azx_dev->period_bytes = byte_size;
947 azx_dev->format_val = format; 645 azx_dev->format_val = format;
948 646
949 snd_hdac_stream_reset(azx_dev); 647 snd_hdac_stream_reset(azx_dev);
950 648
951 /* reset BDL address */ 649 /* reset BDL address */
952 snd_hdac_stream_writel(azx_dev, SD_BDL 650 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
953 snd_hdac_stream_writel(azx_dev, SD_BDL 651 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
954 652
955 azx_dev->frags = 0; 653 azx_dev->frags = 0;
956 bdl = (__le32 *)azx_dev->bdl.area; !! 654 bdl = (u32 *)azx_dev->bdl.area;
957 err = setup_bdle(bus, bufp, azx_dev, & 655 err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0);
958 if (err < 0) 656 if (err < 0)
959 goto error; 657 goto error;
960 658
961 snd_hdac_stream_setup(azx_dev, true); !! 659 snd_hdac_stream_setup(azx_dev);
962 snd_hdac_dsp_unlock(azx_dev); 660 snd_hdac_dsp_unlock(azx_dev);
963 return azx_dev->stream_tag; 661 return azx_dev->stream_tag;
964 662
965 error: 663 error:
966 snd_dma_free_pages(bufp); !! 664 bus->io_ops->dma_free_pages(bus, bufp);
967 err_alloc: 665 err_alloc:
968 spin_lock_irq(&bus->reg_lock); 666 spin_lock_irq(&bus->reg_lock);
969 azx_dev->locked = false; 667 azx_dev->locked = false;
970 spin_unlock_irq(&bus->reg_lock); 668 spin_unlock_irq(&bus->reg_lock);
971 unlock: 669 unlock:
972 snd_hdac_dsp_unlock(azx_dev); 670 snd_hdac_dsp_unlock(azx_dev);
973 return err; 671 return err;
974 } 672 }
975 EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare); 673 EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare);
976 674
977 /** 675 /**
978 * snd_hdac_dsp_trigger - start / stop DSP loa 676 * snd_hdac_dsp_trigger - start / stop DSP loading
979 * @azx_dev: HD-audio core stream used for DSP 677 * @azx_dev: HD-audio core stream used for DSP loading
980 * @start: trigger start or stop 678 * @start: trigger start or stop
981 */ 679 */
982 void snd_hdac_dsp_trigger(struct hdac_stream * 680 void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
983 { 681 {
984 if (start) 682 if (start)
985 snd_hdac_stream_start(azx_dev) !! 683 snd_hdac_stream_start(azx_dev, true);
986 else 684 else
987 snd_hdac_stream_stop(azx_dev); 685 snd_hdac_stream_stop(azx_dev);
988 } 686 }
989 EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger); 687 EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger);
990 688
991 /** 689 /**
992 * snd_hdac_dsp_cleanup - clean up the stream 690 * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal
993 * @azx_dev: HD-audio core stream used for DSP 691 * @azx_dev: HD-audio core stream used for DSP loading
994 * @dmab: buffer used by DSP loading 692 * @dmab: buffer used by DSP loading
995 */ 693 */
996 void snd_hdac_dsp_cleanup(struct hdac_stream * 694 void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
997 struct snd_dma_buffe 695 struct snd_dma_buffer *dmab)
998 { 696 {
999 struct hdac_bus *bus = azx_dev->bus; 697 struct hdac_bus *bus = azx_dev->bus;
1000 698
1001 if (!dmab->area || !azx_dev->locked) 699 if (!dmab->area || !azx_dev->locked)
1002 return; 700 return;
1003 701
1004 snd_hdac_dsp_lock(azx_dev); 702 snd_hdac_dsp_lock(azx_dev);
1005 /* reset BDL address */ 703 /* reset BDL address */
1006 snd_hdac_stream_writel(azx_dev, SD_BD 704 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
1007 snd_hdac_stream_writel(azx_dev, SD_BD 705 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
1008 snd_hdac_stream_writel(azx_dev, SD_CT 706 snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
1009 azx_dev->bufsize = 0; 707 azx_dev->bufsize = 0;
1010 azx_dev->period_bytes = 0; 708 azx_dev->period_bytes = 0;
1011 azx_dev->format_val = 0; 709 azx_dev->format_val = 0;
1012 710
1013 snd_dma_free_pages(dmab); !! 711 bus->io_ops->dma_free_pages(bus, dmab);
1014 dmab->area = NULL; 712 dmab->area = NULL;
1015 713
1016 spin_lock_irq(&bus->reg_lock); 714 spin_lock_irq(&bus->reg_lock);
1017 azx_dev->locked = false; 715 azx_dev->locked = false;
1018 spin_unlock_irq(&bus->reg_lock); 716 spin_unlock_irq(&bus->reg_lock);
1019 snd_hdac_dsp_unlock(azx_dev); 717 snd_hdac_dsp_unlock(azx_dev);
1020 } 718 }
1021 EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup); 719 EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup);
1022 #endif /* CONFIG_SND_HDA_DSP_LOADER */ 720 #endif /* CONFIG_SND_HDA_DSP_LOADER */
1023 721
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