1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * HD-audio stream operations 3 * HD-audio stream operations
4 */ 4 */
5 5
6 #include <linux/kernel.h> 6 #include <linux/kernel.h>
7 #include <linux/delay.h> 7 #include <linux/delay.h>
8 #include <linux/export.h> 8 #include <linux/export.h>
9 #include <linux/clocksource.h> 9 #include <linux/clocksource.h>
10 #include <sound/compress_driver.h> <<
11 #include <sound/core.h> 10 #include <sound/core.h>
12 #include <sound/pcm.h> 11 #include <sound/pcm.h>
13 #include <sound/hdaudio.h> 12 #include <sound/hdaudio.h>
14 #include <sound/hda_register.h> 13 #include <sound/hda_register.h>
15 #include "trace.h" 14 #include "trace.h"
16 15
17 /* <<
18 * the hdac_stream library is intended to be u <<
19 * transitions. The states are not formally de <<
20 * inspired by boolean variables. Note that th <<
21 * in this library but by the callers during t <<
22 * <<
23 * | <<
24 * stream_init() | <<
25 * v <<
26 * +--+-------+ <<
27 * | unused | <<
28 * +--+----+--+ <<
29 * | ^ <<
30 * stream_assign() | | stream_re <<
31 * v | <<
32 * +--+----+--+ <<
33 * | opened | <<
34 * +--+----+--+ <<
35 * | ^ <<
36 * stream_reset() | | <<
37 * stream_setup() | | stream_cl <<
38 * v | <<
39 * +--+----+--+ <<
40 * | prepared | <<
41 * +--+----+--+ <<
42 * | ^ <<
43 * stream_start() | | stream_st <<
44 * v | <<
45 * +--+----+--+ <<
46 * | running | <<
47 * +----------+ <<
48 */ <<
49 <<
50 /** 16 /**
51 * snd_hdac_get_stream_stripe_ctl - get stripe 17 * snd_hdac_get_stream_stripe_ctl - get stripe control value
52 * @bus: HD-audio core bus 18 * @bus: HD-audio core bus
53 * @substream: PCM substream 19 * @substream: PCM substream
54 */ 20 */
55 int snd_hdac_get_stream_stripe_ctl(struct hdac 21 int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,
56 struct snd_ 22 struct snd_pcm_substream *substream)
57 { 23 {
58 struct snd_pcm_runtime *runtime = subs 24 struct snd_pcm_runtime *runtime = substream->runtime;
59 unsigned int channels = runtime->chann 25 unsigned int channels = runtime->channels,
60 rate = runtime->rate, 26 rate = runtime->rate,
61 bits_per_sample = runtime 27 bits_per_sample = runtime->sample_bits,
62 max_sdo_lines, value, sdo 28 max_sdo_lines, value, sdo_line;
63 29
64 /* T_AZA_GCAP_NSDO is 1:2 bitfields in 30 /* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */
65 max_sdo_lines = snd_hdac_chip_readl(bu 31 max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO;
66 32
67 /* following is from HD audio spec */ 33 /* following is from HD audio spec */
68 for (sdo_line = max_sdo_lines; sdo_lin 34 for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) {
69 if (rate > 48000) 35 if (rate > 48000)
70 value = (channels * bi 36 value = (channels * bits_per_sample *
71 (rate 37 (rate / 48000)) / sdo_line;
72 else 38 else
73 value = (channels * bi 39 value = (channels * bits_per_sample) / sdo_line;
74 40
75 if (value >= bus->sdo_limit) 41 if (value >= bus->sdo_limit)
76 break; 42 break;
77 } 43 }
78 44
79 /* stripe value: 0 for 1SDO, 1 for 2SD 45 /* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */
80 return sdo_line >> 1; 46 return sdo_line >> 1;
81 } 47 }
82 EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_c 48 EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl);
83 49
84 /** 50 /**
85 * snd_hdac_stream_init - initialize each stre 51 * snd_hdac_stream_init - initialize each stream (aka device)
86 * @bus: HD-audio core bus 52 * @bus: HD-audio core bus
87 * @azx_dev: HD-audio core stream object to in 53 * @azx_dev: HD-audio core stream object to initialize
88 * @idx: stream index number 54 * @idx: stream index number
89 * @direction: stream direction (SNDRV_PCM_STR 55 * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE)
90 * @tag: the tag id to assign 56 * @tag: the tag id to assign
91 * 57 *
92 * Assign the starting bdl address to each str 58 * Assign the starting bdl address to each stream (device) and initialize.
93 */ 59 */
94 void snd_hdac_stream_init(struct hdac_bus *bus 60 void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
95 int idx, int directi 61 int idx, int direction, int tag)
96 { 62 {
97 azx_dev->bus = bus; 63 azx_dev->bus = bus;
98 /* offset: SDI0=0x80, SDI1=0xa0, ... S 64 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
99 azx_dev->sd_addr = bus->remap_addr + ( 65 azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80);
100 /* int mask: SDI0=0x01, SDI1=0x02, ... 66 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
101 azx_dev->sd_int_sta_mask = 1 << idx; 67 azx_dev->sd_int_sta_mask = 1 << idx;
102 azx_dev->index = idx; 68 azx_dev->index = idx;
103 azx_dev->direction = direction; 69 azx_dev->direction = direction;
104 azx_dev->stream_tag = tag; 70 azx_dev->stream_tag = tag;
105 snd_hdac_dsp_lock_init(azx_dev); 71 snd_hdac_dsp_lock_init(azx_dev);
106 list_add_tail(&azx_dev->list, &bus->st 72 list_add_tail(&azx_dev->list, &bus->stream_list);
107 <<
108 if (bus->spbcap) { <<
109 azx_dev->spib_addr = bus->spbc <<
110 AZX_SP <<
111 AZX_SP <<
112 <<
113 azx_dev->fifo_addr = bus->spbc <<
114 AZX_SP <<
115 AZX_SP <<
116 } <<
117 <<
118 if (bus->drsmcap) <<
119 azx_dev->dpibr_addr = bus->drs <<
120 AZX_DR <<
121 } 73 }
122 EXPORT_SYMBOL_GPL(snd_hdac_stream_init); 74 EXPORT_SYMBOL_GPL(snd_hdac_stream_init);
123 75
124 /** 76 /**
125 * snd_hdac_stream_start - start a stream 77 * snd_hdac_stream_start - start a stream
126 * @azx_dev: HD-audio core stream to start 78 * @azx_dev: HD-audio core stream to start
>> 79 * @fresh_start: false = wallclock timestamp relative to period wallclock
127 * 80 *
128 * Start a stream, set start_wallclk and set t 81 * Start a stream, set start_wallclk and set the running flag.
129 */ 82 */
130 void snd_hdac_stream_start(struct hdac_stream !! 83 void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start)
131 { 84 {
132 struct hdac_bus *bus = azx_dev->bus; 85 struct hdac_bus *bus = azx_dev->bus;
133 int stripe_ctl; 86 int stripe_ctl;
134 87
135 trace_snd_hdac_stream_start(bus, azx_d 88 trace_snd_hdac_stream_start(bus, azx_dev);
136 89
137 azx_dev->start_wallclk = snd_hdac_chip 90 azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK);
>> 91 if (!fresh_start)
>> 92 azx_dev->start_wallclk -= azx_dev->period_wallclk;
138 93
139 /* enable SIE */ 94 /* enable SIE */
140 snd_hdac_chip_updatel(bus, INTCTL, 95 snd_hdac_chip_updatel(bus, INTCTL,
141 1 << azx_dev->in 96 1 << azx_dev->index,
142 1 << azx_dev->in 97 1 << azx_dev->index);
143 /* set stripe control */ 98 /* set stripe control */
144 if (azx_dev->stripe) { 99 if (azx_dev->stripe) {
145 if (azx_dev->substream) 100 if (azx_dev->substream)
146 stripe_ctl = snd_hdac_ 101 stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream);
147 else 102 else
148 stripe_ctl = 0; 103 stripe_ctl = 0;
149 snd_hdac_stream_updateb(azx_de 104 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK,
150 stripe 105 stripe_ctl);
151 } 106 }
152 /* set DMA start and interrupt mask */ 107 /* set DMA start and interrupt mask */
153 if (bus->access_sdnctl_in_dword) !! 108 snd_hdac_stream_updateb(azx_dev, SD_CTL,
154 snd_hdac_stream_updatel(azx_de <<
155 0, SD_CTL_DMA_ <<
156 else <<
157 snd_hdac_stream_updateb(azx_de <<
158 0, SD_CTL_DMA_ 109 0, SD_CTL_DMA_START | SD_INT_MASK);
159 azx_dev->running = true; 110 azx_dev->running = true;
160 } 111 }
161 EXPORT_SYMBOL_GPL(snd_hdac_stream_start); 112 EXPORT_SYMBOL_GPL(snd_hdac_stream_start);
162 113
163 /** 114 /**
164 * snd_hdac_stream_clear - helper to clear str !! 115 * snd_hdac_stream_clear - stop a stream DMA
165 * @azx_dev: HD-audio core stream to stop 116 * @azx_dev: HD-audio core stream to stop
166 */ 117 */
167 static void snd_hdac_stream_clear(struct hdac_ !! 118 void snd_hdac_stream_clear(struct hdac_stream *azx_dev)
168 { 119 {
169 snd_hdac_stream_updateb(azx_dev, SD_CT 120 snd_hdac_stream_updateb(azx_dev, SD_CTL,
170 SD_CTL_DMA_STA 121 SD_CTL_DMA_START | SD_INT_MASK, 0);
171 snd_hdac_stream_writeb(azx_dev, SD_STS 122 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
172 if (azx_dev->stripe) 123 if (azx_dev->stripe)
173 snd_hdac_stream_updateb(azx_de 124 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0);
174 azx_dev->running = false; 125 azx_dev->running = false;
175 } 126 }
>> 127 EXPORT_SYMBOL_GPL(snd_hdac_stream_clear);
176 128
177 /** 129 /**
178 * snd_hdac_stream_stop - stop a stream 130 * snd_hdac_stream_stop - stop a stream
179 * @azx_dev: HD-audio core stream to stop 131 * @azx_dev: HD-audio core stream to stop
180 * 132 *
181 * Stop a stream DMA and disable stream interr 133 * Stop a stream DMA and disable stream interrupt
182 */ 134 */
183 void snd_hdac_stream_stop(struct hdac_stream * 135 void snd_hdac_stream_stop(struct hdac_stream *azx_dev)
184 { 136 {
185 trace_snd_hdac_stream_stop(azx_dev->bu 137 trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev);
186 138
187 snd_hdac_stream_clear(azx_dev); 139 snd_hdac_stream_clear(azx_dev);
188 /* disable SIE */ 140 /* disable SIE */
189 snd_hdac_chip_updatel(azx_dev->bus, IN 141 snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0);
190 } 142 }
191 EXPORT_SYMBOL_GPL(snd_hdac_stream_stop); 143 EXPORT_SYMBOL_GPL(snd_hdac_stream_stop);
192 144
193 /** 145 /**
194 * snd_hdac_stop_streams - stop all streams <<
195 * @bus: HD-audio core bus <<
196 */ <<
197 void snd_hdac_stop_streams(struct hdac_bus *bu <<
198 { <<
199 struct hdac_stream *stream; <<
200 <<
201 list_for_each_entry(stream, &bus->stre <<
202 snd_hdac_stream_stop(stream); <<
203 } <<
204 EXPORT_SYMBOL_GPL(snd_hdac_stop_streams); <<
205 <<
206 /** <<
207 * snd_hdac_stop_streams_and_chip - stop all s <<
208 * @bus: HD-audio core bus <<
209 */ <<
210 void snd_hdac_stop_streams_and_chip(struct hda <<
211 { <<
212 <<
213 if (bus->chip_init) { <<
214 snd_hdac_stop_streams(bus); <<
215 snd_hdac_bus_stop_chip(bus); <<
216 } <<
217 } <<
218 EXPORT_SYMBOL_GPL(snd_hdac_stop_streams_and_ch <<
219 <<
220 /** <<
221 * snd_hdac_stream_reset - reset a stream 146 * snd_hdac_stream_reset - reset a stream
222 * @azx_dev: HD-audio core stream to reset 147 * @azx_dev: HD-audio core stream to reset
223 */ 148 */
224 void snd_hdac_stream_reset(struct hdac_stream 149 void snd_hdac_stream_reset(struct hdac_stream *azx_dev)
225 { 150 {
226 unsigned char val; 151 unsigned char val;
227 int dma_run_state; !! 152 int timeout;
228 153
229 snd_hdac_stream_clear(azx_dev); 154 snd_hdac_stream_clear(azx_dev);
230 155
231 dma_run_state = snd_hdac_stream_readb( <<
232 <<
233 snd_hdac_stream_updateb(azx_dev, SD_CT 156 snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET);
234 !! 157 udelay(3);
235 /* wait for hardware to report that th !! 158 timeout = 300;
236 snd_hdac_stream_readb_poll(azx_dev, SD !! 159 do {
237 !! 160 val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
238 if (azx_dev->bus->dma_stop_delay && dm !! 161 SD_CTL_STREAM_RESET;
239 udelay(azx_dev->bus->dma_stop_ !! 162 if (val)
240 !! 163 break;
241 snd_hdac_stream_updateb(azx_dev, SD_CT !! 164 } while (--timeout);
242 !! 165 val &= ~SD_CTL_STREAM_RESET;
243 /* wait for hardware to report that th !! 166 snd_hdac_stream_writeb(azx_dev, SD_CTL, val);
244 snd_hdac_stream_readb_poll(azx_dev, SD !! 167 udelay(3);
>> 168
>> 169 timeout = 300;
>> 170 /* waiting for hardware to report that the stream is out of reset */
>> 171 do {
>> 172 val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
>> 173 SD_CTL_STREAM_RESET;
>> 174 if (!val)
>> 175 break;
>> 176 } while (--timeout);
245 177
246 /* reset first position - may not be s 178 /* reset first position - may not be synced with hw at this time */
247 if (azx_dev->posbuf) 179 if (azx_dev->posbuf)
248 *azx_dev->posbuf = 0; 180 *azx_dev->posbuf = 0;
249 } 181 }
250 EXPORT_SYMBOL_GPL(snd_hdac_stream_reset); 182 EXPORT_SYMBOL_GPL(snd_hdac_stream_reset);
251 183
252 /** 184 /**
253 * snd_hdac_stream_setup - set up the SD for 185 * snd_hdac_stream_setup - set up the SD for streaming
254 * @azx_dev: HD-audio core stream to set up 186 * @azx_dev: HD-audio core stream to set up
255 * @code_loading: Whether the stream is for PC <<
256 */ 187 */
257 int snd_hdac_stream_setup(struct hdac_stream * !! 188 int snd_hdac_stream_setup(struct hdac_stream *azx_dev)
258 { 189 {
259 struct hdac_bus *bus = azx_dev->bus; 190 struct hdac_bus *bus = azx_dev->bus;
260 struct snd_pcm_runtime *runtime; 191 struct snd_pcm_runtime *runtime;
261 unsigned int val; 192 unsigned int val;
262 u16 reg; <<
263 int ret; <<
264 193
265 if (azx_dev->substream) 194 if (azx_dev->substream)
266 runtime = azx_dev->substream-> 195 runtime = azx_dev->substream->runtime;
267 else 196 else
268 runtime = NULL; 197 runtime = NULL;
269 /* make sure the run bit is zero for S 198 /* make sure the run bit is zero for SD */
270 snd_hdac_stream_clear(azx_dev); 199 snd_hdac_stream_clear(azx_dev);
271 /* program the stream_tag */ 200 /* program the stream_tag */
272 val = snd_hdac_stream_readl(azx_dev, S 201 val = snd_hdac_stream_readl(azx_dev, SD_CTL);
273 val = (val & ~SD_CTL_STREAM_TAG_MASK) 202 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
274 (azx_dev->stream_tag << SD_CTL 203 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
275 if (!bus->snoop) 204 if (!bus->snoop)
276 val |= SD_CTL_TRAFFIC_PRIO; 205 val |= SD_CTL_TRAFFIC_PRIO;
277 snd_hdac_stream_writel(azx_dev, SD_CTL 206 snd_hdac_stream_writel(azx_dev, SD_CTL, val);
278 207
279 /* program the length of samples in cy 208 /* program the length of samples in cyclic buffer */
280 snd_hdac_stream_writel(azx_dev, SD_CBL 209 snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize);
281 210
282 /* program the stream format */ 211 /* program the stream format */
283 /* this value needs to be the same as 212 /* this value needs to be the same as the one programmed */
284 snd_hdac_stream_writew(azx_dev, SD_FOR 213 snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
285 214
286 /* program the stream LVI (last valid 215 /* program the stream LVI (last valid index) of the BDL */
287 snd_hdac_stream_writew(azx_dev, SD_LVI 216 snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
288 217
289 /* program the BDL address */ 218 /* program the BDL address */
290 /* lower BDL address */ 219 /* lower BDL address */
291 snd_hdac_stream_writel(azx_dev, SD_BDL 220 snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
292 /* upper BDL address */ 221 /* upper BDL address */
293 snd_hdac_stream_writel(azx_dev, SD_BDL 222 snd_hdac_stream_writel(azx_dev, SD_BDLPU,
294 upper_32_bits(a 223 upper_32_bits(azx_dev->bdl.addr));
295 224
296 /* enable the position buffer */ 225 /* enable the position buffer */
297 if (bus->use_posbuf && bus->posbuf.add 226 if (bus->use_posbuf && bus->posbuf.addr) {
298 if (!(snd_hdac_chip_readl(bus, 227 if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE))
299 snd_hdac_chip_writel(b 228 snd_hdac_chip_writel(bus, DPLBASE,
300 (u32)bus->posb 229 (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE);
301 } 230 }
302 231
303 /* set the interrupt enable bits in th 232 /* set the interrupt enable bits in the descriptor control register */
304 snd_hdac_stream_updatel(azx_dev, SD_CT 233 snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK);
305 234
306 if (!code_loading) { !! 235 azx_dev->fifo_size = snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1;
307 /* Once SDxFMT is set, the con <<
308 ret = snd_hdac_stream_readw_po <<
309 <<
310 if (ret) <<
311 dev_dbg(bus->dev, "pol <<
312 AZX_REG_SD_FIF <<
313 azx_dev->fifo_size = reg; <<
314 } <<
315 236
316 /* when LPIB delay correction gives a 237 /* when LPIB delay correction gives a small negative value,
317 * we ignore it; currently set the thr 238 * we ignore it; currently set the threshold statically to
318 * 64 frames 239 * 64 frames
319 */ 240 */
320 if (runtime && runtime->period_size > 241 if (runtime && runtime->period_size > 64)
321 azx_dev->delay_negative_thresh 242 azx_dev->delay_negative_threshold =
322 -frames_to_bytes(runti 243 -frames_to_bytes(runtime, 64);
323 else 244 else
324 azx_dev->delay_negative_thresh 245 azx_dev->delay_negative_threshold = 0;
325 246
326 /* wallclk has 24Mhz clock source */ 247 /* wallclk has 24Mhz clock source */
327 if (runtime) 248 if (runtime)
328 azx_dev->period_wallclk = (((r 249 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
329 runtime->r 250 runtime->rate) * 1000);
330 251
331 return 0; 252 return 0;
332 } 253 }
333 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup); 254 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup);
334 255
335 /** 256 /**
336 * snd_hdac_stream_cleanup - cleanup a stream 257 * snd_hdac_stream_cleanup - cleanup a stream
337 * @azx_dev: HD-audio core stream to clean up 258 * @azx_dev: HD-audio core stream to clean up
338 */ 259 */
339 void snd_hdac_stream_cleanup(struct hdac_strea 260 void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev)
340 { 261 {
341 snd_hdac_stream_writel(azx_dev, SD_BDL 262 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
342 snd_hdac_stream_writel(azx_dev, SD_BDL 263 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
343 snd_hdac_stream_writel(azx_dev, SD_CTL 264 snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
344 azx_dev->bufsize = 0; 265 azx_dev->bufsize = 0;
345 azx_dev->period_bytes = 0; 266 azx_dev->period_bytes = 0;
346 azx_dev->format_val = 0; 267 azx_dev->format_val = 0;
347 } 268 }
348 EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup); 269 EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup);
349 270
350 /** 271 /**
351 * snd_hdac_stream_assign - assign a stream fo 272 * snd_hdac_stream_assign - assign a stream for the PCM
352 * @bus: HD-audio core bus 273 * @bus: HD-audio core bus
353 * @substream: PCM substream to assign 274 * @substream: PCM substream to assign
354 * 275 *
355 * Look for an unused stream for the given PCM 276 * Look for an unused stream for the given PCM substream, assign it
356 * and return the stream object. If no stream 277 * and return the stream object. If no stream is free, returns NULL.
357 * The function tries to keep using the same s 278 * The function tries to keep using the same stream object when it's used
358 * beforehand. Also, when bus->reverse_assign 279 * beforehand. Also, when bus->reverse_assign flag is set, the last free
359 * or matching entry is returned. This is nee 280 * or matching entry is returned. This is needed for some strange codecs.
360 */ 281 */
361 struct hdac_stream *snd_hdac_stream_assign(str 282 struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
362 str 283 struct snd_pcm_substream *substream)
363 { 284 {
364 struct hdac_stream *azx_dev; 285 struct hdac_stream *azx_dev;
365 struct hdac_stream *res = NULL; 286 struct hdac_stream *res = NULL;
366 287
367 /* make a non-zero unique key for the 288 /* make a non-zero unique key for the substream */
368 int key = (substream->number << 2) | ( !! 289 int key = (substream->pcm->device << 16) | (substream->number << 2) |
369 !! 290 (substream->stream + 1);
370 if (substream->pcm) <<
371 key |= (substream->pcm->device <<
372 291
373 spin_lock_irq(&bus->reg_lock); <<
374 list_for_each_entry(azx_dev, &bus->str 292 list_for_each_entry(azx_dev, &bus->stream_list, list) {
375 if (azx_dev->direction != subs 293 if (azx_dev->direction != substream->stream)
376 continue; 294 continue;
377 if (azx_dev->opened) 295 if (azx_dev->opened)
378 continue; 296 continue;
379 if (azx_dev->assigned_key == k 297 if (azx_dev->assigned_key == key) {
380 res = azx_dev; 298 res = azx_dev;
381 break; 299 break;
382 } 300 }
383 if (!res || bus->reverse_assig 301 if (!res || bus->reverse_assign)
384 res = azx_dev; 302 res = azx_dev;
385 } 303 }
386 if (res) { 304 if (res) {
>> 305 spin_lock_irq(&bus->reg_lock);
387 res->opened = 1; 306 res->opened = 1;
388 res->running = 0; 307 res->running = 0;
389 res->assigned_key = key; 308 res->assigned_key = key;
390 res->substream = substream; 309 res->substream = substream;
>> 310 spin_unlock_irq(&bus->reg_lock);
391 } 311 }
392 spin_unlock_irq(&bus->reg_lock); <<
393 return res; 312 return res;
394 } 313 }
395 EXPORT_SYMBOL_GPL(snd_hdac_stream_assign); 314 EXPORT_SYMBOL_GPL(snd_hdac_stream_assign);
396 315
397 /** 316 /**
398 * snd_hdac_stream_release_locked - release th <<
399 * @azx_dev: HD-audio core stream to release <<
400 * <<
401 * Release the stream that has been assigned b <<
402 * The bus->reg_lock needs to be taken at a hi <<
403 */ <<
404 void snd_hdac_stream_release_locked(struct hda <<
405 { <<
406 azx_dev->opened = 0; <<
407 azx_dev->running = 0; <<
408 azx_dev->substream = NULL; <<
409 } <<
410 EXPORT_SYMBOL_GPL(snd_hdac_stream_release_lock <<
411 <<
412 /** <<
413 * snd_hdac_stream_release - release the assig 317 * snd_hdac_stream_release - release the assigned stream
414 * @azx_dev: HD-audio core stream to release 318 * @azx_dev: HD-audio core stream to release
415 * 319 *
416 * Release the stream that has been assigned b 320 * Release the stream that has been assigned by snd_hdac_stream_assign().
417 */ 321 */
418 void snd_hdac_stream_release(struct hdac_strea 322 void snd_hdac_stream_release(struct hdac_stream *azx_dev)
419 { 323 {
420 struct hdac_bus *bus = azx_dev->bus; 324 struct hdac_bus *bus = azx_dev->bus;
421 325
422 spin_lock_irq(&bus->reg_lock); 326 spin_lock_irq(&bus->reg_lock);
423 snd_hdac_stream_release_locked(azx_dev !! 327 azx_dev->opened = 0;
>> 328 azx_dev->running = 0;
>> 329 azx_dev->substream = NULL;
424 spin_unlock_irq(&bus->reg_lock); 330 spin_unlock_irq(&bus->reg_lock);
425 } 331 }
426 EXPORT_SYMBOL_GPL(snd_hdac_stream_release); 332 EXPORT_SYMBOL_GPL(snd_hdac_stream_release);
427 333
428 /** 334 /**
429 * snd_hdac_get_stream - return hdac_stream ba 335 * snd_hdac_get_stream - return hdac_stream based on stream_tag and
430 * direction 336 * direction
431 * 337 *
432 * @bus: HD-audio core bus 338 * @bus: HD-audio core bus
433 * @dir: direction for the stream to be found 339 * @dir: direction for the stream to be found
434 * @stream_tag: stream tag for stream to be fo 340 * @stream_tag: stream tag for stream to be found
435 */ 341 */
436 struct hdac_stream *snd_hdac_get_stream(struct 342 struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
437 int di 343 int dir, int stream_tag)
438 { 344 {
439 struct hdac_stream *s; 345 struct hdac_stream *s;
440 346
441 list_for_each_entry(s, &bus->stream_li 347 list_for_each_entry(s, &bus->stream_list, list) {
442 if (s->direction == dir && s-> 348 if (s->direction == dir && s->stream_tag == stream_tag)
443 return s; 349 return s;
444 } 350 }
445 351
446 return NULL; 352 return NULL;
447 } 353 }
448 EXPORT_SYMBOL_GPL(snd_hdac_get_stream); 354 EXPORT_SYMBOL_GPL(snd_hdac_get_stream);
449 355
450 /* 356 /*
451 * set up a BDL entry 357 * set up a BDL entry
452 */ 358 */
453 static int setup_bdle(struct hdac_bus *bus, 359 static int setup_bdle(struct hdac_bus *bus,
454 struct snd_dma_buffer *d 360 struct snd_dma_buffer *dmab,
455 struct hdac_stream *azx_ 361 struct hdac_stream *azx_dev, __le32 **bdlp,
456 int ofs, int size, int w 362 int ofs, int size, int with_ioc)
457 { 363 {
458 __le32 *bdl = *bdlp; 364 __le32 *bdl = *bdlp;
459 365
460 while (size > 0) { 366 while (size > 0) {
461 dma_addr_t addr; 367 dma_addr_t addr;
462 int chunk; 368 int chunk;
463 369
464 if (azx_dev->frags >= AZX_MAX_ 370 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
465 return -EINVAL; 371 return -EINVAL;
466 372
467 addr = snd_sgbuf_get_addr(dmab 373 addr = snd_sgbuf_get_addr(dmab, ofs);
468 /* program the address field o 374 /* program the address field of the BDL entry */
469 bdl[0] = cpu_to_le32((u32)addr 375 bdl[0] = cpu_to_le32((u32)addr);
470 bdl[1] = cpu_to_le32(upper_32_ 376 bdl[1] = cpu_to_le32(upper_32_bits(addr));
471 /* program the size field of t 377 /* program the size field of the BDL entry */
472 chunk = snd_sgbuf_get_chunk_si 378 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
473 /* one BDLE cannot cross 4K bo 379 /* one BDLE cannot cross 4K boundary on CTHDA chips */
474 if (bus->align_bdle_4k) { 380 if (bus->align_bdle_4k) {
475 u32 remain = 0x1000 - 381 u32 remain = 0x1000 - (ofs & 0xfff);
476 382
477 if (chunk > remain) 383 if (chunk > remain)
478 chunk = remain 384 chunk = remain;
479 } 385 }
480 bdl[2] = cpu_to_le32(chunk); 386 bdl[2] = cpu_to_le32(chunk);
481 /* program the IOC to enable i 387 /* program the IOC to enable interrupt
482 * only when the whole fragmen 388 * only when the whole fragment is processed
483 */ 389 */
484 size -= chunk; 390 size -= chunk;
485 bdl[3] = (size || !with_ioc) ? 391 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
486 bdl += 4; 392 bdl += 4;
487 azx_dev->frags++; 393 azx_dev->frags++;
488 ofs += chunk; 394 ofs += chunk;
489 } 395 }
490 *bdlp = bdl; 396 *bdlp = bdl;
491 return ofs; 397 return ofs;
492 } 398 }
493 399
494 /** 400 /**
495 * snd_hdac_stream_setup_periods - set up BDL 401 * snd_hdac_stream_setup_periods - set up BDL entries
496 * @azx_dev: HD-audio core stream to set up 402 * @azx_dev: HD-audio core stream to set up
497 * 403 *
498 * Set up the buffer descriptor table of the g 404 * Set up the buffer descriptor table of the given stream based on the
499 * period and buffer sizes of the assigned PCM 405 * period and buffer sizes of the assigned PCM substream.
500 */ 406 */
501 int snd_hdac_stream_setup_periods(struct hdac_ 407 int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)
502 { 408 {
503 struct hdac_bus *bus = azx_dev->bus; 409 struct hdac_bus *bus = azx_dev->bus;
504 struct snd_pcm_substream *substream = 410 struct snd_pcm_substream *substream = azx_dev->substream;
505 struct snd_compr_stream *cstream = azx !! 411 struct snd_pcm_runtime *runtime = substream->runtime;
506 struct snd_pcm_runtime *runtime = NULL <<
507 struct snd_dma_buffer *dmab; <<
508 __le32 *bdl; 412 __le32 *bdl;
509 int i, ofs, periods, period_bytes; 413 int i, ofs, periods, period_bytes;
510 int pos_adj, pos_align; 414 int pos_adj, pos_align;
511 415
512 if (substream) { <<
513 runtime = substream->runtime; <<
514 dmab = snd_pcm_get_dma_buf(sub <<
515 } else if (cstream) { <<
516 dmab = snd_pcm_get_dma_buf(cst <<
517 } else { <<
518 WARN(1, "No substream or cstre <<
519 return -EINVAL; <<
520 } <<
521 <<
522 /* reset BDL address */ 416 /* reset BDL address */
523 snd_hdac_stream_writel(azx_dev, SD_BDL 417 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
524 snd_hdac_stream_writel(azx_dev, SD_BDL 418 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
525 419
526 period_bytes = azx_dev->period_bytes; 420 period_bytes = azx_dev->period_bytes;
527 periods = azx_dev->bufsize / period_by 421 periods = azx_dev->bufsize / period_bytes;
528 422
529 /* program the initial BDL entries */ 423 /* program the initial BDL entries */
530 bdl = (__le32 *)azx_dev->bdl.area; 424 bdl = (__le32 *)azx_dev->bdl.area;
531 ofs = 0; 425 ofs = 0;
532 azx_dev->frags = 0; 426 azx_dev->frags = 0;
533 427
534 pos_adj = bus->bdl_pos_adj; 428 pos_adj = bus->bdl_pos_adj;
535 if (runtime && !azx_dev->no_period_wak !! 429 if (!azx_dev->no_period_wakeup && pos_adj > 0) {
536 pos_align = pos_adj; 430 pos_align = pos_adj;
537 pos_adj = DIV_ROUND_UP(pos_adj !! 431 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
538 if (!pos_adj) 432 if (!pos_adj)
539 pos_adj = pos_align; 433 pos_adj = pos_align;
540 else 434 else
541 pos_adj = roundup(pos_ !! 435 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
>> 436 pos_align;
542 pos_adj = frames_to_bytes(runt 437 pos_adj = frames_to_bytes(runtime, pos_adj);
543 if (pos_adj >= period_bytes) { 438 if (pos_adj >= period_bytes) {
544 dev_warn(bus->dev, "To 439 dev_warn(bus->dev, "Too big adjustment %d\n",
545 pos_adj); 440 pos_adj);
546 pos_adj = 0; 441 pos_adj = 0;
547 } else { 442 } else {
548 ofs = setup_bdle(bus, !! 443 ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
>> 444 azx_dev,
549 &bdl, 445 &bdl, ofs, pos_adj, true);
550 if (ofs < 0) 446 if (ofs < 0)
551 goto error; 447 goto error;
552 } 448 }
553 } else 449 } else
554 pos_adj = 0; 450 pos_adj = 0;
555 451
556 for (i = 0; i < periods; i++) { 452 for (i = 0; i < periods; i++) {
557 if (i == periods - 1 && pos_ad 453 if (i == periods - 1 && pos_adj)
558 ofs = setup_bdle(bus, !! 454 ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
559 &bdl, !! 455 azx_dev, &bdl, ofs,
>> 456 period_bytes - pos_adj, 0);
560 else 457 else
561 ofs = setup_bdle(bus, !! 458 ofs = setup_bdle(bus, snd_pcm_get_dma_buf(substream),
562 &bdl, !! 459 azx_dev, &bdl, ofs,
>> 460 period_bytes,
563 !azx_ 461 !azx_dev->no_period_wakeup);
564 if (ofs < 0) 462 if (ofs < 0)
565 goto error; 463 goto error;
566 } 464 }
567 return 0; 465 return 0;
568 466
569 error: 467 error:
570 dev_dbg(bus->dev, "Too many BDL entrie !! 468 dev_err(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n",
571 azx_dev->bufsize, period_bytes 469 azx_dev->bufsize, period_bytes);
572 return -EINVAL; 470 return -EINVAL;
573 } 471 }
574 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_period 472 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods);
575 473
576 /** 474 /**
577 * snd_hdac_stream_set_params - set stream par 475 * snd_hdac_stream_set_params - set stream parameters
578 * @azx_dev: HD-audio core stream for which pa 476 * @azx_dev: HD-audio core stream for which parameters are to be set
579 * @format_val: format value parameter 477 * @format_val: format value parameter
580 * 478 *
581 * Setup the HD-audio core stream parameters f 479 * Setup the HD-audio core stream parameters from substream of the stream
582 * and passed format value 480 * and passed format value
583 */ 481 */
584 int snd_hdac_stream_set_params(struct hdac_str 482 int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
585 unsigned int 483 unsigned int format_val)
586 { 484 {
587 struct snd_pcm_substream *substream = !! 485
588 struct snd_compr_stream *cstream = azx <<
589 unsigned int bufsize, period_bytes; 486 unsigned int bufsize, period_bytes;
590 unsigned int no_period_wakeup; !! 487 struct snd_pcm_substream *substream = azx_dev->substream;
>> 488 struct snd_pcm_runtime *runtime;
591 int err; 489 int err;
592 490
593 if (substream) { !! 491 if (!substream)
594 bufsize = snd_pcm_lib_buffer_b <<
595 period_bytes = snd_pcm_lib_per <<
596 no_period_wakeup = substream-> <<
597 } else if (cstream) { <<
598 bufsize = cstream->runtime->bu <<
599 period_bytes = cstream->runtim <<
600 no_period_wakeup = 0; <<
601 } else { <<
602 return -EINVAL; 492 return -EINVAL;
603 } !! 493 runtime = substream->runtime;
>> 494 bufsize = snd_pcm_lib_buffer_bytes(substream);
>> 495 period_bytes = snd_pcm_lib_period_bytes(substream);
604 496
605 if (bufsize != azx_dev->bufsize || 497 if (bufsize != azx_dev->bufsize ||
606 period_bytes != azx_dev->period_by 498 period_bytes != azx_dev->period_bytes ||
607 format_val != azx_dev->format_val 499 format_val != azx_dev->format_val ||
608 no_period_wakeup != azx_dev->no_pe !! 500 runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
609 azx_dev->bufsize = bufsize; 501 azx_dev->bufsize = bufsize;
610 azx_dev->period_bytes = period 502 azx_dev->period_bytes = period_bytes;
611 azx_dev->format_val = format_v 503 azx_dev->format_val = format_val;
612 azx_dev->no_period_wakeup = no !! 504 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
613 err = snd_hdac_stream_setup_pe 505 err = snd_hdac_stream_setup_periods(azx_dev);
614 if (err < 0) 506 if (err < 0)
615 return err; 507 return err;
616 } 508 }
617 return 0; 509 return 0;
618 } 510 }
619 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params); 511 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params);
620 512
621 static u64 azx_cc_read(const struct cyclecount 513 static u64 azx_cc_read(const struct cyclecounter *cc)
622 { 514 {
623 struct hdac_stream *azx_dev = containe 515 struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc);
624 516
625 return snd_hdac_chip_readl(azx_dev->bu 517 return snd_hdac_chip_readl(azx_dev->bus, WALLCLK);
626 } 518 }
627 519
628 static void azx_timecounter_init(struct hdac_s 520 static void azx_timecounter_init(struct hdac_stream *azx_dev,
629 bool force, u 521 bool force, u64 last)
630 { 522 {
631 struct timecounter *tc = &azx_dev->tc; 523 struct timecounter *tc = &azx_dev->tc;
632 struct cyclecounter *cc = &azx_dev->cc 524 struct cyclecounter *cc = &azx_dev->cc;
633 u64 nsec; 525 u64 nsec;
634 526
635 cc->read = azx_cc_read; 527 cc->read = azx_cc_read;
636 cc->mask = CLOCKSOURCE_MASK(32); 528 cc->mask = CLOCKSOURCE_MASK(32);
637 529
638 /* 530 /*
639 * Calculate the optimal mult/shift va !! 531 * Converting from 24 MHz to ns means applying a 125/3 factor.
640 * around after ~178.9 seconds. !! 532 * To avoid any saturation issues in intermediate operations,
>> 533 * the 125 factor is applied first. The division is applied
>> 534 * last after reading the timecounter value.
>> 535 * Applying the 1/3 factor as part of the multiplication
>> 536 * requires at least 20 bits for a decent precision, however
>> 537 * overflows occur after about 4 hours or less, not a option.
641 */ 538 */
642 clocks_calc_mult_shift(&cc->mult, &cc- !! 539
643 NSEC_PER_SEC, 1 !! 540 cc->mult = 125; /* saturation after 195 years */
>> 541 cc->shift = 0;
644 542
645 nsec = 0; /* audio time is elapsed tim 543 nsec = 0; /* audio time is elapsed time since trigger */
646 timecounter_init(tc, cc, nsec); 544 timecounter_init(tc, cc, nsec);
647 if (force) { 545 if (force) {
648 /* 546 /*
649 * force timecounter to use pr 547 * force timecounter to use predefined value,
650 * used for synchronized start 548 * used for synchronized starts
651 */ 549 */
652 tc->cycle_last = last; 550 tc->cycle_last = last;
653 } 551 }
654 } 552 }
655 553
656 /** 554 /**
657 * snd_hdac_stream_timecounter_init - initiali 555 * snd_hdac_stream_timecounter_init - initialize time counter
658 * @azx_dev: HD-audio core stream (master stre 556 * @azx_dev: HD-audio core stream (master stream)
659 * @streams: bit flags of streams to set up 557 * @streams: bit flags of streams to set up
660 * @start: true for PCM trigger start, false f <<
661 * 558 *
662 * Initializes the time counter of streams mar 559 * Initializes the time counter of streams marked by the bit flags (each
663 * bit corresponds to the stream index). 560 * bit corresponds to the stream index).
664 * The trigger timestamp of PCM substream assi 561 * The trigger timestamp of PCM substream assigned to the given stream is
665 * updated accordingly, too. 562 * updated accordingly, too.
666 */ 563 */
667 void snd_hdac_stream_timecounter_init(struct h 564 void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
668 unsigned !! 565 unsigned int streams)
669 { 566 {
670 struct hdac_bus *bus = azx_dev->bus; 567 struct hdac_bus *bus = azx_dev->bus;
671 struct snd_pcm_runtime *runtime = azx_ 568 struct snd_pcm_runtime *runtime = azx_dev->substream->runtime;
672 struct hdac_stream *s; 569 struct hdac_stream *s;
673 bool inited = false; 570 bool inited = false;
674 u64 cycle_last = 0; 571 u64 cycle_last = 0;
675 !! 572 int i = 0;
676 if (!start) <<
677 goto skip; <<
678 573
679 list_for_each_entry(s, &bus->stream_li 574 list_for_each_entry(s, &bus->stream_list, list) {
680 if ((streams & (1 << s->index) !! 575 if (streams & (1 << i)) {
681 azx_timecounter_init(s 576 azx_timecounter_init(s, inited, cycle_last);
682 if (!inited) { 577 if (!inited) {
683 inited = true; 578 inited = true;
684 cycle_last = s 579 cycle_last = s->tc.cycle_last;
685 } 580 }
686 } 581 }
>> 582 i++;
687 } 583 }
688 584
689 skip: <<
690 snd_pcm_gettime(runtime, &runtime->tri 585 snd_pcm_gettime(runtime, &runtime->trigger_tstamp);
691 runtime->trigger_tstamp_latched = true 586 runtime->trigger_tstamp_latched = true;
692 } 587 }
693 EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_ 588 EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init);
694 589
695 /** 590 /**
696 * snd_hdac_stream_sync_trigger - turn on/off 591 * snd_hdac_stream_sync_trigger - turn on/off stream sync register
697 * @azx_dev: HD-audio core stream (master stre 592 * @azx_dev: HD-audio core stream (master stream)
698 * @set: true = set, false = clear 593 * @set: true = set, false = clear
699 * @streams: bit flags of streams to sync 594 * @streams: bit flags of streams to sync
700 * @reg: the stream sync register address 595 * @reg: the stream sync register address
701 */ 596 */
702 void snd_hdac_stream_sync_trigger(struct hdac_ 597 void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
703 unsigned int 598 unsigned int streams, unsigned int reg)
704 { 599 {
705 struct hdac_bus *bus = azx_dev->bus; 600 struct hdac_bus *bus = azx_dev->bus;
706 unsigned int val; 601 unsigned int val;
707 602
708 if (!reg) 603 if (!reg)
709 reg = AZX_REG_SSYNC; 604 reg = AZX_REG_SSYNC;
710 val = _snd_hdac_chip_readl(bus, reg); 605 val = _snd_hdac_chip_readl(bus, reg);
711 if (set) 606 if (set)
712 val |= streams; 607 val |= streams;
713 else 608 else
714 val &= ~streams; 609 val &= ~streams;
715 _snd_hdac_chip_writel(bus, reg, val); 610 _snd_hdac_chip_writel(bus, reg, val);
716 } 611 }
717 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger 612 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger);
718 613
719 /** 614 /**
720 * snd_hdac_stream_sync - sync with start/stop !! 615 * snd_hdac_stream_sync - sync with start/strop trigger operation
721 * @azx_dev: HD-audio core stream (master stre 616 * @azx_dev: HD-audio core stream (master stream)
722 * @start: true = start, false = stop 617 * @start: true = start, false = stop
723 * @streams: bit flags of streams to sync 618 * @streams: bit flags of streams to sync
724 * 619 *
725 * For @start = true, wait until all FIFOs get 620 * For @start = true, wait until all FIFOs get ready.
726 * For @start = false, wait until all RUN bits 621 * For @start = false, wait until all RUN bits are cleared.
727 */ 622 */
728 void snd_hdac_stream_sync(struct hdac_stream * 623 void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
729 unsigned int streams 624 unsigned int streams)
730 { 625 {
731 struct hdac_bus *bus = azx_dev->bus; 626 struct hdac_bus *bus = azx_dev->bus;
732 int nwait, timeout; !! 627 int i, nwait, timeout;
733 struct hdac_stream *s; 628 struct hdac_stream *s;
734 629
735 for (timeout = 5000; timeout; timeout- 630 for (timeout = 5000; timeout; timeout--) {
736 nwait = 0; 631 nwait = 0;
>> 632 i = 0;
737 list_for_each_entry(s, &bus->s 633 list_for_each_entry(s, &bus->stream_list, list) {
738 if (!(streams & (1 << !! 634 if (!(streams & (1 << i++)))
739 continue; 635 continue;
740 636
741 if (start) { 637 if (start) {
742 /* check FIFO 638 /* check FIFO gets ready */
743 if (!(snd_hdac 639 if (!(snd_hdac_stream_readb(s, SD_STS) &
744 SD_STS_F 640 SD_STS_FIFO_READY))
745 nwait+ 641 nwait++;
746 } else { 642 } else {
747 /* check RUN b 643 /* check RUN bit is cleared */
748 if (snd_hdac_s 644 if (snd_hdac_stream_readb(s, SD_CTL) &
749 SD_CTL_DMA 645 SD_CTL_DMA_START) {
750 nwait+ 646 nwait++;
751 /* 647 /*
752 * Per 648 * Perform stream reset if DMA RUN
753 * bit 649 * bit not cleared within given timeout
754 */ 650 */
755 if (ti 651 if (timeout == 1)
756 652 snd_hdac_stream_reset(s);
757 } 653 }
758 } 654 }
759 } 655 }
760 if (!nwait) 656 if (!nwait)
761 break; 657 break;
762 cpu_relax(); 658 cpu_relax();
763 } 659 }
764 } 660 }
765 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync); 661 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync);
766 662
767 /** <<
768 * snd_hdac_stream_spbcap_enable - enable SPIB <<
769 * @bus: HD-audio core bus <<
770 * @enable: flag to enable/disable SPIB <<
771 * @index: stream index for which SPIB need to <<
772 */ <<
773 void snd_hdac_stream_spbcap_enable(struct hdac <<
774 bool enable <<
775 { <<
776 u32 mask = 0; <<
777 <<
778 if (!bus->spbcap) { <<
779 dev_err(bus->dev, "Address of <<
780 return; <<
781 } <<
782 <<
783 mask |= (1 << index); <<
784 <<
785 if (enable) <<
786 snd_hdac_updatel(bus->spbcap, <<
787 else <<
788 snd_hdac_updatel(bus->spbcap, <<
789 } <<
790 EXPORT_SYMBOL_GPL(snd_hdac_stream_spbcap_enabl <<
791 <<
792 /** <<
793 * snd_hdac_stream_set_spib - sets the spib va <<
794 * @bus: HD-audio core bus <<
795 * @azx_dev: hdac_stream <<
796 * @value: spib value to set <<
797 */ <<
798 int snd_hdac_stream_set_spib(struct hdac_bus * <<
799 struct hdac_strea <<
800 { <<
801 if (!bus->spbcap) { <<
802 dev_err(bus->dev, "Address of <<
803 return -EINVAL; <<
804 } <<
805 <<
806 writel(value, azx_dev->spib_addr); <<
807 <<
808 return 0; <<
809 } <<
810 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_spib); <<
811 <<
812 /** <<
813 * snd_hdac_stream_get_spbmaxfifo - gets the s <<
814 * @bus: HD-audio core bus <<
815 * @azx_dev: hdac_stream <<
816 * <<
817 * Return maxfifo for the stream <<
818 */ <<
819 int snd_hdac_stream_get_spbmaxfifo(struct hdac <<
820 struct hdac <<
821 { <<
822 if (!bus->spbcap) { <<
823 dev_err(bus->dev, "Address of <<
824 return -EINVAL; <<
825 } <<
826 <<
827 return readl(azx_dev->fifo_addr); <<
828 } <<
829 EXPORT_SYMBOL_GPL(snd_hdac_stream_get_spbmaxfi <<
830 <<
831 /** <<
832 * snd_hdac_stream_drsm_enable - enable DMA re <<
833 * @bus: HD-audio core bus <<
834 * @enable: flag to enable/disable DRSM <<
835 * @index: stream index for which DRSM need to <<
836 */ <<
837 void snd_hdac_stream_drsm_enable(struct hdac_b <<
838 bool enable, <<
839 { <<
840 u32 mask = 0; <<
841 <<
842 if (!bus->drsmcap) { <<
843 dev_err(bus->dev, "Address of <<
844 return; <<
845 } <<
846 <<
847 mask |= (1 << index); <<
848 <<
849 if (enable) <<
850 snd_hdac_updatel(bus->drsmcap, <<
851 else <<
852 snd_hdac_updatel(bus->drsmcap, <<
853 } <<
854 EXPORT_SYMBOL_GPL(snd_hdac_stream_drsm_enable) <<
855 <<
856 /* <<
857 * snd_hdac_stream_wait_drsm - wait for HW to <<
858 * @azx_dev: HD-audio core stream to await RSM <<
859 * <<
860 * Returns 0 on success and -ETIMEDOUT upon a <<
861 */ <<
862 int snd_hdac_stream_wait_drsm(struct hdac_stre <<
863 { <<
864 struct hdac_bus *bus = azx_dev->bus; <<
865 u32 mask, reg; <<
866 int ret; <<
867 <<
868 mask = 1 << azx_dev->index; <<
869 <<
870 ret = read_poll_timeout(snd_hdac_reg_r <<
871 bus->drsmcap + <<
872 if (ret) <<
873 dev_dbg(bus->dev, "polling RSM <<
874 return ret; <<
875 } <<
876 EXPORT_SYMBOL_GPL(snd_hdac_stream_wait_drsm); <<
877 <<
878 /** <<
879 * snd_hdac_stream_set_dpibr - sets the dpibr <<
880 * @bus: HD-audio core bus <<
881 * @azx_dev: hdac_stream <<
882 * @value: dpib value to set <<
883 */ <<
884 int snd_hdac_stream_set_dpibr(struct hdac_bus <<
885 struct hdac_stre <<
886 { <<
887 if (!bus->drsmcap) { <<
888 dev_err(bus->dev, "Address of <<
889 return -EINVAL; <<
890 } <<
891 <<
892 writel(value, azx_dev->dpibr_addr); <<
893 <<
894 return 0; <<
895 } <<
896 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_dpibr); <<
897 <<
898 /** <<
899 * snd_hdac_stream_set_lpib - sets the lpib va <<
900 * @azx_dev: hdac_stream <<
901 * @value: lpib value to set <<
902 */ <<
903 int snd_hdac_stream_set_lpib(struct hdac_strea <<
904 { <<
905 snd_hdac_stream_writel(azx_dev, SD_LPI <<
906 <<
907 return 0; <<
908 } <<
909 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_lpib); <<
910 <<
911 #ifdef CONFIG_SND_HDA_DSP_LOADER 663 #ifdef CONFIG_SND_HDA_DSP_LOADER
912 /** 664 /**
913 * snd_hdac_dsp_prepare - prepare for DSP load 665 * snd_hdac_dsp_prepare - prepare for DSP loading
914 * @azx_dev: HD-audio core stream used for DSP 666 * @azx_dev: HD-audio core stream used for DSP loading
915 * @format: HD-audio stream format 667 * @format: HD-audio stream format
916 * @byte_size: data chunk byte size 668 * @byte_size: data chunk byte size
917 * @bufp: allocated buffer 669 * @bufp: allocated buffer
918 * 670 *
919 * Allocate the buffer for the given size and 671 * Allocate the buffer for the given size and set up the given stream for
920 * DSP loading. Returns the stream tag (>= 0) 672 * DSP loading. Returns the stream tag (>= 0), or a negative error code.
921 */ 673 */
922 int snd_hdac_dsp_prepare(struct hdac_stream *a 674 int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
923 unsigned int byte_siz 675 unsigned int byte_size, struct snd_dma_buffer *bufp)
924 { 676 {
925 struct hdac_bus *bus = azx_dev->bus; 677 struct hdac_bus *bus = azx_dev->bus;
926 __le32 *bdl; 678 __le32 *bdl;
927 int err; 679 int err;
928 680
929 snd_hdac_dsp_lock(azx_dev); 681 snd_hdac_dsp_lock(azx_dev);
930 spin_lock_irq(&bus->reg_lock); 682 spin_lock_irq(&bus->reg_lock);
931 if (azx_dev->running || azx_dev->locke 683 if (azx_dev->running || azx_dev->locked) {
932 spin_unlock_irq(&bus->reg_lock 684 spin_unlock_irq(&bus->reg_lock);
933 err = -EBUSY; 685 err = -EBUSY;
934 goto unlock; 686 goto unlock;
935 } 687 }
936 azx_dev->locked = true; 688 azx_dev->locked = true;
937 spin_unlock_irq(&bus->reg_lock); 689 spin_unlock_irq(&bus->reg_lock);
938 690
939 err = snd_dma_alloc_pages(SNDRV_DMA_TY 691 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, bus->dev,
940 byte_size, b 692 byte_size, bufp);
941 if (err < 0) 693 if (err < 0)
942 goto err_alloc; 694 goto err_alloc;
943 695
944 azx_dev->substream = NULL; 696 azx_dev->substream = NULL;
945 azx_dev->bufsize = byte_size; 697 azx_dev->bufsize = byte_size;
946 azx_dev->period_bytes = byte_size; 698 azx_dev->period_bytes = byte_size;
947 azx_dev->format_val = format; 699 azx_dev->format_val = format;
948 700
949 snd_hdac_stream_reset(azx_dev); 701 snd_hdac_stream_reset(azx_dev);
950 702
951 /* reset BDL address */ 703 /* reset BDL address */
952 snd_hdac_stream_writel(azx_dev, SD_BDL 704 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
953 snd_hdac_stream_writel(azx_dev, SD_BDL 705 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
954 706
955 azx_dev->frags = 0; 707 azx_dev->frags = 0;
956 bdl = (__le32 *)azx_dev->bdl.area; 708 bdl = (__le32 *)azx_dev->bdl.area;
957 err = setup_bdle(bus, bufp, azx_dev, & 709 err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0);
958 if (err < 0) 710 if (err < 0)
959 goto error; 711 goto error;
960 712
961 snd_hdac_stream_setup(azx_dev, true); !! 713 snd_hdac_stream_setup(azx_dev);
962 snd_hdac_dsp_unlock(azx_dev); 714 snd_hdac_dsp_unlock(azx_dev);
963 return azx_dev->stream_tag; 715 return azx_dev->stream_tag;
964 716
965 error: 717 error:
966 snd_dma_free_pages(bufp); 718 snd_dma_free_pages(bufp);
967 err_alloc: 719 err_alloc:
968 spin_lock_irq(&bus->reg_lock); 720 spin_lock_irq(&bus->reg_lock);
969 azx_dev->locked = false; 721 azx_dev->locked = false;
970 spin_unlock_irq(&bus->reg_lock); 722 spin_unlock_irq(&bus->reg_lock);
971 unlock: 723 unlock:
972 snd_hdac_dsp_unlock(azx_dev); 724 snd_hdac_dsp_unlock(azx_dev);
973 return err; 725 return err;
974 } 726 }
975 EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare); 727 EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare);
976 728
977 /** 729 /**
978 * snd_hdac_dsp_trigger - start / stop DSP loa 730 * snd_hdac_dsp_trigger - start / stop DSP loading
979 * @azx_dev: HD-audio core stream used for DSP 731 * @azx_dev: HD-audio core stream used for DSP loading
980 * @start: trigger start or stop 732 * @start: trigger start or stop
981 */ 733 */
982 void snd_hdac_dsp_trigger(struct hdac_stream * 734 void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
983 { 735 {
984 if (start) 736 if (start)
985 snd_hdac_stream_start(azx_dev) !! 737 snd_hdac_stream_start(azx_dev, true);
986 else 738 else
987 snd_hdac_stream_stop(azx_dev); 739 snd_hdac_stream_stop(azx_dev);
988 } 740 }
989 EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger); 741 EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger);
990 742
991 /** 743 /**
992 * snd_hdac_dsp_cleanup - clean up the stream 744 * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal
993 * @azx_dev: HD-audio core stream used for DSP 745 * @azx_dev: HD-audio core stream used for DSP loading
994 * @dmab: buffer used by DSP loading 746 * @dmab: buffer used by DSP loading
995 */ 747 */
996 void snd_hdac_dsp_cleanup(struct hdac_stream * 748 void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
997 struct snd_dma_buffe 749 struct snd_dma_buffer *dmab)
998 { 750 {
999 struct hdac_bus *bus = azx_dev->bus; 751 struct hdac_bus *bus = azx_dev->bus;
1000 752
1001 if (!dmab->area || !azx_dev->locked) 753 if (!dmab->area || !azx_dev->locked)
1002 return; 754 return;
1003 755
1004 snd_hdac_dsp_lock(azx_dev); 756 snd_hdac_dsp_lock(azx_dev);
1005 /* reset BDL address */ 757 /* reset BDL address */
1006 snd_hdac_stream_writel(azx_dev, SD_BD 758 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
1007 snd_hdac_stream_writel(azx_dev, SD_BD 759 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
1008 snd_hdac_stream_writel(azx_dev, SD_CT 760 snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
1009 azx_dev->bufsize = 0; 761 azx_dev->bufsize = 0;
1010 azx_dev->period_bytes = 0; 762 azx_dev->period_bytes = 0;
1011 azx_dev->format_val = 0; 763 azx_dev->format_val = 0;
1012 764
1013 snd_dma_free_pages(dmab); 765 snd_dma_free_pages(dmab);
1014 dmab->area = NULL; 766 dmab->area = NULL;
1015 767
1016 spin_lock_irq(&bus->reg_lock); 768 spin_lock_irq(&bus->reg_lock);
1017 azx_dev->locked = false; 769 azx_dev->locked = false;
1018 spin_unlock_irq(&bus->reg_lock); 770 spin_unlock_irq(&bus->reg_lock);
1019 snd_hdac_dsp_unlock(azx_dev); 771 snd_hdac_dsp_unlock(azx_dev);
1020 } 772 }
1021 EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup); 773 EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup);
1022 #endif /* CONFIG_SND_HDA_DSP_LOADER */ 774 #endif /* CONFIG_SND_HDA_DSP_LOADER */
1023 775
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