1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* 2 /*
3 * HD-audio stream operations 3 * HD-audio stream operations
4 */ 4 */
5 5
6 #include <linux/kernel.h> 6 #include <linux/kernel.h>
7 #include <linux/delay.h> 7 #include <linux/delay.h>
8 #include <linux/export.h> 8 #include <linux/export.h>
9 #include <linux/clocksource.h> 9 #include <linux/clocksource.h>
10 #include <sound/compress_driver.h> 10 #include <sound/compress_driver.h>
11 #include <sound/core.h> 11 #include <sound/core.h>
12 #include <sound/pcm.h> 12 #include <sound/pcm.h>
13 #include <sound/hdaudio.h> 13 #include <sound/hdaudio.h>
14 #include <sound/hda_register.h> 14 #include <sound/hda_register.h>
15 #include "trace.h" 15 #include "trace.h"
16 16
17 /* 17 /*
18 * the hdac_stream library is intended to be u 18 * the hdac_stream library is intended to be used with the following
19 * transitions. The states are not formally de 19 * transitions. The states are not formally defined in the code but loosely
20 * inspired by boolean variables. Note that th 20 * inspired by boolean variables. Note that the 'prepared' field is not used
21 * in this library but by the callers during t 21 * in this library but by the callers during the hw_params/prepare transitions
22 * 22 *
23 * | 23 * |
24 * stream_init() | 24 * stream_init() |
25 * v 25 * v
26 * +--+-------+ 26 * +--+-------+
27 * | unused | 27 * | unused |
28 * +--+----+--+ 28 * +--+----+--+
29 * | ^ 29 * | ^
30 * stream_assign() | | stream_re 30 * stream_assign() | | stream_release()
31 * v | 31 * v |
32 * +--+----+--+ 32 * +--+----+--+
33 * | opened | 33 * | opened |
34 * +--+----+--+ 34 * +--+----+--+
35 * | ^ 35 * | ^
36 * stream_reset() | | 36 * stream_reset() | |
37 * stream_setup() | | stream_cl 37 * stream_setup() | | stream_cleanup()
38 * v | 38 * v |
39 * +--+----+--+ 39 * +--+----+--+
40 * | prepared | 40 * | prepared |
41 * +--+----+--+ 41 * +--+----+--+
42 * | ^ 42 * | ^
43 * stream_start() | | stream_st 43 * stream_start() | | stream_stop()
44 * v | 44 * v |
45 * +--+----+--+ 45 * +--+----+--+
46 * | running | 46 * | running |
47 * +----------+ 47 * +----------+
48 */ 48 */
49 49
50 /** 50 /**
51 * snd_hdac_get_stream_stripe_ctl - get stripe 51 * snd_hdac_get_stream_stripe_ctl - get stripe control value
52 * @bus: HD-audio core bus 52 * @bus: HD-audio core bus
53 * @substream: PCM substream 53 * @substream: PCM substream
54 */ 54 */
55 int snd_hdac_get_stream_stripe_ctl(struct hdac 55 int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,
56 struct snd_ 56 struct snd_pcm_substream *substream)
57 { 57 {
58 struct snd_pcm_runtime *runtime = subs 58 struct snd_pcm_runtime *runtime = substream->runtime;
59 unsigned int channels = runtime->chann 59 unsigned int channels = runtime->channels,
60 rate = runtime->rate, 60 rate = runtime->rate,
61 bits_per_sample = runtime 61 bits_per_sample = runtime->sample_bits,
62 max_sdo_lines, value, sdo 62 max_sdo_lines, value, sdo_line;
63 63
64 /* T_AZA_GCAP_NSDO is 1:2 bitfields in 64 /* T_AZA_GCAP_NSDO is 1:2 bitfields in GCAP */
65 max_sdo_lines = snd_hdac_chip_readl(bu 65 max_sdo_lines = snd_hdac_chip_readl(bus, GCAP) & AZX_GCAP_NSDO;
66 66
67 /* following is from HD audio spec */ 67 /* following is from HD audio spec */
68 for (sdo_line = max_sdo_lines; sdo_lin 68 for (sdo_line = max_sdo_lines; sdo_line > 0; sdo_line >>= 1) {
69 if (rate > 48000) 69 if (rate > 48000)
70 value = (channels * bi 70 value = (channels * bits_per_sample *
71 (rate 71 (rate / 48000)) / sdo_line;
72 else 72 else
73 value = (channels * bi 73 value = (channels * bits_per_sample) / sdo_line;
74 74
75 if (value >= bus->sdo_limit) 75 if (value >= bus->sdo_limit)
76 break; 76 break;
77 } 77 }
78 78
79 /* stripe value: 0 for 1SDO, 1 for 2SD 79 /* stripe value: 0 for 1SDO, 1 for 2SDO, 2 for 4SDO lines */
80 return sdo_line >> 1; 80 return sdo_line >> 1;
81 } 81 }
82 EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_c 82 EXPORT_SYMBOL_GPL(snd_hdac_get_stream_stripe_ctl);
83 83
84 /** 84 /**
85 * snd_hdac_stream_init - initialize each stre 85 * snd_hdac_stream_init - initialize each stream (aka device)
86 * @bus: HD-audio core bus 86 * @bus: HD-audio core bus
87 * @azx_dev: HD-audio core stream object to in 87 * @azx_dev: HD-audio core stream object to initialize
88 * @idx: stream index number 88 * @idx: stream index number
89 * @direction: stream direction (SNDRV_PCM_STR 89 * @direction: stream direction (SNDRV_PCM_STREAM_PLAYBACK or SNDRV_PCM_STREAM_CAPTURE)
90 * @tag: the tag id to assign 90 * @tag: the tag id to assign
91 * 91 *
92 * Assign the starting bdl address to each str 92 * Assign the starting bdl address to each stream (device) and initialize.
93 */ 93 */
94 void snd_hdac_stream_init(struct hdac_bus *bus 94 void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
95 int idx, int directi 95 int idx, int direction, int tag)
96 { 96 {
97 azx_dev->bus = bus; 97 azx_dev->bus = bus;
98 /* offset: SDI0=0x80, SDI1=0xa0, ... S 98 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
99 azx_dev->sd_addr = bus->remap_addr + ( 99 azx_dev->sd_addr = bus->remap_addr + (0x20 * idx + 0x80);
100 /* int mask: SDI0=0x01, SDI1=0x02, ... 100 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
101 azx_dev->sd_int_sta_mask = 1 << idx; 101 azx_dev->sd_int_sta_mask = 1 << idx;
102 azx_dev->index = idx; 102 azx_dev->index = idx;
103 azx_dev->direction = direction; 103 azx_dev->direction = direction;
104 azx_dev->stream_tag = tag; 104 azx_dev->stream_tag = tag;
105 snd_hdac_dsp_lock_init(azx_dev); 105 snd_hdac_dsp_lock_init(azx_dev);
106 list_add_tail(&azx_dev->list, &bus->st 106 list_add_tail(&azx_dev->list, &bus->stream_list);
107 107
108 if (bus->spbcap) { 108 if (bus->spbcap) {
109 azx_dev->spib_addr = bus->spbc 109 azx_dev->spib_addr = bus->spbcap + AZX_SPB_BASE +
110 AZX_SP 110 AZX_SPB_INTERVAL * idx +
111 AZX_SP 111 AZX_SPB_SPIB;
112 112
113 azx_dev->fifo_addr = bus->spbc 113 azx_dev->fifo_addr = bus->spbcap + AZX_SPB_BASE +
114 AZX_SP 114 AZX_SPB_INTERVAL * idx +
115 AZX_SP 115 AZX_SPB_MAXFIFO;
116 } 116 }
117 117
118 if (bus->drsmcap) 118 if (bus->drsmcap)
119 azx_dev->dpibr_addr = bus->drs 119 azx_dev->dpibr_addr = bus->drsmcap + AZX_DRSM_BASE +
120 AZX_DR 120 AZX_DRSM_INTERVAL * idx;
121 } 121 }
122 EXPORT_SYMBOL_GPL(snd_hdac_stream_init); 122 EXPORT_SYMBOL_GPL(snd_hdac_stream_init);
123 123
124 /** 124 /**
125 * snd_hdac_stream_start - start a stream 125 * snd_hdac_stream_start - start a stream
126 * @azx_dev: HD-audio core stream to start 126 * @azx_dev: HD-audio core stream to start
127 * 127 *
128 * Start a stream, set start_wallclk and set t 128 * Start a stream, set start_wallclk and set the running flag.
129 */ 129 */
130 void snd_hdac_stream_start(struct hdac_stream 130 void snd_hdac_stream_start(struct hdac_stream *azx_dev)
131 { 131 {
132 struct hdac_bus *bus = azx_dev->bus; 132 struct hdac_bus *bus = azx_dev->bus;
133 int stripe_ctl; 133 int stripe_ctl;
134 134
135 trace_snd_hdac_stream_start(bus, azx_d 135 trace_snd_hdac_stream_start(bus, azx_dev);
136 136
137 azx_dev->start_wallclk = snd_hdac_chip 137 azx_dev->start_wallclk = snd_hdac_chip_readl(bus, WALLCLK);
138 138
139 /* enable SIE */ 139 /* enable SIE */
140 snd_hdac_chip_updatel(bus, INTCTL, 140 snd_hdac_chip_updatel(bus, INTCTL,
141 1 << azx_dev->in 141 1 << azx_dev->index,
142 1 << azx_dev->in 142 1 << azx_dev->index);
143 /* set stripe control */ 143 /* set stripe control */
144 if (azx_dev->stripe) { 144 if (azx_dev->stripe) {
145 if (azx_dev->substream) 145 if (azx_dev->substream)
146 stripe_ctl = snd_hdac_ 146 stripe_ctl = snd_hdac_get_stream_stripe_ctl(bus, azx_dev->substream);
147 else 147 else
148 stripe_ctl = 0; 148 stripe_ctl = 0;
149 snd_hdac_stream_updateb(azx_de 149 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK,
150 stripe 150 stripe_ctl);
151 } 151 }
152 /* set DMA start and interrupt mask */ 152 /* set DMA start and interrupt mask */
153 if (bus->access_sdnctl_in_dword) !! 153 snd_hdac_stream_updateb(azx_dev, SD_CTL,
154 snd_hdac_stream_updatel(azx_de <<
155 0, SD_CTL_DMA_ <<
156 else <<
157 snd_hdac_stream_updateb(azx_de <<
158 0, SD_CTL_DMA_ 154 0, SD_CTL_DMA_START | SD_INT_MASK);
159 azx_dev->running = true; 155 azx_dev->running = true;
160 } 156 }
161 EXPORT_SYMBOL_GPL(snd_hdac_stream_start); 157 EXPORT_SYMBOL_GPL(snd_hdac_stream_start);
162 158
163 /** 159 /**
164 * snd_hdac_stream_clear - helper to clear str 160 * snd_hdac_stream_clear - helper to clear stream registers and stop DMA transfers
165 * @azx_dev: HD-audio core stream to stop 161 * @azx_dev: HD-audio core stream to stop
166 */ 162 */
167 static void snd_hdac_stream_clear(struct hdac_ 163 static void snd_hdac_stream_clear(struct hdac_stream *azx_dev)
168 { 164 {
169 snd_hdac_stream_updateb(azx_dev, SD_CT 165 snd_hdac_stream_updateb(azx_dev, SD_CTL,
170 SD_CTL_DMA_STA 166 SD_CTL_DMA_START | SD_INT_MASK, 0);
171 snd_hdac_stream_writeb(azx_dev, SD_STS 167 snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
172 if (azx_dev->stripe) 168 if (azx_dev->stripe)
173 snd_hdac_stream_updateb(azx_de 169 snd_hdac_stream_updateb(azx_dev, SD_CTL_3B, SD_CTL_STRIPE_MASK, 0);
174 azx_dev->running = false; 170 azx_dev->running = false;
175 } 171 }
176 172
177 /** 173 /**
178 * snd_hdac_stream_stop - stop a stream 174 * snd_hdac_stream_stop - stop a stream
179 * @azx_dev: HD-audio core stream to stop 175 * @azx_dev: HD-audio core stream to stop
180 * 176 *
181 * Stop a stream DMA and disable stream interr 177 * Stop a stream DMA and disable stream interrupt
182 */ 178 */
183 void snd_hdac_stream_stop(struct hdac_stream * 179 void snd_hdac_stream_stop(struct hdac_stream *azx_dev)
184 { 180 {
185 trace_snd_hdac_stream_stop(azx_dev->bu 181 trace_snd_hdac_stream_stop(azx_dev->bus, azx_dev);
186 182
187 snd_hdac_stream_clear(azx_dev); 183 snd_hdac_stream_clear(azx_dev);
188 /* disable SIE */ 184 /* disable SIE */
189 snd_hdac_chip_updatel(azx_dev->bus, IN 185 snd_hdac_chip_updatel(azx_dev->bus, INTCTL, 1 << azx_dev->index, 0);
190 } 186 }
191 EXPORT_SYMBOL_GPL(snd_hdac_stream_stop); 187 EXPORT_SYMBOL_GPL(snd_hdac_stream_stop);
192 188
193 /** 189 /**
194 * snd_hdac_stop_streams - stop all streams 190 * snd_hdac_stop_streams - stop all streams
195 * @bus: HD-audio core bus 191 * @bus: HD-audio core bus
196 */ 192 */
197 void snd_hdac_stop_streams(struct hdac_bus *bu 193 void snd_hdac_stop_streams(struct hdac_bus *bus)
198 { 194 {
199 struct hdac_stream *stream; 195 struct hdac_stream *stream;
200 196
201 list_for_each_entry(stream, &bus->stre 197 list_for_each_entry(stream, &bus->stream_list, list)
202 snd_hdac_stream_stop(stream); 198 snd_hdac_stream_stop(stream);
203 } 199 }
204 EXPORT_SYMBOL_GPL(snd_hdac_stop_streams); 200 EXPORT_SYMBOL_GPL(snd_hdac_stop_streams);
205 201
206 /** 202 /**
207 * snd_hdac_stop_streams_and_chip - stop all s 203 * snd_hdac_stop_streams_and_chip - stop all streams and chip if running
208 * @bus: HD-audio core bus 204 * @bus: HD-audio core bus
209 */ 205 */
210 void snd_hdac_stop_streams_and_chip(struct hda 206 void snd_hdac_stop_streams_and_chip(struct hdac_bus *bus)
211 { 207 {
212 208
213 if (bus->chip_init) { 209 if (bus->chip_init) {
214 snd_hdac_stop_streams(bus); 210 snd_hdac_stop_streams(bus);
215 snd_hdac_bus_stop_chip(bus); 211 snd_hdac_bus_stop_chip(bus);
216 } 212 }
217 } 213 }
218 EXPORT_SYMBOL_GPL(snd_hdac_stop_streams_and_ch 214 EXPORT_SYMBOL_GPL(snd_hdac_stop_streams_and_chip);
219 215
220 /** 216 /**
221 * snd_hdac_stream_reset - reset a stream 217 * snd_hdac_stream_reset - reset a stream
222 * @azx_dev: HD-audio core stream to reset 218 * @azx_dev: HD-audio core stream to reset
223 */ 219 */
224 void snd_hdac_stream_reset(struct hdac_stream 220 void snd_hdac_stream_reset(struct hdac_stream *azx_dev)
225 { 221 {
226 unsigned char val; 222 unsigned char val;
227 int dma_run_state; 223 int dma_run_state;
228 224
229 snd_hdac_stream_clear(azx_dev); 225 snd_hdac_stream_clear(azx_dev);
230 226
231 dma_run_state = snd_hdac_stream_readb( 227 dma_run_state = snd_hdac_stream_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START;
232 228
233 snd_hdac_stream_updateb(azx_dev, SD_CT 229 snd_hdac_stream_updateb(azx_dev, SD_CTL, 0, SD_CTL_STREAM_RESET);
234 230
235 /* wait for hardware to report that th 231 /* wait for hardware to report that the stream entered reset */
236 snd_hdac_stream_readb_poll(azx_dev, SD 232 snd_hdac_stream_readb_poll(azx_dev, SD_CTL, val, (val & SD_CTL_STREAM_RESET), 3, 300);
237 233
238 if (azx_dev->bus->dma_stop_delay && dm 234 if (azx_dev->bus->dma_stop_delay && dma_run_state)
239 udelay(azx_dev->bus->dma_stop_ 235 udelay(azx_dev->bus->dma_stop_delay);
240 236
241 snd_hdac_stream_updateb(azx_dev, SD_CT 237 snd_hdac_stream_updateb(azx_dev, SD_CTL, SD_CTL_STREAM_RESET, 0);
242 238
243 /* wait for hardware to report that th 239 /* wait for hardware to report that the stream is out of reset */
244 snd_hdac_stream_readb_poll(azx_dev, SD 240 snd_hdac_stream_readb_poll(azx_dev, SD_CTL, val, !(val & SD_CTL_STREAM_RESET), 3, 300);
245 241
246 /* reset first position - may not be s 242 /* reset first position - may not be synced with hw at this time */
247 if (azx_dev->posbuf) 243 if (azx_dev->posbuf)
248 *azx_dev->posbuf = 0; 244 *azx_dev->posbuf = 0;
249 } 245 }
250 EXPORT_SYMBOL_GPL(snd_hdac_stream_reset); 246 EXPORT_SYMBOL_GPL(snd_hdac_stream_reset);
251 247
252 /** 248 /**
253 * snd_hdac_stream_setup - set up the SD for 249 * snd_hdac_stream_setup - set up the SD for streaming
254 * @azx_dev: HD-audio core stream to set up 250 * @azx_dev: HD-audio core stream to set up
255 * @code_loading: Whether the stream is for PC <<
256 */ 251 */
257 int snd_hdac_stream_setup(struct hdac_stream * !! 252 int snd_hdac_stream_setup(struct hdac_stream *azx_dev)
258 { 253 {
259 struct hdac_bus *bus = azx_dev->bus; 254 struct hdac_bus *bus = azx_dev->bus;
260 struct snd_pcm_runtime *runtime; 255 struct snd_pcm_runtime *runtime;
261 unsigned int val; 256 unsigned int val;
262 u16 reg; <<
263 int ret; <<
264 257
265 if (azx_dev->substream) 258 if (azx_dev->substream)
266 runtime = azx_dev->substream-> 259 runtime = azx_dev->substream->runtime;
267 else 260 else
268 runtime = NULL; 261 runtime = NULL;
269 /* make sure the run bit is zero for S 262 /* make sure the run bit is zero for SD */
270 snd_hdac_stream_clear(azx_dev); 263 snd_hdac_stream_clear(azx_dev);
271 /* program the stream_tag */ 264 /* program the stream_tag */
272 val = snd_hdac_stream_readl(azx_dev, S 265 val = snd_hdac_stream_readl(azx_dev, SD_CTL);
273 val = (val & ~SD_CTL_STREAM_TAG_MASK) 266 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
274 (azx_dev->stream_tag << SD_CTL 267 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
275 if (!bus->snoop) 268 if (!bus->snoop)
276 val |= SD_CTL_TRAFFIC_PRIO; 269 val |= SD_CTL_TRAFFIC_PRIO;
277 snd_hdac_stream_writel(azx_dev, SD_CTL 270 snd_hdac_stream_writel(azx_dev, SD_CTL, val);
278 271
279 /* program the length of samples in cy 272 /* program the length of samples in cyclic buffer */
280 snd_hdac_stream_writel(azx_dev, SD_CBL 273 snd_hdac_stream_writel(azx_dev, SD_CBL, azx_dev->bufsize);
281 274
282 /* program the stream format */ 275 /* program the stream format */
283 /* this value needs to be the same as 276 /* this value needs to be the same as the one programmed */
284 snd_hdac_stream_writew(azx_dev, SD_FOR 277 snd_hdac_stream_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
285 278
286 /* program the stream LVI (last valid 279 /* program the stream LVI (last valid index) of the BDL */
287 snd_hdac_stream_writew(azx_dev, SD_LVI 280 snd_hdac_stream_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
288 281
289 /* program the BDL address */ 282 /* program the BDL address */
290 /* lower BDL address */ 283 /* lower BDL address */
291 snd_hdac_stream_writel(azx_dev, SD_BDL 284 snd_hdac_stream_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
292 /* upper BDL address */ 285 /* upper BDL address */
293 snd_hdac_stream_writel(azx_dev, SD_BDL 286 snd_hdac_stream_writel(azx_dev, SD_BDLPU,
294 upper_32_bits(a 287 upper_32_bits(azx_dev->bdl.addr));
295 288
296 /* enable the position buffer */ 289 /* enable the position buffer */
297 if (bus->use_posbuf && bus->posbuf.add 290 if (bus->use_posbuf && bus->posbuf.addr) {
298 if (!(snd_hdac_chip_readl(bus, 291 if (!(snd_hdac_chip_readl(bus, DPLBASE) & AZX_DPLBASE_ENABLE))
299 snd_hdac_chip_writel(b 292 snd_hdac_chip_writel(bus, DPLBASE,
300 (u32)bus->posb 293 (u32)bus->posbuf.addr | AZX_DPLBASE_ENABLE);
301 } 294 }
302 295
303 /* set the interrupt enable bits in th 296 /* set the interrupt enable bits in the descriptor control register */
304 snd_hdac_stream_updatel(azx_dev, SD_CT 297 snd_hdac_stream_updatel(azx_dev, SD_CTL, 0, SD_INT_MASK);
305 298
306 if (!code_loading) { !! 299 azx_dev->fifo_size = snd_hdac_stream_readw(azx_dev, SD_FIFOSIZE) + 1;
307 /* Once SDxFMT is set, the con <<
308 ret = snd_hdac_stream_readw_po <<
309 <<
310 if (ret) <<
311 dev_dbg(bus->dev, "pol <<
312 AZX_REG_SD_FIF <<
313 azx_dev->fifo_size = reg; <<
314 } <<
315 300
316 /* when LPIB delay correction gives a 301 /* when LPIB delay correction gives a small negative value,
317 * we ignore it; currently set the thr 302 * we ignore it; currently set the threshold statically to
318 * 64 frames 303 * 64 frames
319 */ 304 */
320 if (runtime && runtime->period_size > 305 if (runtime && runtime->period_size > 64)
321 azx_dev->delay_negative_thresh 306 azx_dev->delay_negative_threshold =
322 -frames_to_bytes(runti 307 -frames_to_bytes(runtime, 64);
323 else 308 else
324 azx_dev->delay_negative_thresh 309 azx_dev->delay_negative_threshold = 0;
325 310
326 /* wallclk has 24Mhz clock source */ 311 /* wallclk has 24Mhz clock source */
327 if (runtime) 312 if (runtime)
328 azx_dev->period_wallclk = (((r 313 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
329 runtime->r 314 runtime->rate) * 1000);
330 315
331 return 0; 316 return 0;
332 } 317 }
333 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup); 318 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup);
334 319
335 /** 320 /**
336 * snd_hdac_stream_cleanup - cleanup a stream 321 * snd_hdac_stream_cleanup - cleanup a stream
337 * @azx_dev: HD-audio core stream to clean up 322 * @azx_dev: HD-audio core stream to clean up
338 */ 323 */
339 void snd_hdac_stream_cleanup(struct hdac_strea 324 void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev)
340 { 325 {
341 snd_hdac_stream_writel(azx_dev, SD_BDL 326 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
342 snd_hdac_stream_writel(azx_dev, SD_BDL 327 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
343 snd_hdac_stream_writel(azx_dev, SD_CTL 328 snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
344 azx_dev->bufsize = 0; 329 azx_dev->bufsize = 0;
345 azx_dev->period_bytes = 0; 330 azx_dev->period_bytes = 0;
346 azx_dev->format_val = 0; 331 azx_dev->format_val = 0;
347 } 332 }
348 EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup); 333 EXPORT_SYMBOL_GPL(snd_hdac_stream_cleanup);
349 334
350 /** 335 /**
351 * snd_hdac_stream_assign - assign a stream fo 336 * snd_hdac_stream_assign - assign a stream for the PCM
352 * @bus: HD-audio core bus 337 * @bus: HD-audio core bus
353 * @substream: PCM substream to assign 338 * @substream: PCM substream to assign
354 * 339 *
355 * Look for an unused stream for the given PCM 340 * Look for an unused stream for the given PCM substream, assign it
356 * and return the stream object. If no stream 341 * and return the stream object. If no stream is free, returns NULL.
357 * The function tries to keep using the same s 342 * The function tries to keep using the same stream object when it's used
358 * beforehand. Also, when bus->reverse_assign 343 * beforehand. Also, when bus->reverse_assign flag is set, the last free
359 * or matching entry is returned. This is nee 344 * or matching entry is returned. This is needed for some strange codecs.
360 */ 345 */
361 struct hdac_stream *snd_hdac_stream_assign(str 346 struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
362 str 347 struct snd_pcm_substream *substream)
363 { 348 {
364 struct hdac_stream *azx_dev; 349 struct hdac_stream *azx_dev;
365 struct hdac_stream *res = NULL; 350 struct hdac_stream *res = NULL;
366 351
367 /* make a non-zero unique key for the 352 /* make a non-zero unique key for the substream */
368 int key = (substream->number << 2) | ( !! 353 int key = (substream->pcm->device << 16) | (substream->number << 2) |
369 !! 354 (substream->stream + 1);
370 if (substream->pcm) <<
371 key |= (substream->pcm->device <<
372 355
373 spin_lock_irq(&bus->reg_lock); 356 spin_lock_irq(&bus->reg_lock);
374 list_for_each_entry(azx_dev, &bus->str 357 list_for_each_entry(azx_dev, &bus->stream_list, list) {
375 if (azx_dev->direction != subs 358 if (azx_dev->direction != substream->stream)
376 continue; 359 continue;
377 if (azx_dev->opened) 360 if (azx_dev->opened)
378 continue; 361 continue;
379 if (azx_dev->assigned_key == k 362 if (azx_dev->assigned_key == key) {
380 res = azx_dev; 363 res = azx_dev;
381 break; 364 break;
382 } 365 }
383 if (!res || bus->reverse_assig 366 if (!res || bus->reverse_assign)
384 res = azx_dev; 367 res = azx_dev;
385 } 368 }
386 if (res) { 369 if (res) {
387 res->opened = 1; 370 res->opened = 1;
388 res->running = 0; 371 res->running = 0;
389 res->assigned_key = key; 372 res->assigned_key = key;
390 res->substream = substream; 373 res->substream = substream;
391 } 374 }
392 spin_unlock_irq(&bus->reg_lock); 375 spin_unlock_irq(&bus->reg_lock);
393 return res; 376 return res;
394 } 377 }
395 EXPORT_SYMBOL_GPL(snd_hdac_stream_assign); 378 EXPORT_SYMBOL_GPL(snd_hdac_stream_assign);
396 379
397 /** 380 /**
398 * snd_hdac_stream_release_locked - release th 381 * snd_hdac_stream_release_locked - release the assigned stream
399 * @azx_dev: HD-audio core stream to release 382 * @azx_dev: HD-audio core stream to release
400 * 383 *
401 * Release the stream that has been assigned b 384 * Release the stream that has been assigned by snd_hdac_stream_assign().
402 * The bus->reg_lock needs to be taken at a hi 385 * The bus->reg_lock needs to be taken at a higher level
403 */ 386 */
404 void snd_hdac_stream_release_locked(struct hda 387 void snd_hdac_stream_release_locked(struct hdac_stream *azx_dev)
405 { 388 {
406 azx_dev->opened = 0; 389 azx_dev->opened = 0;
407 azx_dev->running = 0; 390 azx_dev->running = 0;
408 azx_dev->substream = NULL; 391 azx_dev->substream = NULL;
409 } 392 }
410 EXPORT_SYMBOL_GPL(snd_hdac_stream_release_lock 393 EXPORT_SYMBOL_GPL(snd_hdac_stream_release_locked);
411 394
412 /** 395 /**
413 * snd_hdac_stream_release - release the assig 396 * snd_hdac_stream_release - release the assigned stream
414 * @azx_dev: HD-audio core stream to release 397 * @azx_dev: HD-audio core stream to release
415 * 398 *
416 * Release the stream that has been assigned b 399 * Release the stream that has been assigned by snd_hdac_stream_assign().
417 */ 400 */
418 void snd_hdac_stream_release(struct hdac_strea 401 void snd_hdac_stream_release(struct hdac_stream *azx_dev)
419 { 402 {
420 struct hdac_bus *bus = azx_dev->bus; 403 struct hdac_bus *bus = azx_dev->bus;
421 404
422 spin_lock_irq(&bus->reg_lock); 405 spin_lock_irq(&bus->reg_lock);
423 snd_hdac_stream_release_locked(azx_dev 406 snd_hdac_stream_release_locked(azx_dev);
424 spin_unlock_irq(&bus->reg_lock); 407 spin_unlock_irq(&bus->reg_lock);
425 } 408 }
426 EXPORT_SYMBOL_GPL(snd_hdac_stream_release); 409 EXPORT_SYMBOL_GPL(snd_hdac_stream_release);
427 410
428 /** 411 /**
429 * snd_hdac_get_stream - return hdac_stream ba 412 * snd_hdac_get_stream - return hdac_stream based on stream_tag and
430 * direction 413 * direction
431 * 414 *
432 * @bus: HD-audio core bus 415 * @bus: HD-audio core bus
433 * @dir: direction for the stream to be found 416 * @dir: direction for the stream to be found
434 * @stream_tag: stream tag for stream to be fo 417 * @stream_tag: stream tag for stream to be found
435 */ 418 */
436 struct hdac_stream *snd_hdac_get_stream(struct 419 struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
437 int di 420 int dir, int stream_tag)
438 { 421 {
439 struct hdac_stream *s; 422 struct hdac_stream *s;
440 423
441 list_for_each_entry(s, &bus->stream_li 424 list_for_each_entry(s, &bus->stream_list, list) {
442 if (s->direction == dir && s-> 425 if (s->direction == dir && s->stream_tag == stream_tag)
443 return s; 426 return s;
444 } 427 }
445 428
446 return NULL; 429 return NULL;
447 } 430 }
448 EXPORT_SYMBOL_GPL(snd_hdac_get_stream); 431 EXPORT_SYMBOL_GPL(snd_hdac_get_stream);
449 432
450 /* 433 /*
451 * set up a BDL entry 434 * set up a BDL entry
452 */ 435 */
453 static int setup_bdle(struct hdac_bus *bus, 436 static int setup_bdle(struct hdac_bus *bus,
454 struct snd_dma_buffer *d 437 struct snd_dma_buffer *dmab,
455 struct hdac_stream *azx_ 438 struct hdac_stream *azx_dev, __le32 **bdlp,
456 int ofs, int size, int w 439 int ofs, int size, int with_ioc)
457 { 440 {
458 __le32 *bdl = *bdlp; 441 __le32 *bdl = *bdlp;
459 442
460 while (size > 0) { 443 while (size > 0) {
461 dma_addr_t addr; 444 dma_addr_t addr;
462 int chunk; 445 int chunk;
463 446
464 if (azx_dev->frags >= AZX_MAX_ 447 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
465 return -EINVAL; 448 return -EINVAL;
466 449
467 addr = snd_sgbuf_get_addr(dmab 450 addr = snd_sgbuf_get_addr(dmab, ofs);
468 /* program the address field o 451 /* program the address field of the BDL entry */
469 bdl[0] = cpu_to_le32((u32)addr 452 bdl[0] = cpu_to_le32((u32)addr);
470 bdl[1] = cpu_to_le32(upper_32_ 453 bdl[1] = cpu_to_le32(upper_32_bits(addr));
471 /* program the size field of t 454 /* program the size field of the BDL entry */
472 chunk = snd_sgbuf_get_chunk_si 455 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
473 /* one BDLE cannot cross 4K bo 456 /* one BDLE cannot cross 4K boundary on CTHDA chips */
474 if (bus->align_bdle_4k) { 457 if (bus->align_bdle_4k) {
475 u32 remain = 0x1000 - 458 u32 remain = 0x1000 - (ofs & 0xfff);
476 459
477 if (chunk > remain) 460 if (chunk > remain)
478 chunk = remain 461 chunk = remain;
479 } 462 }
480 bdl[2] = cpu_to_le32(chunk); 463 bdl[2] = cpu_to_le32(chunk);
481 /* program the IOC to enable i 464 /* program the IOC to enable interrupt
482 * only when the whole fragmen 465 * only when the whole fragment is processed
483 */ 466 */
484 size -= chunk; 467 size -= chunk;
485 bdl[3] = (size || !with_ioc) ? 468 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
486 bdl += 4; 469 bdl += 4;
487 azx_dev->frags++; 470 azx_dev->frags++;
488 ofs += chunk; 471 ofs += chunk;
489 } 472 }
490 *bdlp = bdl; 473 *bdlp = bdl;
491 return ofs; 474 return ofs;
492 } 475 }
493 476
494 /** 477 /**
495 * snd_hdac_stream_setup_periods - set up BDL 478 * snd_hdac_stream_setup_periods - set up BDL entries
496 * @azx_dev: HD-audio core stream to set up 479 * @azx_dev: HD-audio core stream to set up
497 * 480 *
498 * Set up the buffer descriptor table of the g 481 * Set up the buffer descriptor table of the given stream based on the
499 * period and buffer sizes of the assigned PCM 482 * period and buffer sizes of the assigned PCM substream.
500 */ 483 */
501 int snd_hdac_stream_setup_periods(struct hdac_ 484 int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev)
502 { 485 {
503 struct hdac_bus *bus = azx_dev->bus; 486 struct hdac_bus *bus = azx_dev->bus;
504 struct snd_pcm_substream *substream = 487 struct snd_pcm_substream *substream = azx_dev->substream;
505 struct snd_compr_stream *cstream = azx 488 struct snd_compr_stream *cstream = azx_dev->cstream;
506 struct snd_pcm_runtime *runtime = NULL 489 struct snd_pcm_runtime *runtime = NULL;
507 struct snd_dma_buffer *dmab; 490 struct snd_dma_buffer *dmab;
508 __le32 *bdl; 491 __le32 *bdl;
509 int i, ofs, periods, period_bytes; 492 int i, ofs, periods, period_bytes;
510 int pos_adj, pos_align; 493 int pos_adj, pos_align;
511 494
512 if (substream) { 495 if (substream) {
513 runtime = substream->runtime; 496 runtime = substream->runtime;
514 dmab = snd_pcm_get_dma_buf(sub 497 dmab = snd_pcm_get_dma_buf(substream);
515 } else if (cstream) { 498 } else if (cstream) {
516 dmab = snd_pcm_get_dma_buf(cst 499 dmab = snd_pcm_get_dma_buf(cstream);
517 } else { 500 } else {
518 WARN(1, "No substream or cstre 501 WARN(1, "No substream or cstream assigned\n");
519 return -EINVAL; 502 return -EINVAL;
520 } 503 }
521 504
522 /* reset BDL address */ 505 /* reset BDL address */
523 snd_hdac_stream_writel(azx_dev, SD_BDL 506 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
524 snd_hdac_stream_writel(azx_dev, SD_BDL 507 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
525 508
526 period_bytes = azx_dev->period_bytes; 509 period_bytes = azx_dev->period_bytes;
527 periods = azx_dev->bufsize / period_by 510 periods = azx_dev->bufsize / period_bytes;
528 511
529 /* program the initial BDL entries */ 512 /* program the initial BDL entries */
530 bdl = (__le32 *)azx_dev->bdl.area; 513 bdl = (__le32 *)azx_dev->bdl.area;
531 ofs = 0; 514 ofs = 0;
532 azx_dev->frags = 0; 515 azx_dev->frags = 0;
533 516
534 pos_adj = bus->bdl_pos_adj; 517 pos_adj = bus->bdl_pos_adj;
535 if (runtime && !azx_dev->no_period_wak 518 if (runtime && !azx_dev->no_period_wakeup && pos_adj > 0) {
536 pos_align = pos_adj; 519 pos_align = pos_adj;
537 pos_adj = DIV_ROUND_UP(pos_adj 520 pos_adj = DIV_ROUND_UP(pos_adj * runtime->rate, 48000);
538 if (!pos_adj) 521 if (!pos_adj)
539 pos_adj = pos_align; 522 pos_adj = pos_align;
540 else 523 else
541 pos_adj = roundup(pos_ 524 pos_adj = roundup(pos_adj, pos_align);
542 pos_adj = frames_to_bytes(runt 525 pos_adj = frames_to_bytes(runtime, pos_adj);
543 if (pos_adj >= period_bytes) { 526 if (pos_adj >= period_bytes) {
544 dev_warn(bus->dev, "To 527 dev_warn(bus->dev, "Too big adjustment %d\n",
545 pos_adj); 528 pos_adj);
546 pos_adj = 0; 529 pos_adj = 0;
547 } else { 530 } else {
548 ofs = setup_bdle(bus, 531 ofs = setup_bdle(bus, dmab, azx_dev,
549 &bdl, 532 &bdl, ofs, pos_adj, true);
550 if (ofs < 0) 533 if (ofs < 0)
551 goto error; 534 goto error;
552 } 535 }
553 } else 536 } else
554 pos_adj = 0; 537 pos_adj = 0;
555 538
556 for (i = 0; i < periods; i++) { 539 for (i = 0; i < periods; i++) {
557 if (i == periods - 1 && pos_ad 540 if (i == periods - 1 && pos_adj)
558 ofs = setup_bdle(bus, 541 ofs = setup_bdle(bus, dmab, azx_dev,
559 &bdl, 542 &bdl, ofs, period_bytes - pos_adj, 0);
560 else 543 else
561 ofs = setup_bdle(bus, 544 ofs = setup_bdle(bus, dmab, azx_dev,
562 &bdl, 545 &bdl, ofs, period_bytes,
563 !azx_ 546 !azx_dev->no_period_wakeup);
564 if (ofs < 0) 547 if (ofs < 0)
565 goto error; 548 goto error;
566 } 549 }
567 return 0; 550 return 0;
568 551
569 error: 552 error:
570 dev_dbg(bus->dev, "Too many BDL entrie !! 553 dev_err(bus->dev, "Too many BDL entries: buffer=%d, period=%d\n",
571 azx_dev->bufsize, period_bytes 554 azx_dev->bufsize, period_bytes);
572 return -EINVAL; 555 return -EINVAL;
573 } 556 }
574 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_period 557 EXPORT_SYMBOL_GPL(snd_hdac_stream_setup_periods);
575 558
576 /** 559 /**
577 * snd_hdac_stream_set_params - set stream par 560 * snd_hdac_stream_set_params - set stream parameters
578 * @azx_dev: HD-audio core stream for which pa 561 * @azx_dev: HD-audio core stream for which parameters are to be set
579 * @format_val: format value parameter 562 * @format_val: format value parameter
580 * 563 *
581 * Setup the HD-audio core stream parameters f 564 * Setup the HD-audio core stream parameters from substream of the stream
582 * and passed format value 565 * and passed format value
583 */ 566 */
584 int snd_hdac_stream_set_params(struct hdac_str 567 int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
585 unsigned int 568 unsigned int format_val)
586 { 569 {
587 struct snd_pcm_substream *substream = 570 struct snd_pcm_substream *substream = azx_dev->substream;
588 struct snd_compr_stream *cstream = azx 571 struct snd_compr_stream *cstream = azx_dev->cstream;
589 unsigned int bufsize, period_bytes; 572 unsigned int bufsize, period_bytes;
590 unsigned int no_period_wakeup; 573 unsigned int no_period_wakeup;
591 int err; 574 int err;
592 575
593 if (substream) { 576 if (substream) {
594 bufsize = snd_pcm_lib_buffer_b 577 bufsize = snd_pcm_lib_buffer_bytes(substream);
595 period_bytes = snd_pcm_lib_per 578 period_bytes = snd_pcm_lib_period_bytes(substream);
596 no_period_wakeup = substream-> 579 no_period_wakeup = substream->runtime->no_period_wakeup;
597 } else if (cstream) { 580 } else if (cstream) {
598 bufsize = cstream->runtime->bu 581 bufsize = cstream->runtime->buffer_size;
599 period_bytes = cstream->runtim 582 period_bytes = cstream->runtime->fragment_size;
600 no_period_wakeup = 0; 583 no_period_wakeup = 0;
601 } else { 584 } else {
602 return -EINVAL; 585 return -EINVAL;
603 } 586 }
604 587
605 if (bufsize != azx_dev->bufsize || 588 if (bufsize != azx_dev->bufsize ||
606 period_bytes != azx_dev->period_by 589 period_bytes != azx_dev->period_bytes ||
607 format_val != azx_dev->format_val 590 format_val != azx_dev->format_val ||
608 no_period_wakeup != azx_dev->no_pe 591 no_period_wakeup != azx_dev->no_period_wakeup) {
609 azx_dev->bufsize = bufsize; 592 azx_dev->bufsize = bufsize;
610 azx_dev->period_bytes = period 593 azx_dev->period_bytes = period_bytes;
611 azx_dev->format_val = format_v 594 azx_dev->format_val = format_val;
612 azx_dev->no_period_wakeup = no 595 azx_dev->no_period_wakeup = no_period_wakeup;
613 err = snd_hdac_stream_setup_pe 596 err = snd_hdac_stream_setup_periods(azx_dev);
614 if (err < 0) 597 if (err < 0)
615 return err; 598 return err;
616 } 599 }
617 return 0; 600 return 0;
618 } 601 }
619 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params); 602 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_params);
620 603
621 static u64 azx_cc_read(const struct cyclecount 604 static u64 azx_cc_read(const struct cyclecounter *cc)
622 { 605 {
623 struct hdac_stream *azx_dev = containe 606 struct hdac_stream *azx_dev = container_of(cc, struct hdac_stream, cc);
624 607
625 return snd_hdac_chip_readl(azx_dev->bu 608 return snd_hdac_chip_readl(azx_dev->bus, WALLCLK);
626 } 609 }
627 610
628 static void azx_timecounter_init(struct hdac_s 611 static void azx_timecounter_init(struct hdac_stream *azx_dev,
629 bool force, u 612 bool force, u64 last)
630 { 613 {
631 struct timecounter *tc = &azx_dev->tc; 614 struct timecounter *tc = &azx_dev->tc;
632 struct cyclecounter *cc = &azx_dev->cc 615 struct cyclecounter *cc = &azx_dev->cc;
633 u64 nsec; 616 u64 nsec;
634 617
635 cc->read = azx_cc_read; 618 cc->read = azx_cc_read;
636 cc->mask = CLOCKSOURCE_MASK(32); 619 cc->mask = CLOCKSOURCE_MASK(32);
637 620
638 /* 621 /*
639 * Calculate the optimal mult/shift va 622 * Calculate the optimal mult/shift values. The counter wraps
640 * around after ~178.9 seconds. 623 * around after ~178.9 seconds.
641 */ 624 */
642 clocks_calc_mult_shift(&cc->mult, &cc- 625 clocks_calc_mult_shift(&cc->mult, &cc->shift, 24000000,
643 NSEC_PER_SEC, 1 626 NSEC_PER_SEC, 178);
644 627
645 nsec = 0; /* audio time is elapsed tim 628 nsec = 0; /* audio time is elapsed time since trigger */
646 timecounter_init(tc, cc, nsec); 629 timecounter_init(tc, cc, nsec);
647 if (force) { 630 if (force) {
648 /* 631 /*
649 * force timecounter to use pr 632 * force timecounter to use predefined value,
650 * used for synchronized start 633 * used for synchronized starts
651 */ 634 */
652 tc->cycle_last = last; 635 tc->cycle_last = last;
653 } 636 }
654 } 637 }
655 638
656 /** 639 /**
657 * snd_hdac_stream_timecounter_init - initiali 640 * snd_hdac_stream_timecounter_init - initialize time counter
658 * @azx_dev: HD-audio core stream (master stre 641 * @azx_dev: HD-audio core stream (master stream)
659 * @streams: bit flags of streams to set up 642 * @streams: bit flags of streams to set up
660 * @start: true for PCM trigger start, false f <<
661 * 643 *
662 * Initializes the time counter of streams mar 644 * Initializes the time counter of streams marked by the bit flags (each
663 * bit corresponds to the stream index). 645 * bit corresponds to the stream index).
664 * The trigger timestamp of PCM substream assi 646 * The trigger timestamp of PCM substream assigned to the given stream is
665 * updated accordingly, too. 647 * updated accordingly, too.
666 */ 648 */
667 void snd_hdac_stream_timecounter_init(struct h 649 void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
668 unsigned !! 650 unsigned int streams)
669 { 651 {
670 struct hdac_bus *bus = azx_dev->bus; 652 struct hdac_bus *bus = azx_dev->bus;
671 struct snd_pcm_runtime *runtime = azx_ 653 struct snd_pcm_runtime *runtime = azx_dev->substream->runtime;
672 struct hdac_stream *s; 654 struct hdac_stream *s;
673 bool inited = false; 655 bool inited = false;
674 u64 cycle_last = 0; 656 u64 cycle_last = 0;
675 !! 657 int i = 0;
676 if (!start) <<
677 goto skip; <<
678 658
679 list_for_each_entry(s, &bus->stream_li 659 list_for_each_entry(s, &bus->stream_list, list) {
680 if ((streams & (1 << s->index) !! 660 if (streams & (1 << i)) {
681 azx_timecounter_init(s 661 azx_timecounter_init(s, inited, cycle_last);
682 if (!inited) { 662 if (!inited) {
683 inited = true; 663 inited = true;
684 cycle_last = s 664 cycle_last = s->tc.cycle_last;
685 } 665 }
686 } 666 }
>> 667 i++;
687 } 668 }
688 669
689 skip: <<
690 snd_pcm_gettime(runtime, &runtime->tri 670 snd_pcm_gettime(runtime, &runtime->trigger_tstamp);
691 runtime->trigger_tstamp_latched = true 671 runtime->trigger_tstamp_latched = true;
692 } 672 }
693 EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_ 673 EXPORT_SYMBOL_GPL(snd_hdac_stream_timecounter_init);
694 674
695 /** 675 /**
696 * snd_hdac_stream_sync_trigger - turn on/off 676 * snd_hdac_stream_sync_trigger - turn on/off stream sync register
697 * @azx_dev: HD-audio core stream (master stre 677 * @azx_dev: HD-audio core stream (master stream)
698 * @set: true = set, false = clear 678 * @set: true = set, false = clear
699 * @streams: bit flags of streams to sync 679 * @streams: bit flags of streams to sync
700 * @reg: the stream sync register address 680 * @reg: the stream sync register address
701 */ 681 */
702 void snd_hdac_stream_sync_trigger(struct hdac_ 682 void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
703 unsigned int 683 unsigned int streams, unsigned int reg)
704 { 684 {
705 struct hdac_bus *bus = azx_dev->bus; 685 struct hdac_bus *bus = azx_dev->bus;
706 unsigned int val; 686 unsigned int val;
707 687
708 if (!reg) 688 if (!reg)
709 reg = AZX_REG_SSYNC; 689 reg = AZX_REG_SSYNC;
710 val = _snd_hdac_chip_readl(bus, reg); 690 val = _snd_hdac_chip_readl(bus, reg);
711 if (set) 691 if (set)
712 val |= streams; 692 val |= streams;
713 else 693 else
714 val &= ~streams; 694 val &= ~streams;
715 _snd_hdac_chip_writel(bus, reg, val); 695 _snd_hdac_chip_writel(bus, reg, val);
716 } 696 }
717 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger 697 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync_trigger);
718 698
719 /** 699 /**
720 * snd_hdac_stream_sync - sync with start/stop 700 * snd_hdac_stream_sync - sync with start/stop trigger operation
721 * @azx_dev: HD-audio core stream (master stre 701 * @azx_dev: HD-audio core stream (master stream)
722 * @start: true = start, false = stop 702 * @start: true = start, false = stop
723 * @streams: bit flags of streams to sync 703 * @streams: bit flags of streams to sync
724 * 704 *
725 * For @start = true, wait until all FIFOs get 705 * For @start = true, wait until all FIFOs get ready.
726 * For @start = false, wait until all RUN bits 706 * For @start = false, wait until all RUN bits are cleared.
727 */ 707 */
728 void snd_hdac_stream_sync(struct hdac_stream * 708 void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
729 unsigned int streams 709 unsigned int streams)
730 { 710 {
731 struct hdac_bus *bus = azx_dev->bus; 711 struct hdac_bus *bus = azx_dev->bus;
732 int nwait, timeout; !! 712 int i, nwait, timeout;
733 struct hdac_stream *s; 713 struct hdac_stream *s;
734 714
735 for (timeout = 5000; timeout; timeout- 715 for (timeout = 5000; timeout; timeout--) {
736 nwait = 0; 716 nwait = 0;
>> 717 i = 0;
737 list_for_each_entry(s, &bus->s 718 list_for_each_entry(s, &bus->stream_list, list) {
738 if (!(streams & (1 << !! 719 if (!(streams & (1 << i++)))
739 continue; 720 continue;
740 721
741 if (start) { 722 if (start) {
742 /* check FIFO 723 /* check FIFO gets ready */
743 if (!(snd_hdac 724 if (!(snd_hdac_stream_readb(s, SD_STS) &
744 SD_STS_F 725 SD_STS_FIFO_READY))
745 nwait+ 726 nwait++;
746 } else { 727 } else {
747 /* check RUN b 728 /* check RUN bit is cleared */
748 if (snd_hdac_s 729 if (snd_hdac_stream_readb(s, SD_CTL) &
749 SD_CTL_DMA 730 SD_CTL_DMA_START) {
750 nwait+ 731 nwait++;
751 /* 732 /*
752 * Per 733 * Perform stream reset if DMA RUN
753 * bit 734 * bit not cleared within given timeout
754 */ 735 */
755 if (ti 736 if (timeout == 1)
756 737 snd_hdac_stream_reset(s);
757 } 738 }
758 } 739 }
759 } 740 }
760 if (!nwait) 741 if (!nwait)
761 break; 742 break;
762 cpu_relax(); 743 cpu_relax();
763 } 744 }
764 } 745 }
765 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync); 746 EXPORT_SYMBOL_GPL(snd_hdac_stream_sync);
766 747
767 /** 748 /**
768 * snd_hdac_stream_spbcap_enable - enable SPIB 749 * snd_hdac_stream_spbcap_enable - enable SPIB for a stream
769 * @bus: HD-audio core bus 750 * @bus: HD-audio core bus
770 * @enable: flag to enable/disable SPIB 751 * @enable: flag to enable/disable SPIB
771 * @index: stream index for which SPIB need to 752 * @index: stream index for which SPIB need to be enabled
772 */ 753 */
773 void snd_hdac_stream_spbcap_enable(struct hdac 754 void snd_hdac_stream_spbcap_enable(struct hdac_bus *bus,
774 bool enable 755 bool enable, int index)
775 { 756 {
776 u32 mask = 0; 757 u32 mask = 0;
777 758
778 if (!bus->spbcap) { 759 if (!bus->spbcap) {
779 dev_err(bus->dev, "Address of 760 dev_err(bus->dev, "Address of SPB capability is NULL\n");
780 return; 761 return;
781 } 762 }
782 763
783 mask |= (1 << index); 764 mask |= (1 << index);
784 765
785 if (enable) 766 if (enable)
786 snd_hdac_updatel(bus->spbcap, 767 snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, mask);
787 else 768 else
788 snd_hdac_updatel(bus->spbcap, 769 snd_hdac_updatel(bus->spbcap, AZX_REG_SPB_SPBFCCTL, mask, 0);
789 } 770 }
790 EXPORT_SYMBOL_GPL(snd_hdac_stream_spbcap_enabl 771 EXPORT_SYMBOL_GPL(snd_hdac_stream_spbcap_enable);
791 772
792 /** 773 /**
793 * snd_hdac_stream_set_spib - sets the spib va 774 * snd_hdac_stream_set_spib - sets the spib value of a stream
794 * @bus: HD-audio core bus 775 * @bus: HD-audio core bus
795 * @azx_dev: hdac_stream 776 * @azx_dev: hdac_stream
796 * @value: spib value to set 777 * @value: spib value to set
797 */ 778 */
798 int snd_hdac_stream_set_spib(struct hdac_bus * 779 int snd_hdac_stream_set_spib(struct hdac_bus *bus,
799 struct hdac_strea 780 struct hdac_stream *azx_dev, u32 value)
800 { 781 {
801 if (!bus->spbcap) { 782 if (!bus->spbcap) {
802 dev_err(bus->dev, "Address of 783 dev_err(bus->dev, "Address of SPB capability is NULL\n");
803 return -EINVAL; 784 return -EINVAL;
804 } 785 }
805 786
806 writel(value, azx_dev->spib_addr); 787 writel(value, azx_dev->spib_addr);
807 788
808 return 0; 789 return 0;
809 } 790 }
810 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_spib); 791 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_spib);
811 792
812 /** 793 /**
813 * snd_hdac_stream_get_spbmaxfifo - gets the s 794 * snd_hdac_stream_get_spbmaxfifo - gets the spib value of a stream
814 * @bus: HD-audio core bus 795 * @bus: HD-audio core bus
815 * @azx_dev: hdac_stream 796 * @azx_dev: hdac_stream
816 * 797 *
817 * Return maxfifo for the stream 798 * Return maxfifo for the stream
818 */ 799 */
819 int snd_hdac_stream_get_spbmaxfifo(struct hdac 800 int snd_hdac_stream_get_spbmaxfifo(struct hdac_bus *bus,
820 struct hdac 801 struct hdac_stream *azx_dev)
821 { 802 {
822 if (!bus->spbcap) { 803 if (!bus->spbcap) {
823 dev_err(bus->dev, "Address of 804 dev_err(bus->dev, "Address of SPB capability is NULL\n");
824 return -EINVAL; 805 return -EINVAL;
825 } 806 }
826 807
827 return readl(azx_dev->fifo_addr); 808 return readl(azx_dev->fifo_addr);
828 } 809 }
829 EXPORT_SYMBOL_GPL(snd_hdac_stream_get_spbmaxfi 810 EXPORT_SYMBOL_GPL(snd_hdac_stream_get_spbmaxfifo);
830 811
831 /** 812 /**
832 * snd_hdac_stream_drsm_enable - enable DMA re 813 * snd_hdac_stream_drsm_enable - enable DMA resume for a stream
833 * @bus: HD-audio core bus 814 * @bus: HD-audio core bus
834 * @enable: flag to enable/disable DRSM 815 * @enable: flag to enable/disable DRSM
835 * @index: stream index for which DRSM need to 816 * @index: stream index for which DRSM need to be enabled
836 */ 817 */
837 void snd_hdac_stream_drsm_enable(struct hdac_b 818 void snd_hdac_stream_drsm_enable(struct hdac_bus *bus,
838 bool enable, 819 bool enable, int index)
839 { 820 {
840 u32 mask = 0; 821 u32 mask = 0;
841 822
842 if (!bus->drsmcap) { 823 if (!bus->drsmcap) {
843 dev_err(bus->dev, "Address of 824 dev_err(bus->dev, "Address of DRSM capability is NULL\n");
844 return; 825 return;
845 } 826 }
846 827
847 mask |= (1 << index); 828 mask |= (1 << index);
848 829
849 if (enable) 830 if (enable)
850 snd_hdac_updatel(bus->drsmcap, 831 snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, mask);
851 else 832 else
852 snd_hdac_updatel(bus->drsmcap, 833 snd_hdac_updatel(bus->drsmcap, AZX_REG_DRSM_CTL, mask, 0);
853 } 834 }
854 EXPORT_SYMBOL_GPL(snd_hdac_stream_drsm_enable) 835 EXPORT_SYMBOL_GPL(snd_hdac_stream_drsm_enable);
855 836
856 /* 837 /*
857 * snd_hdac_stream_wait_drsm - wait for HW to 838 * snd_hdac_stream_wait_drsm - wait for HW to clear RSM for a stream
858 * @azx_dev: HD-audio core stream to await RSM 839 * @azx_dev: HD-audio core stream to await RSM for
859 * 840 *
860 * Returns 0 on success and -ETIMEDOUT upon a 841 * Returns 0 on success and -ETIMEDOUT upon a timeout.
861 */ 842 */
862 int snd_hdac_stream_wait_drsm(struct hdac_stre 843 int snd_hdac_stream_wait_drsm(struct hdac_stream *azx_dev)
863 { 844 {
864 struct hdac_bus *bus = azx_dev->bus; 845 struct hdac_bus *bus = azx_dev->bus;
865 u32 mask, reg; 846 u32 mask, reg;
866 int ret; 847 int ret;
867 848
868 mask = 1 << azx_dev->index; 849 mask = 1 << azx_dev->index;
869 850
870 ret = read_poll_timeout(snd_hdac_reg_r 851 ret = read_poll_timeout(snd_hdac_reg_readl, reg, !(reg & mask), 250, 2000, false, bus,
871 bus->drsmcap + 852 bus->drsmcap + AZX_REG_DRSM_CTL);
872 if (ret) 853 if (ret)
873 dev_dbg(bus->dev, "polling RSM 854 dev_dbg(bus->dev, "polling RSM 0x%08x failed: %d\n", mask, ret);
874 return ret; 855 return ret;
875 } 856 }
876 EXPORT_SYMBOL_GPL(snd_hdac_stream_wait_drsm); 857 EXPORT_SYMBOL_GPL(snd_hdac_stream_wait_drsm);
877 858
878 /** 859 /**
879 * snd_hdac_stream_set_dpibr - sets the dpibr 860 * snd_hdac_stream_set_dpibr - sets the dpibr value of a stream
880 * @bus: HD-audio core bus 861 * @bus: HD-audio core bus
881 * @azx_dev: hdac_stream 862 * @azx_dev: hdac_stream
882 * @value: dpib value to set 863 * @value: dpib value to set
883 */ 864 */
884 int snd_hdac_stream_set_dpibr(struct hdac_bus 865 int snd_hdac_stream_set_dpibr(struct hdac_bus *bus,
885 struct hdac_stre 866 struct hdac_stream *azx_dev, u32 value)
886 { 867 {
887 if (!bus->drsmcap) { 868 if (!bus->drsmcap) {
888 dev_err(bus->dev, "Address of 869 dev_err(bus->dev, "Address of DRSM capability is NULL\n");
889 return -EINVAL; 870 return -EINVAL;
890 } 871 }
891 872
892 writel(value, azx_dev->dpibr_addr); 873 writel(value, azx_dev->dpibr_addr);
893 874
894 return 0; 875 return 0;
895 } 876 }
896 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_dpibr); 877 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_dpibr);
897 878
898 /** 879 /**
899 * snd_hdac_stream_set_lpib - sets the lpib va 880 * snd_hdac_stream_set_lpib - sets the lpib value of a stream
900 * @azx_dev: hdac_stream 881 * @azx_dev: hdac_stream
901 * @value: lpib value to set 882 * @value: lpib value to set
902 */ 883 */
903 int snd_hdac_stream_set_lpib(struct hdac_strea 884 int snd_hdac_stream_set_lpib(struct hdac_stream *azx_dev, u32 value)
904 { 885 {
905 snd_hdac_stream_writel(azx_dev, SD_LPI 886 snd_hdac_stream_writel(azx_dev, SD_LPIB, value);
906 887
907 return 0; 888 return 0;
908 } 889 }
909 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_lpib); 890 EXPORT_SYMBOL_GPL(snd_hdac_stream_set_lpib);
910 891
911 #ifdef CONFIG_SND_HDA_DSP_LOADER 892 #ifdef CONFIG_SND_HDA_DSP_LOADER
912 /** 893 /**
913 * snd_hdac_dsp_prepare - prepare for DSP load 894 * snd_hdac_dsp_prepare - prepare for DSP loading
914 * @azx_dev: HD-audio core stream used for DSP 895 * @azx_dev: HD-audio core stream used for DSP loading
915 * @format: HD-audio stream format 896 * @format: HD-audio stream format
916 * @byte_size: data chunk byte size 897 * @byte_size: data chunk byte size
917 * @bufp: allocated buffer 898 * @bufp: allocated buffer
918 * 899 *
919 * Allocate the buffer for the given size and 900 * Allocate the buffer for the given size and set up the given stream for
920 * DSP loading. Returns the stream tag (>= 0) 901 * DSP loading. Returns the stream tag (>= 0), or a negative error code.
921 */ 902 */
922 int snd_hdac_dsp_prepare(struct hdac_stream *a 903 int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
923 unsigned int byte_siz 904 unsigned int byte_size, struct snd_dma_buffer *bufp)
924 { 905 {
925 struct hdac_bus *bus = azx_dev->bus; 906 struct hdac_bus *bus = azx_dev->bus;
926 __le32 *bdl; 907 __le32 *bdl;
927 int err; 908 int err;
928 909
929 snd_hdac_dsp_lock(azx_dev); 910 snd_hdac_dsp_lock(azx_dev);
930 spin_lock_irq(&bus->reg_lock); 911 spin_lock_irq(&bus->reg_lock);
931 if (azx_dev->running || azx_dev->locke 912 if (azx_dev->running || azx_dev->locked) {
932 spin_unlock_irq(&bus->reg_lock 913 spin_unlock_irq(&bus->reg_lock);
933 err = -EBUSY; 914 err = -EBUSY;
934 goto unlock; 915 goto unlock;
935 } 916 }
936 azx_dev->locked = true; 917 azx_dev->locked = true;
937 spin_unlock_irq(&bus->reg_lock); 918 spin_unlock_irq(&bus->reg_lock);
938 919
939 err = snd_dma_alloc_pages(SNDRV_DMA_TY 920 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG, bus->dev,
940 byte_size, b 921 byte_size, bufp);
941 if (err < 0) 922 if (err < 0)
942 goto err_alloc; 923 goto err_alloc;
943 924
944 azx_dev->substream = NULL; 925 azx_dev->substream = NULL;
945 azx_dev->bufsize = byte_size; 926 azx_dev->bufsize = byte_size;
946 azx_dev->period_bytes = byte_size; 927 azx_dev->period_bytes = byte_size;
947 azx_dev->format_val = format; 928 azx_dev->format_val = format;
948 929
949 snd_hdac_stream_reset(azx_dev); 930 snd_hdac_stream_reset(azx_dev);
950 931
951 /* reset BDL address */ 932 /* reset BDL address */
952 snd_hdac_stream_writel(azx_dev, SD_BDL 933 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
953 snd_hdac_stream_writel(azx_dev, SD_BDL 934 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
954 935
955 azx_dev->frags = 0; 936 azx_dev->frags = 0;
956 bdl = (__le32 *)azx_dev->bdl.area; 937 bdl = (__le32 *)azx_dev->bdl.area;
957 err = setup_bdle(bus, bufp, azx_dev, & 938 err = setup_bdle(bus, bufp, azx_dev, &bdl, 0, byte_size, 0);
958 if (err < 0) 939 if (err < 0)
959 goto error; 940 goto error;
960 941
961 snd_hdac_stream_setup(azx_dev, true); !! 942 snd_hdac_stream_setup(azx_dev);
962 snd_hdac_dsp_unlock(azx_dev); 943 snd_hdac_dsp_unlock(azx_dev);
963 return azx_dev->stream_tag; 944 return azx_dev->stream_tag;
964 945
965 error: 946 error:
966 snd_dma_free_pages(bufp); 947 snd_dma_free_pages(bufp);
967 err_alloc: 948 err_alloc:
968 spin_lock_irq(&bus->reg_lock); 949 spin_lock_irq(&bus->reg_lock);
969 azx_dev->locked = false; 950 azx_dev->locked = false;
970 spin_unlock_irq(&bus->reg_lock); 951 spin_unlock_irq(&bus->reg_lock);
971 unlock: 952 unlock:
972 snd_hdac_dsp_unlock(azx_dev); 953 snd_hdac_dsp_unlock(azx_dev);
973 return err; 954 return err;
974 } 955 }
975 EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare); 956 EXPORT_SYMBOL_GPL(snd_hdac_dsp_prepare);
976 957
977 /** 958 /**
978 * snd_hdac_dsp_trigger - start / stop DSP loa 959 * snd_hdac_dsp_trigger - start / stop DSP loading
979 * @azx_dev: HD-audio core stream used for DSP 960 * @azx_dev: HD-audio core stream used for DSP loading
980 * @start: trigger start or stop 961 * @start: trigger start or stop
981 */ 962 */
982 void snd_hdac_dsp_trigger(struct hdac_stream * 963 void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
983 { 964 {
984 if (start) 965 if (start)
985 snd_hdac_stream_start(azx_dev) 966 snd_hdac_stream_start(azx_dev);
986 else 967 else
987 snd_hdac_stream_stop(azx_dev); 968 snd_hdac_stream_stop(azx_dev);
988 } 969 }
989 EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger); 970 EXPORT_SYMBOL_GPL(snd_hdac_dsp_trigger);
990 971
991 /** 972 /**
992 * snd_hdac_dsp_cleanup - clean up the stream 973 * snd_hdac_dsp_cleanup - clean up the stream from DSP loading to normal
993 * @azx_dev: HD-audio core stream used for DSP 974 * @azx_dev: HD-audio core stream used for DSP loading
994 * @dmab: buffer used by DSP loading 975 * @dmab: buffer used by DSP loading
995 */ 976 */
996 void snd_hdac_dsp_cleanup(struct hdac_stream * 977 void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
997 struct snd_dma_buffe 978 struct snd_dma_buffer *dmab)
998 { 979 {
999 struct hdac_bus *bus = azx_dev->bus; 980 struct hdac_bus *bus = azx_dev->bus;
1000 981
1001 if (!dmab->area || !azx_dev->locked) 982 if (!dmab->area || !azx_dev->locked)
1002 return; 983 return;
1003 984
1004 snd_hdac_dsp_lock(azx_dev); 985 snd_hdac_dsp_lock(azx_dev);
1005 /* reset BDL address */ 986 /* reset BDL address */
1006 snd_hdac_stream_writel(azx_dev, SD_BD 987 snd_hdac_stream_writel(azx_dev, SD_BDLPL, 0);
1007 snd_hdac_stream_writel(azx_dev, SD_BD 988 snd_hdac_stream_writel(azx_dev, SD_BDLPU, 0);
1008 snd_hdac_stream_writel(azx_dev, SD_CT 989 snd_hdac_stream_writel(azx_dev, SD_CTL, 0);
1009 azx_dev->bufsize = 0; 990 azx_dev->bufsize = 0;
1010 azx_dev->period_bytes = 0; 991 azx_dev->period_bytes = 0;
1011 azx_dev->format_val = 0; 992 azx_dev->format_val = 0;
1012 993
1013 snd_dma_free_pages(dmab); 994 snd_dma_free_pages(dmab);
1014 dmab->area = NULL; 995 dmab->area = NULL;
1015 996
1016 spin_lock_irq(&bus->reg_lock); 997 spin_lock_irq(&bus->reg_lock);
1017 azx_dev->locked = false; 998 azx_dev->locked = false;
1018 spin_unlock_irq(&bus->reg_lock); 999 spin_unlock_irq(&bus->reg_lock);
1019 snd_hdac_dsp_unlock(azx_dev); 1000 snd_hdac_dsp_unlock(azx_dev);
1020 } 1001 }
1021 EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup); 1002 EXPORT_SYMBOL_GPL(snd_hdac_dsp_cleanup);
1022 #endif /* CONFIG_SND_HDA_DSP_LOADER */ 1003 #endif /* CONFIG_SND_HDA_DSP_LOADER */
1023 1004
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