1 /* SPDX-License-Identifier: GPL-2.0-only */ 1
2 #ifndef __HAL2_H
3 #define __HAL2_H
4
5 /*
6 * Driver for HAL2 sound processors
7 * Copyright (c) 1999 Ulf Carlsson <ulfc@bun.
8 * Copyright (c) 2001, 2002, 2003 Ladislav Mi
9 */
10
11 #include <linux/types.h>
12
13 /* Indirect status register */
14
15 #define H2_ISR_TSTATUS 0x01 /* RO:
16 #define H2_ISR_USTATUS 0x02 /* RO:
17 #define H2_ISR_QUAD_MODE 0x04 /* cod
18 #define H2_ISR_GLOBAL_RESET_N 0x08 /* chi
19 #define H2_ISR_CODEC_RESET_N 0x10 /* cod
20
21 /* Revision register */
22
23 #define H2_REV_AUDIO_PRESENT 0x8000 /* RO:
24 #define H2_REV_BOARD_M 0x7000 /* RO:
25 #define H2_REV_MAJOR_CHIP_M 0x00F0 /* RO:
26 #define H2_REV_MINOR_CHIP_M 0x000F /* RO:
27
28 /* Indirect address register */
29
30 /*
31 * Address of indirect internal register to be
32 * register initiates read or write access to
33 * HAL2. Note that there af four indirect data
34 * registers larger than 16 byte.
35 */
36
37 #define H2_IAR_TYPE_M 0xF000 /* bit
38 /* blo
39 /* 1=D
40 /* 9=G
41 /* 2=B
42 /* 3=U
43 #define H2_IAR_NUM_M 0x0F00 /* bit
44 /* blo
45 /* reg
46 /* If
47 /* 1=S
48 /* 2=A
49 /* 3=A
50 /* 4=D
51 /* 5=A
52 /* 6=S
53 /* If
54 /* 1=C
55 /* If
56 /* 1=B
57 /* 2=B
58 /* 3=B
59 /* If
60 /* 1=U
61 #define H2_IAR_ACCESS_SELECT 0x0080 /* 1=r
62 #define H2_IAR_PARAM 0x000C /* Par
63 #define H2_IAR_RB_INDEX_M 0x0003 /* Rea
64 /* 00:
65 /* 01:
66 /* 10:
67 /* 11:
68 /*
69 * HAL2 internal addressing
70 *
71 * The HAL2 has "indirect registers" (idr) whi
72 * Indirect Data registers. Write the address
73 * to transfer the data.
74 *
75 * We define the H2IR_* to the read address an
76 * H2I_* to be fields in whatever register is
77 *
78 * When we write to indirect registers which a
79 * we have to fill more than one indirect regi
80 * back however we have to read several times,
81 * Back Indexes (there are defs for doing this
82 */
83
84 /*
85 * Relay Control
86 */
87 #define H2I_RELAY_C 0x9100
88 #define H2I_RELAY_C_STATE 0x01
89
90 /* DMA port enable */
91
92 #define H2I_DMA_PORT_EN 0x9104
93 #define H2I_DMA_PORT_EN_SY_IN 0x01
94 #define H2I_DMA_PORT_EN_AESRX 0x02
95 #define H2I_DMA_PORT_EN_AESTX 0x04
96 #define H2I_DMA_PORT_EN_CODECTX 0x08
97 #define H2I_DMA_PORT_EN_CODECR 0x10
98
99 #define H2I_DMA_END 0x9108
100 #define H2I_DMA_END_SY_IN 0x01
101 #define H2I_DMA_END_AESRX 0x02
102 #define H2I_DMA_END_AESTX 0x04
103 #define H2I_DMA_END_CODECTX 0x08
104 #define H2I_DMA_END_CODECR 0x10
105
106
107 #define H2I_DMA_DRV 0x910C
108
109 #define H2I_SYNTH_C 0x1104
110
111 #define H2I_AESRX_C 0x1204
112
113 #define H2I_C_TS_EN 0x20
114 #define H2I_C_TS_FRMT 0x40
115 #define H2I_C_NAUDIO 0x80
116
117 /* AESRX CTL, 16 bit */
118
119 #define H2I_AESTX_C 0x1304
120 #define H2I_AESTX_C_CLKID_SHIFT 3
121 #define H2I_AESTX_C_CLKID_M 0x18
122 #define H2I_AESTX_C_DATAT_SHIFT 8
123 #define H2I_AESTX_C_DATAT_M 0x300
124
125 /* CODEC registers */
126
127 #define H2I_DAC_C1 0x1404
128 #define H2I_DAC_C2 0x1408
129 #define H2I_ADC_C1 0x1504
130 #define H2I_ADC_C2 0x1508
131
132 /* Bits in CTL1 register */
133
134 #define H2I_C1_DMA_SHIFT 0
135 #define H2I_C1_DMA_M 0x7
136 #define H2I_C1_CLKID_SHIFT 3
137 #define H2I_C1_CLKID_M 0x18
138 #define H2I_C1_DATAT_SHIFT 8
139 #define H2I_C1_DATAT_M 0x300
140
141 /* Bits in CTL2 register */
142
143 #define H2I_C2_R_GAIN_SHIFT 0
144 #define H2I_C2_R_GAIN_M 0xf
145 #define H2I_C2_L_GAIN_SHIFT 4
146 #define H2I_C2_L_GAIN_M 0xf0
147 #define H2I_C2_R_SEL 0x100
148 #define H2I_C2_L_SEL 0x200
149 #define H2I_C2_MUTE 0x400
150 #define H2I_C2_DO1 0x00010000
151 #define H2I_C2_DO2 0x00020000
152 #define H2I_C2_R_ATT_SHIFT 18
153 #define H2I_C2_R_ATT_M 0x007c0000
154 #define H2I_C2_L_ATT_SHIFT 23
155 #define H2I_C2_L_ATT_M 0x0f800000
156
157 #define H2I_SYNTH_MAP_C 0x1104
158
159 /* Clock generator CTL 1, 16 bit */
160
161 #define H2I_BRES1_C1 0x2104
162 #define H2I_BRES2_C1 0x2204
163 #define H2I_BRES3_C1 0x2304
164
165 #define H2I_BRES_C1_SHIFT 0
166 #define H2I_BRES_C1_M 0x03
167
168 /* Clock generator CTL 2, 32 bit */
169
170 #define H2I_BRES1_C2 0x2108
171 #define H2I_BRES2_C2 0x2208
172 #define H2I_BRES3_C2 0x2308
173
174 #define H2I_BRES_C2_INC_SHIFT 0
175 #define H2I_BRES_C2_INC_M 0xffff
176 #define H2I_BRES_C2_MOD_SHIFT 16
177 #define H2I_BRES_C2_MOD_M 0xffff0000
178
179 /* Unix timer, 64 bit */
180
181 #define H2I_UTIME 0x3104
182 #define H2I_UTIME_0_LD 0xffff
183 #define H2I_UTIME_1_LD0 0x0f
184 #define H2I_UTIME_1_LD1 0xf0
185 #define H2I_UTIME_2_LD 0xffff
186 #define H2I_UTIME_3_LD 0xffff
187
188 struct hal2_ctl_regs {
189 u32 _unused0[4];
190 u32 isr; /* 0x10 Status
191 u32 _unused1[3];
192 u32 rev; /* 0x20 Revisi
193 u32 _unused2[3];
194 u32 iar; /* 0x30 Indire
195 u32 _unused3[3];
196 u32 idr0; /* 0x40 Indire
197 u32 _unused4[3];
198 u32 idr1; /* 0x50 Indire
199 u32 _unused5[3];
200 u32 idr2; /* 0x60 Indire
201 u32 _unused6[3];
202 u32 idr3; /* 0x70 Indire
203 };
204
205 struct hal2_aes_regs {
206 u32 rx_stat[2]; /* Status registers */
207 u32 rx_cr[2]; /* Control reg
208 u32 rx_ud[4]; /* User data w
209 u32 rx_st[24]; /* Channel sta
210
211 u32 tx_stat[1]; /* Status register */
212 u32 tx_cr[3]; /* Control reg
213 u32 tx_ud[4]; /* User data w
214 u32 tx_st[24]; /* Channel sta
215 };
216
217 struct hal2_vol_regs {
218 u32 right; /* Right volum
219 u32 left; /* Left volume
220 };
221
222 struct hal2_syn_regs {
223 u32 _unused0[2];
224 u32 page; /* DOC Page re
225 u32 regsel; /* DOC Registe
226 u32 dlow; /* DOC Data lo
227 u32 dhigh; /* DOC Data hi
228 u32 irq; /* IRQ Status
229 u32 dram; /* DRAM Access
230 };
231
232 #endif /* __HAL2_H */
233
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