1 /* SPDX-License-Identifier: GPL-2.0-only */ <<
2 #ifndef __HAL2_H 1 #ifndef __HAL2_H
3 #define __HAL2_H 2 #define __HAL2_H
4 3
5 /* 4 /*
6 * Driver for HAL2 sound processors 5 * Driver for HAL2 sound processors
7 * Copyright (c) 1999 Ulf Carlsson <ulfc@bun. 6 * Copyright (c) 1999 Ulf Carlsson <ulfc@bun.falkenberg.se>
8 * Copyright (c) 2001, 2002, 2003 Ladislav Mi 7 * Copyright (c) 2001, 2002, 2003 Ladislav Michl <ladis@linux-mips.org>
>> 8 *
>> 9 * This program is free software; you can redistribute it and/or modify
>> 10 * it under the terms of the GNU General Public License version 2 as
>> 11 * published by the Free Software Foundation.
>> 12 *
>> 13 * This program is distributed in the hope that it will be useful,
>> 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 16 * GNU General Public License for more details.
>> 17 *
>> 18 * You should have received a copy of the GNU General Public License
>> 19 * along with this program; if not, write to the Free Software
>> 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
>> 21 *
9 */ 22 */
10 23
11 #include <linux/types.h> 24 #include <linux/types.h>
12 25
13 /* Indirect status register */ 26 /* Indirect status register */
14 27
15 #define H2_ISR_TSTATUS 0x01 /* RO: 28 #define H2_ISR_TSTATUS 0x01 /* RO: transaction status 1=busy */
16 #define H2_ISR_USTATUS 0x02 /* RO: 29 #define H2_ISR_USTATUS 0x02 /* RO: utime status bit 1=armed */
17 #define H2_ISR_QUAD_MODE 0x04 /* cod 30 #define H2_ISR_QUAD_MODE 0x04 /* codec mode 0=indigo 1=quad */
18 #define H2_ISR_GLOBAL_RESET_N 0x08 /* chi 31 #define H2_ISR_GLOBAL_RESET_N 0x08 /* chip global reset 0=reset */
19 #define H2_ISR_CODEC_RESET_N 0x10 /* cod 32 #define H2_ISR_CODEC_RESET_N 0x10 /* codec/synth reset 0=reset */
20 33
21 /* Revision register */ 34 /* Revision register */
22 35
23 #define H2_REV_AUDIO_PRESENT 0x8000 /* RO: 36 #define H2_REV_AUDIO_PRESENT 0x8000 /* RO: audio present 0=present */
24 #define H2_REV_BOARD_M 0x7000 /* RO: 37 #define H2_REV_BOARD_M 0x7000 /* RO: bits 14:12, board revision */
25 #define H2_REV_MAJOR_CHIP_M 0x00F0 /* RO: 38 #define H2_REV_MAJOR_CHIP_M 0x00F0 /* RO: bits 7:4, major chip revision */
26 #define H2_REV_MINOR_CHIP_M 0x000F /* RO: 39 #define H2_REV_MINOR_CHIP_M 0x000F /* RO: bits 3:0, minor chip revision */
27 40
28 /* Indirect address register */ 41 /* Indirect address register */
29 42
30 /* 43 /*
31 * Address of indirect internal register to be 44 * Address of indirect internal register to be accessed. A write to this
32 * register initiates read or write access to 45 * register initiates read or write access to the indirect registers in the
33 * HAL2. Note that there af four indirect data 46 * HAL2. Note that there af four indirect data registers for write access to
34 * registers larger than 16 byte. 47 * registers larger than 16 byte.
35 */ 48 */
36 49
37 #define H2_IAR_TYPE_M 0xF000 /* bit 50 #define H2_IAR_TYPE_M 0xF000 /* bits 15:12, type of functional */
38 /* blo 51 /* block the register resides in */
39 /* 1=D 52 /* 1=DMA Port */
40 /* 9=G 53 /* 9=Global DMA Control */
41 /* 2=B 54 /* 2=Bresenham */
42 /* 3=U 55 /* 3=Unix Timer */
43 #define H2_IAR_NUM_M 0x0F00 /* bit 56 #define H2_IAR_NUM_M 0x0F00 /* bits 11:8 instance of the */
44 /* blo 57 /* blockin which the indirect */
45 /* reg 58 /* register resides */
46 /* If 59 /* If IAR_TYPE_M=DMA Port: */
47 /* 1=S 60 /* 1=Synth In */
48 /* 2=A 61 /* 2=AES In */
49 /* 3=A 62 /* 3=AES Out */
50 /* 4=D 63 /* 4=DAC Out */
51 /* 5=A 64 /* 5=ADC Out */
52 /* 6=S 65 /* 6=Synth Control */
53 /* If 66 /* If IAR_TYPE_M=Global DMA Control: */
54 /* 1=C 67 /* 1=Control */
55 /* If 68 /* If IAR_TYPE_M=Bresenham: */
56 /* 1=B 69 /* 1=Bresenham Clock Gen 1 */
57 /* 2=B 70 /* 2=Bresenham Clock Gen 2 */
58 /* 3=B 71 /* 3=Bresenham Clock Gen 3 */
59 /* If 72 /* If IAR_TYPE_M=Unix Timer: */
60 /* 1=U 73 /* 1=Unix Timer */
61 #define H2_IAR_ACCESS_SELECT 0x0080 /* 1=r 74 #define H2_IAR_ACCESS_SELECT 0x0080 /* 1=read 0=write */
62 #define H2_IAR_PARAM 0x000C /* Par 75 #define H2_IAR_PARAM 0x000C /* Parameter Select */
63 #define H2_IAR_RB_INDEX_M 0x0003 /* Rea 76 #define H2_IAR_RB_INDEX_M 0x0003 /* Read Back Index */
64 /* 00: 77 /* 00:word0 */
65 /* 01: 78 /* 01:word1 */
66 /* 10: 79 /* 10:word2 */
67 /* 11: 80 /* 11:word3 */
68 /* 81 /*
69 * HAL2 internal addressing 82 * HAL2 internal addressing
70 * 83 *
71 * The HAL2 has "indirect registers" (idr) whi 84 * The HAL2 has "indirect registers" (idr) which are accessed by writing to the
72 * Indirect Data registers. Write the address 85 * Indirect Data registers. Write the address to the Indirect Address register
73 * to transfer the data. 86 * to transfer the data.
74 * 87 *
75 * We define the H2IR_* to the read address an 88 * We define the H2IR_* to the read address and H2IW_* to the write address and
76 * H2I_* to be fields in whatever register is 89 * H2I_* to be fields in whatever register is referred to.
77 * 90 *
78 * When we write to indirect registers which a 91 * When we write to indirect registers which are larger than one word (16 bit)
79 * we have to fill more than one indirect regi 92 * we have to fill more than one indirect register before writing. When we read
80 * back however we have to read several times, 93 * back however we have to read several times, each time with different Read
81 * Back Indexes (there are defs for doing this 94 * Back Indexes (there are defs for doing this easily).
82 */ 95 */
83 96
84 /* 97 /*
85 * Relay Control 98 * Relay Control
86 */ 99 */
87 #define H2I_RELAY_C 0x9100 100 #define H2I_RELAY_C 0x9100
88 #define H2I_RELAY_C_STATE 0x01 101 #define H2I_RELAY_C_STATE 0x01 /* state of RELAY pin signal */
89 102
90 /* DMA port enable */ 103 /* DMA port enable */
91 104
92 #define H2I_DMA_PORT_EN 0x9104 105 #define H2I_DMA_PORT_EN 0x9104
93 #define H2I_DMA_PORT_EN_SY_IN 0x01 106 #define H2I_DMA_PORT_EN_SY_IN 0x01 /* Synth_in DMA port */
94 #define H2I_DMA_PORT_EN_AESRX 0x02 107 #define H2I_DMA_PORT_EN_AESRX 0x02 /* AES receiver DMA port */
95 #define H2I_DMA_PORT_EN_AESTX 0x04 108 #define H2I_DMA_PORT_EN_AESTX 0x04 /* AES transmitter DMA port */
96 #define H2I_DMA_PORT_EN_CODECTX 0x08 109 #define H2I_DMA_PORT_EN_CODECTX 0x08 /* CODEC transmit DMA port */
97 #define H2I_DMA_PORT_EN_CODECR 0x10 110 #define H2I_DMA_PORT_EN_CODECR 0x10 /* CODEC receive DMA port */
98 111
99 #define H2I_DMA_END 0x9108 112 #define H2I_DMA_END 0x9108 /* global dma endian select */
100 #define H2I_DMA_END_SY_IN 0x01 113 #define H2I_DMA_END_SY_IN 0x01 /* Synth_in DMA port */
101 #define H2I_DMA_END_AESRX 0x02 114 #define H2I_DMA_END_AESRX 0x02 /* AES receiver DMA port */
102 #define H2I_DMA_END_AESTX 0x04 115 #define H2I_DMA_END_AESTX 0x04 /* AES transmitter DMA port */
103 #define H2I_DMA_END_CODECTX 0x08 116 #define H2I_DMA_END_CODECTX 0x08 /* CODEC transmit DMA port */
104 #define H2I_DMA_END_CODECR 0x10 117 #define H2I_DMA_END_CODECR 0x10 /* CODEC receive DMA port */
105 118 /* 0=b_end 1=l_end */
106 119
107 #define H2I_DMA_DRV 0x910C 120 #define H2I_DMA_DRV 0x910C /* global PBUS DMA enable */
108 121
109 #define H2I_SYNTH_C 0x1104 122 #define H2I_SYNTH_C 0x1104 /* Synth DMA control */
110 123
111 #define H2I_AESRX_C 0x1204 124 #define H2I_AESRX_C 0x1204 /* AES RX dma control */
112 125
113 #define H2I_C_TS_EN 0x20 126 #define H2I_C_TS_EN 0x20 /* Timestamp enable */
114 #define H2I_C_TS_FRMT 0x40 127 #define H2I_C_TS_FRMT 0x40 /* Timestamp format */
115 #define H2I_C_NAUDIO 0x80 128 #define H2I_C_NAUDIO 0x80 /* Sign extend */
116 129
117 /* AESRX CTL, 16 bit */ 130 /* AESRX CTL, 16 bit */
118 131
119 #define H2I_AESTX_C 0x1304 132 #define H2I_AESTX_C 0x1304 /* AES TX DMA control */
120 #define H2I_AESTX_C_CLKID_SHIFT 3 133 #define H2I_AESTX_C_CLKID_SHIFT 3 /* Bresenham Clock Gen 1-3 */
121 #define H2I_AESTX_C_CLKID_M 0x18 134 #define H2I_AESTX_C_CLKID_M 0x18
122 #define H2I_AESTX_C_DATAT_SHIFT 8 135 #define H2I_AESTX_C_DATAT_SHIFT 8 /* 1=mono 2=stereo (3=quad) */
123 #define H2I_AESTX_C_DATAT_M 0x300 136 #define H2I_AESTX_C_DATAT_M 0x300
124 137
125 /* CODEC registers */ 138 /* CODEC registers */
126 139
127 #define H2I_DAC_C1 0x1404 140 #define H2I_DAC_C1 0x1404 /* DAC DMA control, 16 bit */
128 #define H2I_DAC_C2 0x1408 141 #define H2I_DAC_C2 0x1408 /* DAC DMA control, 32 bit */
129 #define H2I_ADC_C1 0x1504 142 #define H2I_ADC_C1 0x1504 /* ADC DMA control, 16 bit */
130 #define H2I_ADC_C2 0x1508 143 #define H2I_ADC_C2 0x1508 /* ADC DMA control, 32 bit */
131 144
132 /* Bits in CTL1 register */ 145 /* Bits in CTL1 register */
133 146
134 #define H2I_C1_DMA_SHIFT 0 147 #define H2I_C1_DMA_SHIFT 0 /* DMA channel */
135 #define H2I_C1_DMA_M 0x7 148 #define H2I_C1_DMA_M 0x7
136 #define H2I_C1_CLKID_SHIFT 3 149 #define H2I_C1_CLKID_SHIFT 3 /* Bresenham Clock Gen 1-3 */
137 #define H2I_C1_CLKID_M 0x18 150 #define H2I_C1_CLKID_M 0x18
138 #define H2I_C1_DATAT_SHIFT 8 151 #define H2I_C1_DATAT_SHIFT 8 /* 1=mono 2=stereo (3=quad) */
139 #define H2I_C1_DATAT_M 0x300 152 #define H2I_C1_DATAT_M 0x300
140 153
141 /* Bits in CTL2 register */ 154 /* Bits in CTL2 register */
142 155
143 #define H2I_C2_R_GAIN_SHIFT 0 156 #define H2I_C2_R_GAIN_SHIFT 0 /* right a/d input gain */
144 #define H2I_C2_R_GAIN_M 0xf 157 #define H2I_C2_R_GAIN_M 0xf
145 #define H2I_C2_L_GAIN_SHIFT 4 158 #define H2I_C2_L_GAIN_SHIFT 4 /* left a/d input gain */
146 #define H2I_C2_L_GAIN_M 0xf0 159 #define H2I_C2_L_GAIN_M 0xf0
147 #define H2I_C2_R_SEL 0x100 160 #define H2I_C2_R_SEL 0x100 /* right input select */
148 #define H2I_C2_L_SEL 0x200 161 #define H2I_C2_L_SEL 0x200 /* left input select */
149 #define H2I_C2_MUTE 0x400 162 #define H2I_C2_MUTE 0x400 /* mute */
150 #define H2I_C2_DO1 0x00010000 163 #define H2I_C2_DO1 0x00010000 /* digital output port bit 0 */
151 #define H2I_C2_DO2 0x00020000 164 #define H2I_C2_DO2 0x00020000 /* digital output port bit 1 */
152 #define H2I_C2_R_ATT_SHIFT 18 165 #define H2I_C2_R_ATT_SHIFT 18 /* right d/a output - */
153 #define H2I_C2_R_ATT_M 0x007c0000 166 #define H2I_C2_R_ATT_M 0x007c0000 /* attenuation */
154 #define H2I_C2_L_ATT_SHIFT 23 167 #define H2I_C2_L_ATT_SHIFT 23 /* left d/a output - */
155 #define H2I_C2_L_ATT_M 0x0f800000 168 #define H2I_C2_L_ATT_M 0x0f800000 /* attenuation */
156 169
157 #define H2I_SYNTH_MAP_C 0x1104 170 #define H2I_SYNTH_MAP_C 0x1104 /* synth dma handshake ctrl */
158 171
159 /* Clock generator CTL 1, 16 bit */ 172 /* Clock generator CTL 1, 16 bit */
160 173
161 #define H2I_BRES1_C1 0x2104 174 #define H2I_BRES1_C1 0x2104
162 #define H2I_BRES2_C1 0x2204 175 #define H2I_BRES2_C1 0x2204
163 #define H2I_BRES3_C1 0x2304 176 #define H2I_BRES3_C1 0x2304
164 177
165 #define H2I_BRES_C1_SHIFT 0 178 #define H2I_BRES_C1_SHIFT 0 /* 0=48.0 1=44.1 2=aes_rx */
166 #define H2I_BRES_C1_M 0x03 179 #define H2I_BRES_C1_M 0x03
167 180
168 /* Clock generator CTL 2, 32 bit */ 181 /* Clock generator CTL 2, 32 bit */
169 182
170 #define H2I_BRES1_C2 0x2108 183 #define H2I_BRES1_C2 0x2108
171 #define H2I_BRES2_C2 0x2208 184 #define H2I_BRES2_C2 0x2208
172 #define H2I_BRES3_C2 0x2308 185 #define H2I_BRES3_C2 0x2308
173 186
174 #define H2I_BRES_C2_INC_SHIFT 0 187 #define H2I_BRES_C2_INC_SHIFT 0 /* increment value */
175 #define H2I_BRES_C2_INC_M 0xffff 188 #define H2I_BRES_C2_INC_M 0xffff
176 #define H2I_BRES_C2_MOD_SHIFT 16 189 #define H2I_BRES_C2_MOD_SHIFT 16 /* modcontrol value */
177 #define H2I_BRES_C2_MOD_M 0xffff0000 190 #define H2I_BRES_C2_MOD_M 0xffff0000 /* modctrl=0xffff&(modinc-1) */
178 191
179 /* Unix timer, 64 bit */ 192 /* Unix timer, 64 bit */
180 193
181 #define H2I_UTIME 0x3104 194 #define H2I_UTIME 0x3104
182 #define H2I_UTIME_0_LD 0xffff 195 #define H2I_UTIME_0_LD 0xffff /* microseconds, LSB's */
183 #define H2I_UTIME_1_LD0 0x0f 196 #define H2I_UTIME_1_LD0 0x0f /* microseconds, MSB's */
184 #define H2I_UTIME_1_LD1 0xf0 197 #define H2I_UTIME_1_LD1 0xf0 /* tenths of microseconds */
185 #define H2I_UTIME_2_LD 0xffff 198 #define H2I_UTIME_2_LD 0xffff /* seconds, LSB's */
186 #define H2I_UTIME_3_LD 0xffff 199 #define H2I_UTIME_3_LD 0xffff /* seconds, MSB's */
187 200
188 struct hal2_ctl_regs { 201 struct hal2_ctl_regs {
189 u32 _unused0[4]; 202 u32 _unused0[4];
190 u32 isr; /* 0x10 Status 203 u32 isr; /* 0x10 Status Register */
191 u32 _unused1[3]; 204 u32 _unused1[3];
192 u32 rev; /* 0x20 Revisi 205 u32 rev; /* 0x20 Revision Register */
193 u32 _unused2[3]; 206 u32 _unused2[3];
194 u32 iar; /* 0x30 Indire 207 u32 iar; /* 0x30 Indirect Address Register */
195 u32 _unused3[3]; 208 u32 _unused3[3];
196 u32 idr0; /* 0x40 Indire 209 u32 idr0; /* 0x40 Indirect Data Register 0 */
197 u32 _unused4[3]; 210 u32 _unused4[3];
198 u32 idr1; /* 0x50 Indire 211 u32 idr1; /* 0x50 Indirect Data Register 1 */
199 u32 _unused5[3]; 212 u32 _unused5[3];
200 u32 idr2; /* 0x60 Indire 213 u32 idr2; /* 0x60 Indirect Data Register 2 */
201 u32 _unused6[3]; 214 u32 _unused6[3];
202 u32 idr3; /* 0x70 Indire 215 u32 idr3; /* 0x70 Indirect Data Register 3 */
203 }; 216 };
204 217
205 struct hal2_aes_regs { 218 struct hal2_aes_regs {
206 u32 rx_stat[2]; /* Status registers */ 219 u32 rx_stat[2]; /* Status registers */
207 u32 rx_cr[2]; /* Control reg 220 u32 rx_cr[2]; /* Control registers */
208 u32 rx_ud[4]; /* User data w 221 u32 rx_ud[4]; /* User data window */
209 u32 rx_st[24]; /* Channel sta 222 u32 rx_st[24]; /* Channel status data */
210 223
211 u32 tx_stat[1]; /* Status register */ 224 u32 tx_stat[1]; /* Status register */
212 u32 tx_cr[3]; /* Control reg 225 u32 tx_cr[3]; /* Control registers */
213 u32 tx_ud[4]; /* User data w 226 u32 tx_ud[4]; /* User data window */
214 u32 tx_st[24]; /* Channel sta 227 u32 tx_st[24]; /* Channel status data */
215 }; 228 };
216 229
217 struct hal2_vol_regs { 230 struct hal2_vol_regs {
218 u32 right; /* Right volum 231 u32 right; /* Right volume */
219 u32 left; /* Left volume 232 u32 left; /* Left volume */
220 }; 233 };
221 234
222 struct hal2_syn_regs { 235 struct hal2_syn_regs {
223 u32 _unused0[2]; 236 u32 _unused0[2];
224 u32 page; /* DOC Page re 237 u32 page; /* DOC Page register */
225 u32 regsel; /* DOC Registe 238 u32 regsel; /* DOC Register selection */
226 u32 dlow; /* DOC Data lo 239 u32 dlow; /* DOC Data low */
227 u32 dhigh; /* DOC Data hi 240 u32 dhigh; /* DOC Data high */
228 u32 irq; /* IRQ Status 241 u32 irq; /* IRQ Status */
229 u32 dram; /* DRAM Access 242 u32 dram; /* DRAM Access */
230 }; 243 };
231 244
232 #endif /* __HAL2_H */ 245 #endif /* __HAL2_H */
233 246
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