1 /* SPDX-License-Identifier: GPL-2.0 */ 1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Analog Devices 1889 audio driver 2 /* Analog Devices 1889 audio driver 3 * Copyright (C) 2004, Kyle McMartin <kyle@par 3 * Copyright (C) 2004, Kyle McMartin <kyle@parisc-linux.org> 4 */ 4 */ 5 5 6 #ifndef __AD1889_H__ 6 #ifndef __AD1889_H__ 7 #define __AD1889_H__ 7 #define __AD1889_H__ 8 8 9 #define AD_DS_WSMC 0x00 /* wave/synthesis 9 #define AD_DS_WSMC 0x00 /* wave/synthesis channel mixer control */ 10 #define AD_DS_WSMC_SYEN 0x0004 /* synthesis c 10 #define AD_DS_WSMC_SYEN 0x0004 /* synthesis channel enable */ 11 #define AD_DS_WSMC_SYRQ 0x0030 /* synth. fifo 11 #define AD_DS_WSMC_SYRQ 0x0030 /* synth. fifo request point */ 12 #define AD_DS_WSMC_WA16 0x0100 /* wave channe 12 #define AD_DS_WSMC_WA16 0x0100 /* wave channel 16bit select */ 13 #define AD_DS_WSMC_WAST 0x0200 /* wave channe 13 #define AD_DS_WSMC_WAST 0x0200 /* wave channel stereo select */ 14 #define AD_DS_WSMC_WAEN 0x0400 /* wave channe 14 #define AD_DS_WSMC_WAEN 0x0400 /* wave channel enable */ 15 #define AD_DS_WSMC_WARQ 0x3000 /* wave fifo r 15 #define AD_DS_WSMC_WARQ 0x3000 /* wave fifo request point */ 16 16 17 #define AD_DS_RAMC 0x02 /* resampler/ADC 17 #define AD_DS_RAMC 0x02 /* resampler/ADC channel mixer control */ 18 #define AD_DS_RAMC_AD16 0x0001 /* ADC channel 18 #define AD_DS_RAMC_AD16 0x0001 /* ADC channel 16bit select */ 19 #define AD_DS_RAMC_ADST 0x0002 /* ADC channel 19 #define AD_DS_RAMC_ADST 0x0002 /* ADC channel stereo select */ 20 #define AD_DS_RAMC_ADEN 0x0004 /* ADC channel 20 #define AD_DS_RAMC_ADEN 0x0004 /* ADC channel enable */ 21 #define AD_DS_RAMC_ACRQ 0x0030 /* ADC fifo re 21 #define AD_DS_RAMC_ACRQ 0x0030 /* ADC fifo request point */ 22 #define AD_DS_RAMC_REEN 0x0400 /* resampler c 22 #define AD_DS_RAMC_REEN 0x0400 /* resampler channel enable */ 23 #define AD_DS_RAMC_RERQ 0x3000 /* res. fifo r 23 #define AD_DS_RAMC_RERQ 0x3000 /* res. fifo request point */ 24 24 25 #define AD_DS_WADA 0x04 /* wave channel m 25 #define AD_DS_WADA 0x04 /* wave channel mix attenuation */ 26 #define AD_DS_WADA_RWAM 0x0080 /* right wave 26 #define AD_DS_WADA_RWAM 0x0080 /* right wave mute */ 27 #define AD_DS_WADA_RWAA 0x001f /* right wave 27 #define AD_DS_WADA_RWAA 0x001f /* right wave attenuation */ 28 #define AD_DS_WADA_LWAM 0x8000 /* left wave m 28 #define AD_DS_WADA_LWAM 0x8000 /* left wave mute */ 29 #define AD_DS_WADA_LWAA 0x3e00 /* left wave a 29 #define AD_DS_WADA_LWAA 0x3e00 /* left wave attenuation */ 30 30 31 #define AD_DS_SYDA 0x06 /* synthesis chan 31 #define AD_DS_SYDA 0x06 /* synthesis channel mix attenuation */ 32 #define AD_DS_SYDA_RSYM 0x0080 /* right synth 32 #define AD_DS_SYDA_RSYM 0x0080 /* right synthesis mute */ 33 #define AD_DS_SYDA_RSYA 0x001f /* right synth 33 #define AD_DS_SYDA_RSYA 0x001f /* right synthesis attenuation */ 34 #define AD_DS_SYDA_LSYM 0x8000 /* left synthe 34 #define AD_DS_SYDA_LSYM 0x8000 /* left synthesis mute */ 35 #define AD_DS_SYDA_LSYA 0x3e00 /* left synthe 35 #define AD_DS_SYDA_LSYA 0x3e00 /* left synthesis attenuation */ 36 36 37 #define AD_DS_WAS 0x08 /* wave channel s 37 #define AD_DS_WAS 0x08 /* wave channel sample rate */ 38 #define AD_DS_WAS_WAS 0xffff /* sample rate 38 #define AD_DS_WAS_WAS 0xffff /* sample rate mask */ 39 39 40 #define AD_DS_RES 0x0a /* resampler chan 40 #define AD_DS_RES 0x0a /* resampler channel sample rate */ 41 #define AD_DS_RES_RES 0xffff /* sample rate 41 #define AD_DS_RES_RES 0xffff /* sample rate mask */ 42 42 43 #define AD_DS_CCS 0x0c /* chip control/s 43 #define AD_DS_CCS 0x0c /* chip control/status */ 44 #define AD_DS_CCS_ADO 0x0001 /* ADC channel 44 #define AD_DS_CCS_ADO 0x0001 /* ADC channel overflow */ 45 #define AD_DS_CCS_REO 0x0002 /* resampler c 45 #define AD_DS_CCS_REO 0x0002 /* resampler channel overflow */ 46 #define AD_DS_CCS_SYU 0x0004 /* synthesis c 46 #define AD_DS_CCS_SYU 0x0004 /* synthesis channel underflow */ 47 #define AD_DS_CCS_WAU 0x0008 /* wave channe 47 #define AD_DS_CCS_WAU 0x0008 /* wave channel underflow */ 48 /* bits 4 -> 7, 9, 11 -> 14 reserved */ 48 /* bits 4 -> 7, 9, 11 -> 14 reserved */ 49 #define AD_DS_CCS_XTD 0x0100 /* xtd delay c 49 #define AD_DS_CCS_XTD 0x0100 /* xtd delay control (4096 clock cycles) */ 50 #define AD_DS_CCS_PDALL 0x0400 /* power */ 50 #define AD_DS_CCS_PDALL 0x0400 /* power */ 51 #define AD_DS_CCS_CLKEN 0x8000 /* clock */ 51 #define AD_DS_CCS_CLKEN 0x8000 /* clock */ 52 52 53 #define AD_DMA_RESBA 0x40 /* RES base addre 53 #define AD_DMA_RESBA 0x40 /* RES base address */ 54 #define AD_DMA_RESCA 0x44 /* RES current ad 54 #define AD_DMA_RESCA 0x44 /* RES current address */ 55 #define AD_DMA_RESBC 0x48 /* RES base count 55 #define AD_DMA_RESBC 0x48 /* RES base count */ 56 #define AD_DMA_RESCC 0x4c /* RES current co 56 #define AD_DMA_RESCC 0x4c /* RES current count */ 57 57 58 #define AD_DMA_ADCBA 0x50 /* ADC base addre 58 #define AD_DMA_ADCBA 0x50 /* ADC base address */ 59 #define AD_DMA_ADCCA 0x54 /* ADC current ad 59 #define AD_DMA_ADCCA 0x54 /* ADC current address */ 60 #define AD_DMA_ADCBC 0x58 /* ADC base count 60 #define AD_DMA_ADCBC 0x58 /* ADC base count */ 61 #define AD_DMA_ADCCC 0x5c /* ADC current co 61 #define AD_DMA_ADCCC 0x5c /* ADC current count */ 62 62 63 #define AD_DMA_SYNBA 0x60 /* synth base add 63 #define AD_DMA_SYNBA 0x60 /* synth base address */ 64 #define AD_DMA_SYNCA 0x64 /* synth current 64 #define AD_DMA_SYNCA 0x64 /* synth current address */ 65 #define AD_DMA_SYNBC 0x68 /* synth base cou 65 #define AD_DMA_SYNBC 0x68 /* synth base count */ 66 #define AD_DMA_SYNCC 0x6c /* synth current 66 #define AD_DMA_SYNCC 0x6c /* synth current count */ 67 67 68 #define AD_DMA_WAVBA 0x70 /* wave base addr 68 #define AD_DMA_WAVBA 0x70 /* wave base address */ 69 #define AD_DMA_WAVCA 0x74 /* wave current a 69 #define AD_DMA_WAVCA 0x74 /* wave current address */ 70 #define AD_DMA_WAVBC 0x78 /* wave base coun 70 #define AD_DMA_WAVBC 0x78 /* wave base count */ 71 #define AD_DMA_WAVCC 0x7c /* wave current c 71 #define AD_DMA_WAVCC 0x7c /* wave current count */ 72 72 73 #define AD_DMA_RESIC 0x80 /* RES dma interr 73 #define AD_DMA_RESIC 0x80 /* RES dma interrupt current byte count */ 74 #define AD_DMA_RESIB 0x84 /* RES dma interr 74 #define AD_DMA_RESIB 0x84 /* RES dma interrupt base byte count */ 75 75 76 #define AD_DMA_ADCIC 0x88 /* ADC dma interr 76 #define AD_DMA_ADCIC 0x88 /* ADC dma interrupt current byte count */ 77 #define AD_DMA_ADCIB 0x8c /* ADC dma interr 77 #define AD_DMA_ADCIB 0x8c /* ADC dma interrupt base byte count */ 78 78 79 #define AD_DMA_SYNIC 0x90 /* synth dma inte 79 #define AD_DMA_SYNIC 0x90 /* synth dma interrupt current byte count */ 80 #define AD_DMA_SYNIB 0x94 /* synth dma inte 80 #define AD_DMA_SYNIB 0x94 /* synth dma interrupt base byte count */ 81 81 82 #define AD_DMA_WAVIC 0x98 /* wave dma inter 82 #define AD_DMA_WAVIC 0x98 /* wave dma interrupt current byte count */ 83 #define AD_DMA_WAVIB 0x9c /* wave dma inter 83 #define AD_DMA_WAVIB 0x9c /* wave dma interrupt base byte count */ 84 84 85 #define AD_DMA_ICC 0xffffff /* current by 85 #define AD_DMA_ICC 0xffffff /* current byte count mask */ 86 #define AD_DMA_IBC 0xffffff /* base byte 86 #define AD_DMA_IBC 0xffffff /* base byte count mask */ 87 /* bits 24 -> 31 reserved */ 87 /* bits 24 -> 31 reserved */ 88 88 89 /* 4 bytes pad */ 89 /* 4 bytes pad */ 90 #define AD_DMA_ADC 0xa8 /* ADC dm 90 #define AD_DMA_ADC 0xa8 /* ADC dma control and status */ 91 #define AD_DMA_SYNTH 0xb0 /* Synth dm 91 #define AD_DMA_SYNTH 0xb0 /* Synth dma control and status */ 92 #define AD_DMA_WAV 0xb8 /* wave dm 92 #define AD_DMA_WAV 0xb8 /* wave dma control and status */ 93 #define AD_DMA_RES 0xa0 /* Resample dm 93 #define AD_DMA_RES 0xa0 /* Resample dma control and status */ 94 94 95 #define AD_DMA_SGDE 0x0001 /* SGD mode ena 95 #define AD_DMA_SGDE 0x0001 /* SGD mode enable */ 96 #define AD_DMA_LOOP 0x0002 /* loop enable 96 #define AD_DMA_LOOP 0x0002 /* loop enable */ 97 #define AD_DMA_IM 0x000c /* interrupt mo 97 #define AD_DMA_IM 0x000c /* interrupt mode mask */ 98 #define AD_DMA_IM_DIS (~AD_DMA_IM) /* dis 98 #define AD_DMA_IM_DIS (~AD_DMA_IM) /* disable */ 99 #define AD_DMA_IM_CNT 0x0004 /* interrupt on 99 #define AD_DMA_IM_CNT 0x0004 /* interrupt on count */ 100 #define AD_DMA_IM_SGD 0x0008 /* interrupt on 100 #define AD_DMA_IM_SGD 0x0008 /* interrupt on SGD flag */ 101 #define AD_DMA_IM_EOL 0x000c /* interrupt on 101 #define AD_DMA_IM_EOL 0x000c /* interrupt on End of Linked List */ 102 #define AD_DMA_SGDS 0x0030 /* SGD status * 102 #define AD_DMA_SGDS 0x0030 /* SGD status */ 103 #define AD_DMA_SFLG 0x0040 /* SGD flag */ 103 #define AD_DMA_SFLG 0x0040 /* SGD flag */ 104 #define AD_DMA_EOL 0x0080 /* SGD end of l 104 #define AD_DMA_EOL 0x0080 /* SGD end of list */ 105 /* bits 8 -> 15 reserved */ 105 /* bits 8 -> 15 reserved */ 106 106 107 #define AD_DMA_DISR 0xc0 /* dma interrupt 107 #define AD_DMA_DISR 0xc0 /* dma interrupt status */ 108 #define AD_DMA_DISR_RESI 0x000001 /* resample 108 #define AD_DMA_DISR_RESI 0x000001 /* resampler channel interrupt */ 109 #define AD_DMA_DISR_ADCI 0x000002 /* ADC chan 109 #define AD_DMA_DISR_ADCI 0x000002 /* ADC channel interrupt */ 110 #define AD_DMA_DISR_SYNI 0x000004 /* synthesi 110 #define AD_DMA_DISR_SYNI 0x000004 /* synthesis channel interrupt */ 111 #define AD_DMA_DISR_WAVI 0x000008 /* wave cha 111 #define AD_DMA_DISR_WAVI 0x000008 /* wave channel interrupt */ 112 /* bits 4, 5 reserved */ 112 /* bits 4, 5 reserved */ 113 #define AD_DMA_DISR_SEPS 0x000040 /* serial e 113 #define AD_DMA_DISR_SEPS 0x000040 /* serial eeprom status */ 114 /* bits 7 -> 13 reserved */ 114 /* bits 7 -> 13 reserved */ 115 #define AD_DMA_DISR_PMAI 0x004000 /* pci mast 115 #define AD_DMA_DISR_PMAI 0x004000 /* pci master abort interrupt */ 116 #define AD_DMA_DISR_PTAI 0x008000 /* pci targ 116 #define AD_DMA_DISR_PTAI 0x008000 /* pci target abort interrupt */ 117 #define AD_DMA_DISR_PTAE 0x010000 /* pci targ 117 #define AD_DMA_DISR_PTAE 0x010000 /* pci target abort interrupt enable */ 118 #define AD_DMA_DISR_PMAE 0x020000 /* pci mast 118 #define AD_DMA_DISR_PMAE 0x020000 /* pci master abort interrupt enable */ 119 /* bits 19 -> 31 reserved */ 119 /* bits 19 -> 31 reserved */ 120 120 121 /* interrupt mask */ 121 /* interrupt mask */ 122 #define AD_INTR_MASK (AD_DMA_DISR_RESI|AD 122 #define AD_INTR_MASK (AD_DMA_DISR_RESI|AD_DMA_DISR_ADCI| \ 123 AD_DMA_DISR_WAVI|AD 123 AD_DMA_DISR_WAVI|AD_DMA_DISR_SYNI| \ 124 AD_DMA_DISR_PMAI|AD 124 AD_DMA_DISR_PMAI|AD_DMA_DISR_PTAI) 125 125 126 #define AD_DMA_CHSS 0xc4 /* dma channel st 126 #define AD_DMA_CHSS 0xc4 /* dma channel stop status */ 127 #define AD_DMA_CHSS_RESS 0x000001 /* resample 127 #define AD_DMA_CHSS_RESS 0x000001 /* resampler channel stopped */ 128 #define AD_DMA_CHSS_ADCS 0x000002 /* ADC chan 128 #define AD_DMA_CHSS_ADCS 0x000002 /* ADC channel stopped */ 129 #define AD_DMA_CHSS_SYNS 0x000004 /* synthesi 129 #define AD_DMA_CHSS_SYNS 0x000004 /* synthesis channel stopped */ 130 #define AD_DMA_CHSS_WAVS 0x000008 /* wave cha 130 #define AD_DMA_CHSS_WAVS 0x000008 /* wave channel stopped */ 131 131 132 #define AD_GPIO_IPC 0xc8 /* gpio port c 132 #define AD_GPIO_IPC 0xc8 /* gpio port control */ 133 #define AD_GPIO_OP 0xca /* gpio output 133 #define AD_GPIO_OP 0xca /* gpio output port status */ 134 #define AD_GPIO_IP 0xcc /* gpio input 134 #define AD_GPIO_IP 0xcc /* gpio input port status */ 135 135 136 #define AD_AC97_BASE 0x100 /* ac97 base r 136 #define AD_AC97_BASE 0x100 /* ac97 base register */ 137 137 138 #define AD_AC97_RESET 0x100 /* reset */ 138 #define AD_AC97_RESET 0x100 /* reset */ 139 139 140 #define AD_AC97_PWR_CTL 0x126 /* == AC97_POW 140 #define AD_AC97_PWR_CTL 0x126 /* == AC97_POWERDOWN */ 141 #define AD_AC97_PWR_ADC 0x0001 /* ADC ready s 141 #define AD_AC97_PWR_ADC 0x0001 /* ADC ready status */ 142 #define AD_AC97_PWR_DAC 0x0002 /* DAC ready s 142 #define AD_AC97_PWR_DAC 0x0002 /* DAC ready status */ 143 #define AD_AC97_PWR_PR0 0x0100 /* PR0 (ADC) p 143 #define AD_AC97_PWR_PR0 0x0100 /* PR0 (ADC) powerdown */ 144 #define AD_AC97_PWR_PR1 0x0200 /* PR1 (DAC) p 144 #define AD_AC97_PWR_PR1 0x0200 /* PR1 (DAC) powerdown */ 145 145 146 #define AD_MISC_CTL 0x176 /* misc control 146 #define AD_MISC_CTL 0x176 /* misc control */ 147 #define AD_MISC_CTL_DACZ 0x8000 /* set for 147 #define AD_MISC_CTL_DACZ 0x8000 /* set for zero fill, unset for repeat */ 148 #define AD_MISC_CTL_ARSR 0x0001 /* set for 148 #define AD_MISC_CTL_ARSR 0x0001 /* set for SR1, unset for SR0 */ 149 #define AD_MISC_CTL_ALSR 0x0100 149 #define AD_MISC_CTL_ALSR 0x0100 150 #define AD_MISC_CTL_DLSR 0x0400 150 #define AD_MISC_CTL_DLSR 0x0400 151 #define AD_MISC_CTL_DRSR 0x0004 151 #define AD_MISC_CTL_DRSR 0x0004 152 152 153 #define AD_AC97_SR0 0x178 /* sample rate 0 153 #define AD_AC97_SR0 0x178 /* sample rate 0, 0xbb80 == 48K */ 154 #define AD_AC97_SR0_48K 0xbb80 /* 48KHz */ 154 #define AD_AC97_SR0_48K 0xbb80 /* 48KHz */ 155 #define AD_AC97_SR1 0x17a /* sample rate 1 155 #define AD_AC97_SR1 0x17a /* sample rate 1 */ 156 156 157 #define AD_AC97_ACIC 0x180 /* ac97 codec in 157 #define AD_AC97_ACIC 0x180 /* ac97 codec interface control */ 158 #define AD_AC97_ACIC_ACIE 0x0001 /* analog c 158 #define AD_AC97_ACIC_ACIE 0x0001 /* analog codec interface enable */ 159 #define AD_AC97_ACIC_ACRD 0x0002 /* analog c 159 #define AD_AC97_ACIC_ACRD 0x0002 /* analog codec reset disable */ 160 #define AD_AC97_ACIC_ASOE 0x0004 /* audio st 160 #define AD_AC97_ACIC_ASOE 0x0004 /* audio stream output enable */ 161 #define AD_AC97_ACIC_VSRM 0x0008 /* variable 161 #define AD_AC97_ACIC_VSRM 0x0008 /* variable sample rate mode */ 162 #define AD_AC97_ACIC_FSDH 0x0100 /* force SD 162 #define AD_AC97_ACIC_FSDH 0x0100 /* force SDATA_OUT high */ 163 #define AD_AC97_ACIC_FSYH 0x0200 /* force sy 163 #define AD_AC97_ACIC_FSYH 0x0200 /* force sync high */ 164 #define AD_AC97_ACIC_ACRDY 0x8000 /* analog c 164 #define AD_AC97_ACIC_ACRDY 0x8000 /* analog codec ready status */ 165 /* bits 10 -> 14 reserved */ 165 /* bits 10 -> 14 reserved */ 166 166 167 167 168 #define AD_DS_MEMSIZE 512 168 #define AD_DS_MEMSIZE 512 169 #define AD_OPL_MEMSIZE 16 169 #define AD_OPL_MEMSIZE 16 170 #define AD_MIDI_MEMSIZE 16 170 #define AD_MIDI_MEMSIZE 16 171 171 172 #define AD_WAV_STATE 0 172 #define AD_WAV_STATE 0 173 #define AD_ADC_STATE 1 173 #define AD_ADC_STATE 1 174 #define AD_MAX_STATES 2 174 #define AD_MAX_STATES 2 175 175 176 #define AD_CHAN_WAV 0x0001 176 #define AD_CHAN_WAV 0x0001 177 #define AD_CHAN_ADC 0x0002 177 #define AD_CHAN_ADC 0x0002 178 #define AD_CHAN_RES 0x0004 178 #define AD_CHAN_RES 0x0004 179 #define AD_CHAN_SYN 0x0008 179 #define AD_CHAN_SYN 0x0008 180 180 181 181 182 /* The chip would support 4 GB buffers and 16 182 /* The chip would support 4 GB buffers and 16 MB periods, 183 * but let's not overdo it ... */ 183 * but let's not overdo it ... */ 184 #define BUFFER_BYTES_MAX (256 * 1024) 184 #define BUFFER_BYTES_MAX (256 * 1024) 185 #define PERIOD_BYTES_MIN 32 185 #define PERIOD_BYTES_MIN 32 186 #define PERIOD_BYTES_MAX (BUFFER_BYTES_ 186 #define PERIOD_BYTES_MAX (BUFFER_BYTES_MAX / 2) 187 #define PERIODS_MIN 2 187 #define PERIODS_MIN 2 188 #define PERIODS_MAX (BUFFER_BYTES_ 188 #define PERIODS_MAX (BUFFER_BYTES_MAX / PERIOD_BYTES_MIN) 189 189 190 #endif /* __AD1889_H__ */ 190 #endif /* __AD1889_H__ */ 191 191
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.