1 /* SPDX-License-Identifier: GPL-2.0 */ << 2 /* 1 /* 3 Aureal Vortex Soundcard driver. 2 Aureal Vortex Soundcard driver. 4 3 5 IO addr collected from asp4core.vxd: 4 IO addr collected from asp4core.vxd: 6 function address 5 function address 7 0005D5A0 13004 6 0005D5A0 13004 8 00080674 14004 7 00080674 14004 9 00080AFF 12818 8 00080AFF 12818 10 9 11 */ 10 */ 12 11 13 #define CHIP_AU8820 12 #define CHIP_AU8820 14 13 15 #define CARD_NAME "Aureal Vortex" 14 #define CARD_NAME "Aureal Vortex" 16 #define CARD_NAME_SHORT "au8820" 15 #define CARD_NAME_SHORT "au8820" 17 16 18 /* Number of ADB and WT channels */ 17 /* Number of ADB and WT channels */ 19 #define NR_ADB 0x10 18 #define NR_ADB 0x10 20 #define NR_WT 0x20 19 #define NR_WT 0x20 21 #define NR_SRC 0x10 20 #define NR_SRC 0x10 22 #define NR_A3D 0x00 21 #define NR_A3D 0x00 23 #define NR_MIXIN 0x10 22 #define NR_MIXIN 0x10 24 #define NR_MIXOUT 0x10 23 #define NR_MIXOUT 0x10 25 24 26 25 27 /* ADBDMA */ 26 /* ADBDMA */ 28 #define VORTEX_ADBDMA_STAT 0x105c0 /* rea 27 #define VORTEX_ADBDMA_STAT 0x105c0 /* read only, subbuffer, DMA pos */ 29 #define POS_MASK 0x00000fff 28 #define POS_MASK 0x00000fff 30 #define POS_SHIFT 0x0 29 #define POS_SHIFT 0x0 31 #define ADB_SUBBUF_MASK 0x00003000 30 #define ADB_SUBBUF_MASK 0x00003000 /* ADB only. */ 32 #define ADB_SUBBUF_SHIFT 0xc /* ADB 31 #define ADB_SUBBUF_SHIFT 0xc /* ADB only. */ 33 #define VORTEX_ADBDMA_CTRL 0x10580 /* wri 32 #define VORTEX_ADBDMA_CTRL 0x10580 /* write only, format, flags, DMA pos */ 34 #define OFFSET_MASK 0x00000fff 33 #define OFFSET_MASK 0x00000fff 35 #define OFFSET_SHIFT 0x0 34 #define OFFSET_SHIFT 0x0 36 #define IE_MASK 0x00001000 /* int 35 #define IE_MASK 0x00001000 /* interrupt enable. */ 37 #define IE_SHIFT 0xc 36 #define IE_SHIFT 0xc 38 #define DIR_MASK 0x00002000 /* Direction. 37 #define DIR_MASK 0x00002000 /* Direction. */ 39 #define DIR_SHIFT 0xd 38 #define DIR_SHIFT 0xd 40 #define FMT_MASK 0x0003c000 39 #define FMT_MASK 0x0003c000 41 #define FMT_SHIFT 0xe 40 #define FMT_SHIFT 0xe 42 // The masks and shift also work for the wtdma 41 // The masks and shift also work for the wtdma, if not specified otherwise. 43 #define VORTEX_ADBDMA_BUFCFG0 0x10400 42 #define VORTEX_ADBDMA_BUFCFG0 0x10400 44 #define VORTEX_ADBDMA_BUFCFG1 0x10404 43 #define VORTEX_ADBDMA_BUFCFG1 0x10404 45 #define VORTEX_ADBDMA_BUFBASE 0x10200 44 #define VORTEX_ADBDMA_BUFBASE 0x10200 46 #define VORTEX_ADBDMA_START 0x106c0 /* Whi 45 #define VORTEX_ADBDMA_START 0x106c0 /* Which subbuffer starts */ 47 #define VORTEX_ADBDMA_STATUS 0x10600 /* sto 46 #define VORTEX_ADBDMA_STATUS 0x10600 /* stored at AdbDma->this_10 / 2 DWORD in size. */ 48 47 49 /* ADB */ 48 /* ADB */ 50 #define VORTEX_ADB_SR 0x10a00 /* Samplerates 49 #define VORTEX_ADB_SR 0x10a00 /* Samplerates enable/disable */ 51 #define VORTEX_ADB_RTBASE 0x10800 50 #define VORTEX_ADB_RTBASE 0x10800 52 #define VORTEX_ADB_RTBASE_COUNT 103 51 #define VORTEX_ADB_RTBASE_COUNT 103 53 #define VORTEX_ADB_CHNBASE 0x1099c 52 #define VORTEX_ADB_CHNBASE 0x1099c 54 #define VORTEX_ADB_CHNBASE_COUNT 22 53 #define VORTEX_ADB_CHNBASE_COUNT 22 55 #define ROUTE_MASK 0x3fff 54 #define ROUTE_MASK 0x3fff 56 #define ADB_MASK 0x7f 55 #define ADB_MASK 0x7f 57 #define ADB_SHIFT 0x7 56 #define ADB_SHIFT 0x7 58 //#define ADB_MIX_MASK 0xf 57 //#define ADB_MIX_MASK 0xf 59 /* ADB address */ 58 /* ADB address */ 60 #define OFFSET_ADBDMA 0x00 59 #define OFFSET_ADBDMA 0x00 61 #define OFFSET_SRCOUT 0x10 /* on 60 #define OFFSET_SRCOUT 0x10 /* on channel 0x11 */ 62 #define OFFSET_SRCIN 0x10 /* on 61 #define OFFSET_SRCIN 0x10 /* on channel < 0x11 */ 63 #define OFFSET_MIXOUT 0x20 /* sou 62 #define OFFSET_MIXOUT 0x20 /* source */ 64 #define OFFSET_MIXIN 0x30 /* sin 63 #define OFFSET_MIXIN 0x30 /* sink */ 65 #define OFFSET_CODECIN 0x48 /* ADB 64 #define OFFSET_CODECIN 0x48 /* ADB source */ 66 #define OFFSET_CODECOUT 0x58 /* ADB 65 #define OFFSET_CODECOUT 0x58 /* ADB sink/target */ 67 #define OFFSET_SPORTOUT 0x60 /* sin 66 #define OFFSET_SPORTOUT 0x60 /* sink */ 68 #define OFFSET_SPORTIN 0x50 /* sou 67 #define OFFSET_SPORTIN 0x50 /* source */ 69 #define OFFSET_EFXOUT 0x50 /* sin 68 #define OFFSET_EFXOUT 0x50 /* sink */ 70 #define OFFSET_EFXIN 0x40 /* sou 69 #define OFFSET_EFXIN 0x40 /* source */ 71 #define OFFSET_A3DOUT 0x00 /* Thi 70 #define OFFSET_A3DOUT 0x00 /* This card has no HRTF :( */ 72 #define OFFSET_A3DIN 0x00 71 #define OFFSET_A3DIN 0x00 73 #define OFFSET_WTOUT 0x58 /* */ 72 #define OFFSET_WTOUT 0x58 /* */ 74 73 75 /* ADB route translate helper */ 74 /* ADB route translate helper */ 76 #define ADB_DMA(x) (x + OFFSET_ADBDMA) 75 #define ADB_DMA(x) (x + OFFSET_ADBDMA) 77 #define ADB_SRCOUT(x) (x + OFFSET_SRCOUT) 76 #define ADB_SRCOUT(x) (x + OFFSET_SRCOUT) 78 #define ADB_SRCIN(x) (x + OFFSET_SRCIN) 77 #define ADB_SRCIN(x) (x + OFFSET_SRCIN) 79 #define ADB_MIXOUT(x) (x + OFFSET_MIXOUT) 78 #define ADB_MIXOUT(x) (x + OFFSET_MIXOUT) 80 #define ADB_MIXIN(x) (x + OFFSET_MIXIN) 79 #define ADB_MIXIN(x) (x + OFFSET_MIXIN) 81 #define ADB_CODECIN(x) (x + OFFSET_CODECIN) 80 #define ADB_CODECIN(x) (x + OFFSET_CODECIN) 82 #define ADB_CODECOUT(x) (x + OFFSET_CODECOUT) 81 #define ADB_CODECOUT(x) (x + OFFSET_CODECOUT) 83 #define ADB_SPORTOUT(x) (x + OFFSET_SPORTOUT) 82 #define ADB_SPORTOUT(x) (x + OFFSET_SPORTOUT) 84 #define ADB_SPORTIN(x) (x + OFFSET_SPORTIN) 83 #define ADB_SPORTIN(x) (x + OFFSET_SPORTIN) /* */ 85 #define ADB_A3DOUT(x) (x + OFFSET_A3DOUT) 84 #define ADB_A3DOUT(x) (x + OFFSET_A3DOUT) /* 8 A3D blocks */ 86 #define ADB_A3DIN(x) (x + OFFSET_A3DIN) 85 #define ADB_A3DIN(x) (x + OFFSET_A3DIN) 87 #define ADB_WTOUT(x,y) (y + OFFSET_WTOUT) 86 #define ADB_WTOUT(x,y) (y + OFFSET_WTOUT) 88 87 89 /* WTDMA */ 88 /* WTDMA */ 90 #define VORTEX_WTDMA_CTRL 0x10500 /* for 89 #define VORTEX_WTDMA_CTRL 0x10500 /* format, DMA pos */ 91 #define VORTEX_WTDMA_STAT 0x10500 /* DMA 90 #define VORTEX_WTDMA_STAT 0x10500 /* DMA subbuf, DMA pos */ 92 #define WT_SUBBUF_MASK (0x3 << WT_SUBBUF_S 91 #define WT_SUBBUF_MASK (0x3 << WT_SUBBUF_SHIFT) 93 #define WT_SUBBUF_SHIFT 0x15 92 #define WT_SUBBUF_SHIFT 0x15 94 #define VORTEX_WTDMA_BUFBASE 0x10000 93 #define VORTEX_WTDMA_BUFBASE 0x10000 95 #define VORTEX_WTDMA_BUFCFG0 0x10300 94 #define VORTEX_WTDMA_BUFCFG0 0x10300 96 #define VORTEX_WTDMA_BUFCFG1 0x10304 95 #define VORTEX_WTDMA_BUFCFG1 0x10304 97 #define VORTEX_WTDMA_START 0x10640 /* whi 96 #define VORTEX_WTDMA_START 0x10640 /* which subbuffer is first */ 98 97 99 #define VORTEX_WT_BASE 0x9000 98 #define VORTEX_WT_BASE 0x9000 100 99 101 /* MIXER */ 100 /* MIXER */ 102 #define VORTEX_MIXER_SR 0x9f00 101 #define VORTEX_MIXER_SR 0x9f00 103 #define VORTEX_MIXER_CLIP 0x9f80 102 #define VORTEX_MIXER_CLIP 0x9f80 104 #define VORTEX_MIXER_CHNBASE 0x9e40 103 #define VORTEX_MIXER_CHNBASE 0x9e40 105 #define VORTEX_MIXER_RTBASE 0x9e00 104 #define VORTEX_MIXER_RTBASE 0x9e00 106 #define MIXER_RTBASE_SIZE 0x26 105 #define MIXER_RTBASE_SIZE 0x26 107 #define VORTEX_MIX_ENIN 0x9a00 /* Input enabl 106 #define VORTEX_MIX_ENIN 0x9a00 /* Input enable bits. 4 bits wide. */ 108 #define VORTEX_MIX_SMP 0x9c00 107 #define VORTEX_MIX_SMP 0x9c00 109 108 110 /* MIX */ 109 /* MIX */ 111 #define VORTEX_MIX_INVOL_A 0x9000 /* in? 110 #define VORTEX_MIX_INVOL_A 0x9000 /* in? */ 112 #define VORTEX_MIX_INVOL_B 0x8000 /* out 111 #define VORTEX_MIX_INVOL_B 0x8000 /* out? */ 113 #define VORTEX_MIX_VOL_A 0x9800 112 #define VORTEX_MIX_VOL_A 0x9800 114 #define VORTEX_MIX_VOL_B 0x8800 113 #define VORTEX_MIX_VOL_B 0x8800 115 114 116 #define VOL_MIN 0x80 /* Input volum 115 #define VOL_MIN 0x80 /* Input volume when muted. */ 117 #define VOL_MAX 0x7f /* FIXME: Not 116 #define VOL_MAX 0x7f /* FIXME: Not confirmed! Just guessed. */ 118 117 119 //#define MIX_OUTL 0xe 118 //#define MIX_OUTL 0xe 120 //#define MIX_OUTR 0xf 119 //#define MIX_OUTR 0xf 121 //#define MIX_INL 0xe 120 //#define MIX_INL 0xe 122 //#define MIX_INR 0xf 121 //#define MIX_INR 0xf 123 #define MIX_DEFIGAIN 0x08 /* 0x8 => 6dB 122 #define MIX_DEFIGAIN 0x08 /* 0x8 => 6dB */ 124 #define MIX_DEFOGAIN 0x08 123 #define MIX_DEFOGAIN 0x08 125 124 126 /* SRC */ 125 /* SRC */ 127 #define VORTEX_SRCBLOCK_SR 0xccc0 126 #define VORTEX_SRCBLOCK_SR 0xccc0 128 #define VORTEX_SRC_CHNBASE 0xcc40 127 #define VORTEX_SRC_CHNBASE 0xcc40 129 #define VORTEX_SRC_RTBASE 0xcc00 128 #define VORTEX_SRC_RTBASE 0xcc00 130 #define VORTEX_SRC_SOURCE 0xccc4 129 #define VORTEX_SRC_SOURCE 0xccc4 131 #define VORTEX_SRC_SOURCESIZE 0xccc8 130 #define VORTEX_SRC_SOURCESIZE 0xccc8 132 #define VORTEX_SRC_U0 0xce00 131 #define VORTEX_SRC_U0 0xce00 133 #define VORTEX_SRC_DRIFT0 0xce80 132 #define VORTEX_SRC_DRIFT0 0xce80 134 #define VORTEX_SRC_DRIFT1 0xcec0 133 #define VORTEX_SRC_DRIFT1 0xcec0 135 #define VORTEX_SRC_U1 0xcf00 134 #define VORTEX_SRC_U1 0xcf00 136 #define VORTEX_SRC_DRIFT2 0xcf40 135 #define VORTEX_SRC_DRIFT2 0xcf40 137 #define VORTEX_SRC_U2 0xcf80 136 #define VORTEX_SRC_U2 0xcf80 138 #define VORTEX_SRC_DATA 0xc800 137 #define VORTEX_SRC_DATA 0xc800 139 #define VORTEX_SRC_DATA0 0xc000 138 #define VORTEX_SRC_DATA0 0xc000 140 #define VORTEX_SRC_CONVRATIO 0xce40 139 #define VORTEX_SRC_CONVRATIO 0xce40 141 //#define SRC_RATIO(x) ((((x<<15)/48000) + 140 //#define SRC_RATIO(x) ((((x<<15)/48000) + 1)/2) /* Playback */ 142 //#define SRC_RATIO2(x) ((((48000<<15)/x) 141 //#define SRC_RATIO2(x) ((((48000<<15)/x) + 1)/2) /* Recording */ 143 142 144 /* FIFO */ 143 /* FIFO */ 145 #define VORTEX_FIFO_ADBCTRL 0xf800 /* Con 144 #define VORTEX_FIFO_ADBCTRL 0xf800 /* Control bits. */ 146 #define VORTEX_FIFO_WTCTRL 0xf840 145 #define VORTEX_FIFO_WTCTRL 0xf840 147 #define FIFO_RDONLY 0x00000001 146 #define FIFO_RDONLY 0x00000001 148 #define FIFO_CTRL 0x00000002 147 #define FIFO_CTRL 0x00000002 /* Allow ctrl. ? */ 149 #define FIFO_VALID 0x00000010 148 #define FIFO_VALID 0x00000010 150 #define FIFO_EMPTY 0x00000020 149 #define FIFO_EMPTY 0x00000020 151 #define FIFO_U0 0x00001000 150 #define FIFO_U0 0x00001000 /* Unknown. */ 152 #define FIFO_U1 0x00010000 151 #define FIFO_U1 0x00010000 153 #define FIFO_SIZE_BITS 5 152 #define FIFO_SIZE_BITS 5 154 #define FIFO_SIZE (1<<FIFO_SIZE_ 153 #define FIFO_SIZE (1<<FIFO_SIZE_BITS) // 0x20 155 #define FIFO_MASK (FIFO_SIZE-1) 154 #define FIFO_MASK (FIFO_SIZE-1) //0x1f /* at shift left 0xc */ 156 #define VORTEX_FIFO_ADBDATA 0xe000 155 #define VORTEX_FIFO_ADBDATA 0xe000 157 #define VORTEX_FIFO_WTDATA 0xe800 156 #define VORTEX_FIFO_WTDATA 0xe800 158 157 159 /* CODEC */ 158 /* CODEC */ 160 #define VORTEX_CODEC_CTRL 0x11984 159 #define VORTEX_CODEC_CTRL 0x11984 161 #define VORTEX_CODEC_EN 0x11990 160 #define VORTEX_CODEC_EN 0x11990 162 #define EN_CODEC 0x00000300 161 #define EN_CODEC 0x00000300 163 #define EN_SPORT 0x00030000 162 #define EN_SPORT 0x00030000 164 #define EN_SPDIF 0x000c0000 163 #define EN_SPDIF 0x000c0000 165 #define VORTEX_CODEC_CHN 0x11880 164 #define VORTEX_CODEC_CHN 0x11880 166 #define VORTEX_CODEC_IO 0x11988 165 #define VORTEX_CODEC_IO 0x11988 167 166 168 #define VORTEX_SPDIF_FLAGS 0x1005 167 #define VORTEX_SPDIF_FLAGS 0x1005c /* FIXME */ 169 #define VORTEX_SPDIF_CFG0 0x119D 168 #define VORTEX_SPDIF_CFG0 0x119D0 170 #define VORTEX_SPDIF_CFG1 0x119D 169 #define VORTEX_SPDIF_CFG1 0x119D4 171 #define VORTEX_SPDIF_SMPRATE 0x11994 170 #define VORTEX_SPDIF_SMPRATE 0x11994 172 171 173 /* Sample timer */ 172 /* Sample timer */ 174 #define VORTEX_SMP_TIME 0x11998 173 #define VORTEX_SMP_TIME 0x11998 175 174 176 /* IRQ */ 175 /* IRQ */ 177 #define VORTEX_IRQ_SOURCE 0x12800 /* Int 176 #define VORTEX_IRQ_SOURCE 0x12800 /* Interrupt source flags. */ 178 #define VORTEX_IRQ_CTRL 0x12804 /* Interrupt s 177 #define VORTEX_IRQ_CTRL 0x12804 /* Interrupt source mask. */ 179 178 180 #define VORTEX_STAT 0x12808 /* ?? 179 #define VORTEX_STAT 0x12808 /* ?? */ 181 180 182 #define VORTEX_CTRL 0x1280c 181 #define VORTEX_CTRL 0x1280c 183 #define CTRL_MIDI_EN 0x00000001 182 #define CTRL_MIDI_EN 0x00000001 184 #define CTRL_MIDI_PORT 0x00000060 183 #define CTRL_MIDI_PORT 0x00000060 185 #define CTRL_GAME_EN 0x00000008 184 #define CTRL_GAME_EN 0x00000008 186 #define CTRL_GAME_PORT 0x00000e00 185 #define CTRL_GAME_PORT 0x00000e00 187 #define CTRL_IRQ_ENABLE 0x4000 186 #define CTRL_IRQ_ENABLE 0x4000 188 187 189 /* write: Timer period config / read: TIMER IR 188 /* write: Timer period config / read: TIMER IRQ ack. */ 190 #define VORTEX_IRQ_STAT 0x1199c 189 #define VORTEX_IRQ_STAT 0x1199c 191 190 192 /* DMA */ 191 /* DMA */ 193 #define VORTEX_DMA_BUFFER 0x10200 192 #define VORTEX_DMA_BUFFER 0x10200 194 #define VORTEX_ENGINE_CTRL 0x1060c 193 #define VORTEX_ENGINE_CTRL 0x1060c 195 #define ENGINE_INIT 0x0L 194 #define ENGINE_INIT 0x0L 196 195 197 /* MIDI *//* GAME. */ 196 /* MIDI *//* GAME. */ 198 #define VORTEX_MIDI_DATA 0x11000 197 #define VORTEX_MIDI_DATA 0x11000 199 #define VORTEX_MIDI_CMD 0x11004 /* Write comma 198 #define VORTEX_MIDI_CMD 0x11004 /* Write command / Read status */ 200 #define VORTEX_GAME_LEGACY 0x11008 199 #define VORTEX_GAME_LEGACY 0x11008 201 #define VORTEX_CTRL2 0x1100c 200 #define VORTEX_CTRL2 0x1100c 202 #define CTRL2_GAME_ADCMODE 0x40 201 #define CTRL2_GAME_ADCMODE 0x40 203 #define VORTEX_GAME_AXIS 0x11010 202 #define VORTEX_GAME_AXIS 0x11010 204 #define AXIS_SIZE 4 203 #define AXIS_SIZE 4 205 #define AXIS_RANGE 0x1fff 204 #define AXIS_RANGE 0x1fff 206 205
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