1 // SPDX-License-Identifier: GPL-2.0-or-later <<
2 /* 1 /*
>> 2 * This program is free software; you can redistribute it and/or modify
>> 3 * it under the terms of the GNU General Public License as published by
>> 4 * the Free Software Foundation; either version 2 of the License, or
>> 5 * (at your option) any later version.
>> 6 *
>> 7 * This program is distributed in the hope that it will be useful,
>> 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 10 * GNU Library General Public License for more details.
>> 11 *
>> 12 * You should have received a copy of the GNU General Public License
>> 13 * along with this program; if not, write to the Free Software
>> 14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
3 */ 15 */
4 16
5 /* 17 /*
6 * Someday its supposed to make use of the WT 18 * Someday its supposed to make use of the WT DMA engine
7 * for a Wavetable synthesizer. 19 * for a Wavetable synthesizer.
8 */ 20 */
9 21
10 #include "au88x0.h" 22 #include "au88x0.h"
11 #include "au88x0_wt.h" 23 #include "au88x0_wt.h"
12 24
13 static void vortex_fifo_setwtvalid(vortex_t * 25 static void vortex_fifo_setwtvalid(vortex_t * vortex, int fifo, int en);
14 static void vortex_connection_adb_mixin(vortex 26 static void vortex_connection_adb_mixin(vortex_t * vortex, int en,
15 unsign 27 unsigned char channel,
16 unsign 28 unsigned char source,
17 unsign 29 unsigned char mixin);
18 static void vortex_connection_mixin_mix(vortex 30 static void vortex_connection_mixin_mix(vortex_t * vortex, int en,
19 unsign 31 unsigned char mixin,
20 unsign 32 unsigned char mix, int a);
21 static void vortex_fifo_wtinitialize(vortex_t 33 static void vortex_fifo_wtinitialize(vortex_t * vortex, int fifo, int j);
22 static int vortex_wt_SetReg(vortex_t * vortex, 34 static int vortex_wt_SetReg(vortex_t * vortex, unsigned char reg, int wt,
23 u32 val); 35 u32 val);
24 36
25 /* WT */ 37 /* WT */
26 38
27 /* Put 2 WT channels together for one stereo i 39 /* Put 2 WT channels together for one stereo interlaced channel. */
28 static void vortex_wt_setstereo(vortex_t * vor 40 static void vortex_wt_setstereo(vortex_t * vortex, u32 wt, u32 stereo)
29 { 41 {
30 int temp; 42 int temp;
31 43
32 //temp = hwread(vortex->mmio, 0x80 + ( 44 //temp = hwread(vortex->mmio, 0x80 + ((wt >> 0x5)<< 0xf) + (((wt & 0x1f) >> 1) << 2));
33 temp = hwread(vortex->mmio, WT_STEREO( 45 temp = hwread(vortex->mmio, WT_STEREO(wt));
34 temp = (temp & 0xfe) | (stereo & 1); 46 temp = (temp & 0xfe) | (stereo & 1);
35 //hwwrite(vortex->mmio, 0x80 + ((wt >> 47 //hwwrite(vortex->mmio, 0x80 + ((wt >> 0x5)<< 0xf) + (((wt & 0x1f) >> 1) << 2), temp);
36 hwwrite(vortex->mmio, WT_STEREO(wt), t 48 hwwrite(vortex->mmio, WT_STEREO(wt), temp);
37 } 49 }
38 50
39 /* Join to mixdown route. */ 51 /* Join to mixdown route. */
40 static void vortex_wt_setdsout(vortex_t * vort 52 static void vortex_wt_setdsout(vortex_t * vortex, u32 wt, int en)
41 { 53 {
42 int temp; 54 int temp;
43 55
44 /* There is one DSREG register for eac 56 /* There is one DSREG register for each bank (32 voices each). */
45 temp = hwread(vortex->mmio, WT_DSREG(( 57 temp = hwread(vortex->mmio, WT_DSREG((wt >= 0x20) ? 1 : 0));
46 if (en) 58 if (en)
47 temp |= (1 << (wt & 0x1f)); 59 temp |= (1 << (wt & 0x1f));
48 else 60 else
49 temp &= ~(1 << (wt & 0x1f)); 61 temp &= ~(1 << (wt & 0x1f));
50 hwwrite(vortex->mmio, WT_DSREG((wt >= 62 hwwrite(vortex->mmio, WT_DSREG((wt >= 0x20) ? 1 : 0), temp);
51 } 63 }
52 64
53 /* Setup WT route. */ 65 /* Setup WT route. */
54 static int vortex_wt_allocroute(vortex_t * vor 66 static int vortex_wt_allocroute(vortex_t * vortex, int wt, int nr_ch)
55 { 67 {
56 wt_voice_t *voice = &(vortex->wt_voice 68 wt_voice_t *voice = &(vortex->wt_voice[wt]);
57 int temp; 69 int temp;
58 70
59 //FIXME: WT audio routing. 71 //FIXME: WT audio routing.
60 if (nr_ch) { 72 if (nr_ch) {
61 vortex_fifo_wtinitialize(vorte 73 vortex_fifo_wtinitialize(vortex, wt, 1);
62 vortex_fifo_setwtvalid(vortex, 74 vortex_fifo_setwtvalid(vortex, wt, 1);
63 vortex_wt_setstereo(vortex, wt 75 vortex_wt_setstereo(vortex, wt, nr_ch - 1);
64 } else 76 } else
65 vortex_fifo_setwtvalid(vortex, 77 vortex_fifo_setwtvalid(vortex, wt, 0);
66 78
67 /* Set mixdown mode. */ 79 /* Set mixdown mode. */
68 vortex_wt_setdsout(vortex, wt, 1); 80 vortex_wt_setdsout(vortex, wt, 1);
69 /* Set other parameter registers. */ 81 /* Set other parameter registers. */
70 hwwrite(vortex->mmio, WT_SRAMP(0), 0x8 82 hwwrite(vortex->mmio, WT_SRAMP(0), 0x880000);
71 //hwwrite(vortex->mmio, WT_GMODE(0), 0 83 //hwwrite(vortex->mmio, WT_GMODE(0), 0xffffffff);
72 #ifdef CHIP_AU8830 84 #ifdef CHIP_AU8830
73 hwwrite(vortex->mmio, WT_SRAMP(1), 0x8 85 hwwrite(vortex->mmio, WT_SRAMP(1), 0x880000);
74 //hwwrite(vortex->mmio, WT_GMODE(1), 0 86 //hwwrite(vortex->mmio, WT_GMODE(1), 0xffffffff);
75 #endif 87 #endif
76 hwwrite(vortex->mmio, WT_PARM(wt, 0), 88 hwwrite(vortex->mmio, WT_PARM(wt, 0), 0);
77 hwwrite(vortex->mmio, WT_PARM(wt, 1), 89 hwwrite(vortex->mmio, WT_PARM(wt, 1), 0);
78 hwwrite(vortex->mmio, WT_PARM(wt, 2), 90 hwwrite(vortex->mmio, WT_PARM(wt, 2), 0);
79 91
80 temp = hwread(vortex->mmio, WT_PARM(wt 92 temp = hwread(vortex->mmio, WT_PARM(wt, 3));
81 dev_dbg(vortex->card->dev, "WT PARM3: 93 dev_dbg(vortex->card->dev, "WT PARM3: %x\n", temp);
82 //hwwrite(vortex->mmio, WT_PARM(wt, 3) 94 //hwwrite(vortex->mmio, WT_PARM(wt, 3), temp);
83 95
84 hwwrite(vortex->mmio, WT_DELAY(wt, 0), 96 hwwrite(vortex->mmio, WT_DELAY(wt, 0), 0);
85 hwwrite(vortex->mmio, WT_DELAY(wt, 1), 97 hwwrite(vortex->mmio, WT_DELAY(wt, 1), 0);
86 hwwrite(vortex->mmio, WT_DELAY(wt, 2), 98 hwwrite(vortex->mmio, WT_DELAY(wt, 2), 0);
87 hwwrite(vortex->mmio, WT_DELAY(wt, 3), 99 hwwrite(vortex->mmio, WT_DELAY(wt, 3), 0);
88 100
89 dev_dbg(vortex->card->dev, "WT GMODE: 101 dev_dbg(vortex->card->dev, "WT GMODE: %x\n",
90 hwread(vortex->mmio, WT_GMODE( 102 hwread(vortex->mmio, WT_GMODE(wt)));
91 103
92 hwwrite(vortex->mmio, WT_PARM(wt, 2), 104 hwwrite(vortex->mmio, WT_PARM(wt, 2), 0xffffffff);
93 hwwrite(vortex->mmio, WT_PARM(wt, 3), 105 hwwrite(vortex->mmio, WT_PARM(wt, 3), 0xcff1c810);
94 106
95 voice->parm0 = voice->parm1 = 0xcfb23e 107 voice->parm0 = voice->parm1 = 0xcfb23e2f;
96 hwwrite(vortex->mmio, WT_PARM(wt, 0), 108 hwwrite(vortex->mmio, WT_PARM(wt, 0), voice->parm0);
97 hwwrite(vortex->mmio, WT_PARM(wt, 1), 109 hwwrite(vortex->mmio, WT_PARM(wt, 1), voice->parm1);
98 dev_dbg(vortex->card->dev, "WT GMODE 2 110 dev_dbg(vortex->card->dev, "WT GMODE 2 : %x\n",
99 hwread(vortex->mmio, WT_GMODE( 111 hwread(vortex->mmio, WT_GMODE(wt)));
100 return 0; 112 return 0;
101 } 113 }
102 114
103 115
104 static void vortex_wt_connect(vortex_t * vorte 116 static void vortex_wt_connect(vortex_t * vortex, int en)
105 { 117 {
106 int i, ii, mix; 118 int i, ii, mix;
107 119
108 #define NR_WTROUTES 6 120 #define NR_WTROUTES 6
109 #ifdef CHIP_AU8830 121 #ifdef CHIP_AU8830
110 #define NR_WTBLOCKS 2 122 #define NR_WTBLOCKS 2
111 #else 123 #else
112 #define NR_WTBLOCKS 1 124 #define NR_WTBLOCKS 1
113 #endif 125 #endif
114 126
115 for (i = 0; i < NR_WTBLOCKS; i++) { 127 for (i = 0; i < NR_WTBLOCKS; i++) {
116 for (ii = 0; ii < NR_WTROUTES; 128 for (ii = 0; ii < NR_WTROUTES; ii++) {
117 mix = 129 mix =
118 vortex_adb_checkin 130 vortex_adb_checkinout(vortex,
119 131 vortex->fixed_res, en,
120 132 VORTEX_RESOURCE_MIXIN);
121 vortex->mixwt[(i * NR_ 133 vortex->mixwt[(i * NR_WTROUTES) + ii] = mix;
122 134
123 vortex_route(vortex, e 135 vortex_route(vortex, en, 0x11,
124 ADB_WTOUT 136 ADB_WTOUT(i, ii + 0x20), ADB_MIXIN(mix));
125 137
126 vortex_connection_mixi 138 vortex_connection_mixin_mix(vortex, en, mix,
127 139 vortex->mixplayb[ii % 2], 0);
128 if (VORTEX_IS_QUAD(vor 140 if (VORTEX_IS_QUAD(vortex))
129 vortex_connect 141 vortex_connection_mixin_mix(vortex, en,
130 142 mix,
131 143 vortex->mixplayb[2 +
132 144 (ii % 2)], 0);
133 } 145 }
134 } 146 }
135 for (i = 0; i < NR_WT; i++) { 147 for (i = 0; i < NR_WT; i++) {
136 hwwrite(vortex->mmio, WT_RUN(i 148 hwwrite(vortex->mmio, WT_RUN(i), 1);
137 } 149 }
138 } 150 }
139 151
140 /* Read WT Register */ 152 /* Read WT Register */
141 #if 0 153 #if 0
142 static int vortex_wt_GetReg(vortex_t * vortex, 154 static int vortex_wt_GetReg(vortex_t * vortex, char reg, int wt)
143 { 155 {
144 //int eax, esi; 156 //int eax, esi;
145 157
146 if (reg == 4) { 158 if (reg == 4) {
147 return hwread(vortex->mmio, WT 159 return hwread(vortex->mmio, WT_PARM(wt, 3));
148 } 160 }
149 if (reg == 7) { 161 if (reg == 7) {
150 return hwread(vortex->mmio, WT 162 return hwread(vortex->mmio, WT_GMODE(wt));
151 } 163 }
152 164
153 return 0; 165 return 0;
154 } 166 }
155 167
156 /* WT hardware abstraction layer generic regis 168 /* WT hardware abstraction layer generic register interface. */
157 static int 169 static int
158 vortex_wt_SetReg2(vortex_t * vortex, unsigned 170 vortex_wt_SetReg2(vortex_t * vortex, unsigned char reg, int wt,
159 u16 val) 171 u16 val)
160 { 172 {
161 /* 173 /*
162 int eax, edx; 174 int eax, edx;
163 175
164 if (wt >= NR_WT) // 0x40 -> NR_WT 176 if (wt >= NR_WT) // 0x40 -> NR_WT
165 return 0; 177 return 0;
166 178
167 if ((reg - 0x20) > 0) { 179 if ((reg - 0x20) > 0) {
168 if ((reg - 0x21) != 0) 180 if ((reg - 0x21) != 0)
169 return 0; 181 return 0;
170 eax = ((((b & 0xff) << 0xb) + (edx 182 eax = ((((b & 0xff) << 0xb) + (edx & 0xff)) << 4) + 0x208; // param 2
171 } else { 183 } else {
172 eax = ((((b & 0xff) << 0xb) + (edx 184 eax = ((((b & 0xff) << 0xb) + (edx & 0xff)) << 4) + 0x20a; // param 3
173 } 185 }
174 hwwrite(vortex->mmio, eax, c); 186 hwwrite(vortex->mmio, eax, c);
175 */ 187 */
176 return 1; 188 return 1;
177 } 189 }
178 190
179 /*public: static void __thiscall CWTHal::SetRe 191 /*public: static void __thiscall CWTHal::SetReg(unsigned char,int,unsigned long) */
180 #endif 192 #endif
181 static int 193 static int
182 vortex_wt_SetReg(vortex_t * vortex, unsigned c 194 vortex_wt_SetReg(vortex_t * vortex, unsigned char reg, int wt,
183 u32 val) 195 u32 val)
184 { 196 {
185 int ecx; 197 int ecx;
186 198
187 if ((reg == 5) || ((reg >= 7) && (reg 199 if ((reg == 5) || ((reg >= 7) && (reg <= 10)) || (reg == 0xc)) {
188 if (wt >= (NR_WT / NR_WT_PB)) 200 if (wt >= (NR_WT / NR_WT_PB)) {
189 dev_warn(vortex->card- 201 dev_warn(vortex->card->dev,
190 "WT SetReg: b 202 "WT SetReg: bank out of range. reg=0x%x, wt=%d\n",
191 reg, wt); 203 reg, wt);
192 return 0; 204 return 0;
193 } 205 }
194 } else { 206 } else {
195 if (wt >= NR_WT) { 207 if (wt >= NR_WT) {
196 dev_err(vortex->card-> 208 dev_err(vortex->card->dev,
197 "WT SetReg: vo 209 "WT SetReg: voice out of range\n");
198 return 0; 210 return 0;
199 } 211 }
200 } 212 }
201 if (reg > 0xc) 213 if (reg > 0xc)
202 return 0; 214 return 0;
203 215
204 switch (reg) { 216 switch (reg) {
205 /* Voice specific parameters * 217 /* Voice specific parameters */
206 case 0: /* running */ 218 case 0: /* running */
207 /* 219 /*
208 pr_debug( "vortex: WT SetReg(0 220 pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n",
209 WT_RUN(wt), (int)val); 221 WT_RUN(wt), (int)val);
210 */ 222 */
211 hwwrite(vortex->mmio, WT_RUN(w 223 hwwrite(vortex->mmio, WT_RUN(wt), val);
212 return 0xc; 224 return 0xc;
213 case 1: /* param 0 */ 225 case 1: /* param 0 */
214 /* 226 /*
215 pr_debug( "vortex: WT SetReg(0 227 pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n",
216 WT_PARM(wt,0), (int)val 228 WT_PARM(wt,0), (int)val);
217 */ 229 */
218 hwwrite(vortex->mmio, WT_PARM( 230 hwwrite(vortex->mmio, WT_PARM(wt, 0), val);
219 return 0xc; 231 return 0xc;
220 case 2: /* param 1 */ 232 case 2: /* param 1 */
221 /* 233 /*
222 pr_debug( "vortex: WT SetReg(0 234 pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n",
223 WT_PARM(wt,1), (int)val 235 WT_PARM(wt,1), (int)val);
224 */ 236 */
225 hwwrite(vortex->mmio, WT_PARM( 237 hwwrite(vortex->mmio, WT_PARM(wt, 1), val);
226 return 0xc; 238 return 0xc;
227 case 3: /* param 2 */ 239 case 3: /* param 2 */
228 /* 240 /*
229 pr_debug( "vortex: WT SetReg(0 241 pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n",
230 WT_PARM(wt,2), (int)val 242 WT_PARM(wt,2), (int)val);
231 */ 243 */
232 hwwrite(vortex->mmio, WT_PARM( 244 hwwrite(vortex->mmio, WT_PARM(wt, 2), val);
233 return 0xc; 245 return 0xc;
234 case 4: /* param 3 */ 246 case 4: /* param 3 */
235 /* 247 /*
236 pr_debug( "vortex: WT SetReg(0 248 pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n",
237 WT_PARM(wt,3), (int)val 249 WT_PARM(wt,3), (int)val);
238 */ 250 */
239 hwwrite(vortex->mmio, WT_PARM( 251 hwwrite(vortex->mmio, WT_PARM(wt, 3), val);
240 return 0xc; 252 return 0xc;
241 case 6: /* mute */ 253 case 6: /* mute */
242 /* 254 /*
243 pr_debug( "vortex: WT SetReg(0 255 pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n",
244 WT_MUTE(wt), (int)val); 256 WT_MUTE(wt), (int)val);
245 */ 257 */
246 hwwrite(vortex->mmio, WT_MUTE( 258 hwwrite(vortex->mmio, WT_MUTE(wt), val);
247 return 0xc; 259 return 0xc;
248 case 0xb: 260 case 0xb:
249 /* delay */ 261 /* delay */
250 /* 262 /*
251 pr_debug( "vortex: WT SetReg(0 263 pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n",
252 WT_DELAY(wt,0), (int)va 264 WT_DELAY(wt,0), (int)val);
253 */ 265 */
254 hwwrite(vortex->mmio, WT_DELAY 266 hwwrite(vortex->mmio, WT_DELAY(wt, 3), val);
255 hwwrite(vortex->mmio, WT_DELAY 267 hwwrite(vortex->mmio, WT_DELAY(wt, 2), val);
256 hwwrite(vortex->mmio, WT_DELAY 268 hwwrite(vortex->mmio, WT_DELAY(wt, 1), val);
257 hwwrite(vortex->mmio, WT_DELAY 269 hwwrite(vortex->mmio, WT_DELAY(wt, 0), val);
258 return 0xc; 270 return 0xc;
259 /* Global WT block parameters 271 /* Global WT block parameters */
260 case 5: /* sramp */ 272 case 5: /* sramp */
261 ecx = WT_SRAMP(wt); 273 ecx = WT_SRAMP(wt);
262 break; 274 break;
263 case 8: /* aramp */ 275 case 8: /* aramp */
264 ecx = WT_ARAMP(wt); 276 ecx = WT_ARAMP(wt);
265 break; 277 break;
266 case 9: /* mramp */ 278 case 9: /* mramp */
267 ecx = WT_MRAMP(wt); 279 ecx = WT_MRAMP(wt);
268 break; 280 break;
269 case 0xa: /* ctrl */ 281 case 0xa: /* ctrl */
270 ecx = WT_CTRL(wt); 282 ecx = WT_CTRL(wt);
271 break; 283 break;
272 case 0xc: /* ds_reg */ 284 case 0xc: /* ds_reg */
273 ecx = WT_DSREG(wt); 285 ecx = WT_DSREG(wt);
274 break; 286 break;
275 default: 287 default:
276 return 0; 288 return 0;
277 } 289 }
278 /* 290 /*
279 pr_debug( "vortex: WT SetReg(0x%x) = 0 291 pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n", ecx, (int)val);
280 */ 292 */
281 hwwrite(vortex->mmio, ecx, val); 293 hwwrite(vortex->mmio, ecx, val);
282 return 1; 294 return 1;
283 } 295 }
284 296
285 static void vortex_wt_init(vortex_t * vortex) 297 static void vortex_wt_init(vortex_t * vortex)
286 { 298 {
287 u32 var4, var8, varc, var10 = 0, edi; 299 u32 var4, var8, varc, var10 = 0, edi;
288 300
289 var10 &= 0xFFFFFFE3; 301 var10 &= 0xFFFFFFE3;
290 var10 |= 0x22; 302 var10 |= 0x22;
291 var10 &= 0xFFFFFEBF; 303 var10 &= 0xFFFFFEBF;
292 var10 |= 0x80; 304 var10 |= 0x80;
293 var10 |= 0x200; 305 var10 |= 0x200;
294 var10 &= 0xfffffffe; 306 var10 &= 0xfffffffe;
295 var10 &= 0xfffffbff; 307 var10 &= 0xfffffbff;
296 var10 |= 0x1800; 308 var10 |= 0x1800;
297 // var10 = 0x1AA2 309 // var10 = 0x1AA2
298 var4 = 0x10000000; 310 var4 = 0x10000000;
299 varc = 0x00830000; 311 varc = 0x00830000;
300 var8 = 0x00830000; 312 var8 = 0x00830000;
301 313
302 /* Init Bank registers. */ 314 /* Init Bank registers. */
303 for (edi = 0; edi < (NR_WT / NR_WT_PB) 315 for (edi = 0; edi < (NR_WT / NR_WT_PB); edi++) {
304 vortex_wt_SetReg(vortex, 0xc, 316 vortex_wt_SetReg(vortex, 0xc, edi, 0); /* ds_reg */
305 vortex_wt_SetReg(vortex, 0xa, 317 vortex_wt_SetReg(vortex, 0xa, edi, var10); /* ctrl */
306 vortex_wt_SetReg(vortex, 0x9, 318 vortex_wt_SetReg(vortex, 0x9, edi, var4); /* mramp */
307 vortex_wt_SetReg(vortex, 0x8, 319 vortex_wt_SetReg(vortex, 0x8, edi, varc); /* aramp */
308 vortex_wt_SetReg(vortex, 0x5, 320 vortex_wt_SetReg(vortex, 0x5, edi, var8); /* sramp */
309 } 321 }
310 /* Init Voice registers. */ 322 /* Init Voice registers. */
311 for (edi = 0; edi < NR_WT; edi++) { 323 for (edi = 0; edi < NR_WT; edi++) {
312 vortex_wt_SetReg(vortex, 0x4, 324 vortex_wt_SetReg(vortex, 0x4, edi, 0); /* param 3 0x20c */
313 vortex_wt_SetReg(vortex, 0x3, 325 vortex_wt_SetReg(vortex, 0x3, edi, 0); /* param 2 0x208 */
314 vortex_wt_SetReg(vortex, 0x2, 326 vortex_wt_SetReg(vortex, 0x2, edi, 0); /* param 1 0x204 */
315 vortex_wt_SetReg(vortex, 0x1, 327 vortex_wt_SetReg(vortex, 0x1, edi, 0); /* param 0 0x200 */
316 vortex_wt_SetReg(vortex, 0xb, 328 vortex_wt_SetReg(vortex, 0xb, edi, 0); /* delay 0x400 - 0x40c */
317 } 329 }
318 var10 |= 1; 330 var10 |= 1;
319 for (edi = 0; edi < (NR_WT / NR_WT_PB) 331 for (edi = 0; edi < (NR_WT / NR_WT_PB); edi++)
320 vortex_wt_SetReg(vortex, 0xa, 332 vortex_wt_SetReg(vortex, 0xa, edi, var10); /* ctrl */
321 } 333 }
322 334
323 /* Extract of CAdbTopology::SetVolume(struct _ 335 /* Extract of CAdbTopology::SetVolume(struct _ASPVOLUME *) */
324 #if 0 336 #if 0
325 static void vortex_wt_SetVolume(vortex_t * vor 337 static void vortex_wt_SetVolume(vortex_t * vortex, int wt, int vol[])
326 { 338 {
327 wt_voice_t *voice = &(vortex->wt_voice 339 wt_voice_t *voice = &(vortex->wt_voice[wt]);
328 int ecx = vol[1], eax = vol[0]; 340 int ecx = vol[1], eax = vol[0];
329 341
330 /* This is pure guess */ 342 /* This is pure guess */
331 voice->parm0 &= 0xff00ffff; 343 voice->parm0 &= 0xff00ffff;
332 voice->parm0 |= (vol[0] & 0xff) << 0x1 344 voice->parm0 |= (vol[0] & 0xff) << 0x10;
333 voice->parm1 &= 0xff00ffff; 345 voice->parm1 &= 0xff00ffff;
334 voice->parm1 |= (vol[1] & 0xff) << 0x1 346 voice->parm1 |= (vol[1] & 0xff) << 0x10;
335 347
336 /* This is real */ 348 /* This is real */
337 hwwrite(vortex, WT_PARM(wt, 0), voice- 349 hwwrite(vortex, WT_PARM(wt, 0), voice->parm0);
338 hwwrite(vortex, WT_PARM(wt, 1), voice- 350 hwwrite(vortex, WT_PARM(wt, 1), voice->parm0);
339 351
340 if (voice->this_1D0 & 4) { 352 if (voice->this_1D0 & 4) {
341 eax >>= 8; 353 eax >>= 8;
342 ecx = eax; 354 ecx = eax;
343 if (ecx < 0x80) 355 if (ecx < 0x80)
344 ecx = 0x7f; 356 ecx = 0x7f;
345 voice->parm3 &= 0xFFFFC07F; 357 voice->parm3 &= 0xFFFFC07F;
346 voice->parm3 |= (ecx & 0x7f) < 358 voice->parm3 |= (ecx & 0x7f) << 7;
347 voice->parm3 &= 0xFFFFFF80; 359 voice->parm3 &= 0xFFFFFF80;
348 voice->parm3 |= (eax & 0x7f); 360 voice->parm3 |= (eax & 0x7f);
349 } else { 361 } else {
350 voice->parm3 &= 0xFFE03FFF; 362 voice->parm3 &= 0xFFE03FFF;
351 voice->parm3 |= (eax & 0xFE00) 363 voice->parm3 |= (eax & 0xFE00) << 5;
352 } 364 }
353 365
354 hwwrite(vortex, WT_PARM(wt, 3), voice- 366 hwwrite(vortex, WT_PARM(wt, 3), voice->parm3);
355 } 367 }
356 368
357 /* Extract of CAdbTopology::SetFrequency(unsig 369 /* Extract of CAdbTopology::SetFrequency(unsigned long arg_0) */
358 static void vortex_wt_SetFrequency(vortex_t * 370 static void vortex_wt_SetFrequency(vortex_t * vortex, int wt, unsigned int sr)
359 { 371 {
360 wt_voice_t *voice = &(vortex->wt_voice 372 wt_voice_t *voice = &(vortex->wt_voice[wt]);
361 u32 eax, edx; 373 u32 eax, edx;
362 374
363 //FIXME: 64 bit operation. 375 //FIXME: 64 bit operation.
364 eax = ((sr << 0xf) * 0x57619F1) & 0xff 376 eax = ((sr << 0xf) * 0x57619F1) & 0xffffffff;
365 edx = (((sr << 0xf) * 0x57619F1)) >> 0 377 edx = (((sr << 0xf) * 0x57619F1)) >> 0x20;
366 378
367 edx >>= 0xa; 379 edx >>= 0xa;
368 edx <<= 1; 380 edx <<= 1;
369 if (edx) { 381 if (edx) {
370 if (edx & 0x0FFF80000) 382 if (edx & 0x0FFF80000)
371 eax = 0x7fff; 383 eax = 0x7fff;
372 else { 384 else {
373 edx <<= 0xd; 385 edx <<= 0xd;
374 eax = 7; 386 eax = 7;
375 while ((edx & 0x800000 387 while ((edx & 0x80000000) == 0) {
376 edx <<= 1; 388 edx <<= 1;
377 eax--; 389 eax--;
378 if (eax == 0) 390 if (eax == 0)
379 break; 391 break;
380 } 392 }
381 if (eax) 393 if (eax)
382 edx <<= 1; 394 edx <<= 1;
383 eax <<= 0xc; 395 eax <<= 0xc;
384 edx >>= 0x14; 396 edx >>= 0x14;
385 eax |= edx; 397 eax |= edx;
386 } 398 }
387 } else 399 } else
388 eax = 0; 400 eax = 0;
389 voice->parm0 &= 0xffff0001; 401 voice->parm0 &= 0xffff0001;
390 voice->parm0 |= (eax & 0x7fff) << 1; 402 voice->parm0 |= (eax & 0x7fff) << 1;
391 voice->parm1 = voice->parm0 | 1; 403 voice->parm1 = voice->parm0 | 1;
392 // Wt: this_1D4 404 // Wt: this_1D4
393 //AuWt::WriteReg((ulong)(this_1DC<<4)+ 405 //AuWt::WriteReg((ulong)(this_1DC<<4)+0x200, (ulong)this_1E4);
394 //AuWt::WriteReg((ulong)(this_1DC<<4)+ 406 //AuWt::WriteReg((ulong)(this_1DC<<4)+0x204, (ulong)this_1E8);
395 hwwrite(vortex->mmio, WT_PARM(wt, 0), 407 hwwrite(vortex->mmio, WT_PARM(wt, 0), voice->parm0);
396 hwwrite(vortex->mmio, WT_PARM(wt, 1), 408 hwwrite(vortex->mmio, WT_PARM(wt, 1), voice->parm1);
397 } 409 }
398 #endif 410 #endif
399 411
400 /* End of File */ 412 /* End of File */
401 413
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