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TOMOYO Linux Cross Reference
Linux/sound/pci/au88x0/au88x0_synth.c

Version: ~ [ linux-6.12-rc7 ] ~ [ linux-6.11.7 ] ~ [ linux-6.10.14 ] ~ [ linux-6.9.12 ] ~ [ linux-6.8.12 ] ~ [ linux-6.7.12 ] ~ [ linux-6.6.60 ] ~ [ linux-6.5.13 ] ~ [ linux-6.4.16 ] ~ [ linux-6.3.13 ] ~ [ linux-6.2.16 ] ~ [ linux-6.1.116 ] ~ [ linux-6.0.19 ] ~ [ linux-5.19.17 ] ~ [ linux-5.18.19 ] ~ [ linux-5.17.15 ] ~ [ linux-5.16.20 ] ~ [ linux-5.15.171 ] ~ [ linux-5.14.21 ] ~ [ linux-5.13.19 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.229 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.285 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.323 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.336 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.337 ] ~ [ linux-4.4.302 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.12 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

Diff markup

Differences between /sound/pci/au88x0/au88x0_synth.c (Version linux-6.12-rc7) and /sound/pci/au88x0/au88x0_synth.c (Version linux-6.7.12)


  1 // SPDX-License-Identifier: GPL-2.0-or-later        1 // SPDX-License-Identifier: GPL-2.0-or-later
  2 /*                                                  2 /*
  3  */                                                 3  */
  4                                                     4 
  5 /*                                                  5 /*
  6  * Someday its supposed to make use of the WT       6  * Someday its supposed to make use of the WT DMA engine
  7  * for a Wavetable synthesizer.                     7  * for a Wavetable synthesizer.
  8  */                                                 8  */
  9                                                     9 
 10 #include "au88x0.h"                                10 #include "au88x0.h"
 11 #include "au88x0_wt.h"                             11 #include "au88x0_wt.h"
 12                                                    12 
 13 static void vortex_fifo_setwtvalid(vortex_t *      13 static void vortex_fifo_setwtvalid(vortex_t * vortex, int fifo, int en);
 14 static void vortex_connection_adb_mixin(vortex     14 static void vortex_connection_adb_mixin(vortex_t * vortex, int en,
 15                                         unsign     15                                         unsigned char channel,
 16                                         unsign     16                                         unsigned char source,
 17                                         unsign     17                                         unsigned char mixin);
 18 static void vortex_connection_mixin_mix(vortex     18 static void vortex_connection_mixin_mix(vortex_t * vortex, int en,
 19                                         unsign     19                                         unsigned char mixin,
 20                                         unsign     20                                         unsigned char mix, int a);
 21 static void vortex_fifo_wtinitialize(vortex_t      21 static void vortex_fifo_wtinitialize(vortex_t * vortex, int fifo, int j);
 22 static int vortex_wt_SetReg(vortex_t * vortex,     22 static int vortex_wt_SetReg(vortex_t * vortex, unsigned char reg, int wt,
 23                             u32 val);              23                             u32 val);
 24                                                    24 
 25 /* WT */                                           25 /* WT */
 26                                                    26 
 27 /* Put 2 WT channels together for one stereo i     27 /* Put 2 WT channels together for one stereo interlaced channel. */
 28 static void vortex_wt_setstereo(vortex_t * vor     28 static void vortex_wt_setstereo(vortex_t * vortex, u32 wt, u32 stereo)
 29 {                                                  29 {
 30         int temp;                                  30         int temp;
 31                                                    31 
 32         //temp = hwread(vortex->mmio, 0x80 + (     32         //temp = hwread(vortex->mmio, 0x80 + ((wt >> 0x5)<< 0xf) + (((wt & 0x1f) >> 1) << 2));
 33         temp = hwread(vortex->mmio, WT_STEREO(     33         temp = hwread(vortex->mmio, WT_STEREO(wt));
 34         temp = (temp & 0xfe) | (stereo & 1);       34         temp = (temp & 0xfe) | (stereo & 1);
 35         //hwwrite(vortex->mmio, 0x80 + ((wt >>     35         //hwwrite(vortex->mmio, 0x80 + ((wt >> 0x5)<< 0xf) + (((wt & 0x1f) >> 1) << 2), temp);
 36         hwwrite(vortex->mmio, WT_STEREO(wt), t     36         hwwrite(vortex->mmio, WT_STEREO(wt), temp);
 37 }                                                  37 }
 38                                                    38 
 39 /* Join to mixdown route. */                       39 /* Join to mixdown route. */
 40 static void vortex_wt_setdsout(vortex_t * vort     40 static void vortex_wt_setdsout(vortex_t * vortex, u32 wt, int en)
 41 {                                                  41 {
 42         int temp;                                  42         int temp;
 43                                                    43 
 44         /* There is one DSREG register for eac     44         /* There is one DSREG register for each bank (32 voices each). */
 45         temp = hwread(vortex->mmio, WT_DSREG((     45         temp = hwread(vortex->mmio, WT_DSREG((wt >= 0x20) ? 1 : 0));
 46         if (en)                                    46         if (en)
 47                 temp |= (1 << (wt & 0x1f));        47                 temp |= (1 << (wt & 0x1f));
 48         else                                       48         else
 49                 temp &= ~(1 << (wt & 0x1f));       49                 temp &= ~(1 << (wt & 0x1f));
 50         hwwrite(vortex->mmio, WT_DSREG((wt >=      50         hwwrite(vortex->mmio, WT_DSREG((wt >= 0x20) ? 1 : 0), temp);
 51 }                                                  51 }
 52                                                    52 
 53 /* Setup WT route. */                              53 /* Setup WT route. */
 54 static int vortex_wt_allocroute(vortex_t * vor     54 static int vortex_wt_allocroute(vortex_t * vortex, int wt, int nr_ch)
 55 {                                                  55 {
 56         wt_voice_t *voice = &(vortex->wt_voice     56         wt_voice_t *voice = &(vortex->wt_voice[wt]);
 57         int temp;                                  57         int temp;
 58                                                    58 
 59         //FIXME: WT audio routing.                 59         //FIXME: WT audio routing.
 60         if (nr_ch) {                               60         if (nr_ch) {
 61                 vortex_fifo_wtinitialize(vorte     61                 vortex_fifo_wtinitialize(vortex, wt, 1);
 62                 vortex_fifo_setwtvalid(vortex,     62                 vortex_fifo_setwtvalid(vortex, wt, 1);
 63                 vortex_wt_setstereo(vortex, wt     63                 vortex_wt_setstereo(vortex, wt, nr_ch - 1);
 64         } else                                     64         } else
 65                 vortex_fifo_setwtvalid(vortex,     65                 vortex_fifo_setwtvalid(vortex, wt, 0);
 66                                                    66         
 67         /* Set mixdown mode. */                    67         /* Set mixdown mode. */
 68         vortex_wt_setdsout(vortex, wt, 1);         68         vortex_wt_setdsout(vortex, wt, 1);
 69         /* Set other parameter registers. */       69         /* Set other parameter registers. */
 70         hwwrite(vortex->mmio, WT_SRAMP(0), 0x8     70         hwwrite(vortex->mmio, WT_SRAMP(0), 0x880000);
 71         //hwwrite(vortex->mmio, WT_GMODE(0), 0     71         //hwwrite(vortex->mmio, WT_GMODE(0), 0xffffffff);
 72 #ifdef CHIP_AU8830                                 72 #ifdef CHIP_AU8830
 73         hwwrite(vortex->mmio, WT_SRAMP(1), 0x8     73         hwwrite(vortex->mmio, WT_SRAMP(1), 0x880000);
 74         //hwwrite(vortex->mmio, WT_GMODE(1), 0     74         //hwwrite(vortex->mmio, WT_GMODE(1), 0xffffffff);
 75 #endif                                             75 #endif
 76         hwwrite(vortex->mmio, WT_PARM(wt, 0),      76         hwwrite(vortex->mmio, WT_PARM(wt, 0), 0);
 77         hwwrite(vortex->mmio, WT_PARM(wt, 1),      77         hwwrite(vortex->mmio, WT_PARM(wt, 1), 0);
 78         hwwrite(vortex->mmio, WT_PARM(wt, 2),      78         hwwrite(vortex->mmio, WT_PARM(wt, 2), 0);
 79                                                    79 
 80         temp = hwread(vortex->mmio, WT_PARM(wt     80         temp = hwread(vortex->mmio, WT_PARM(wt, 3));
 81         dev_dbg(vortex->card->dev, "WT PARM3:      81         dev_dbg(vortex->card->dev, "WT PARM3: %x\n", temp);
 82         //hwwrite(vortex->mmio, WT_PARM(wt, 3)     82         //hwwrite(vortex->mmio, WT_PARM(wt, 3), temp);
 83                                                    83 
 84         hwwrite(vortex->mmio, WT_DELAY(wt, 0),     84         hwwrite(vortex->mmio, WT_DELAY(wt, 0), 0);
 85         hwwrite(vortex->mmio, WT_DELAY(wt, 1),     85         hwwrite(vortex->mmio, WT_DELAY(wt, 1), 0);
 86         hwwrite(vortex->mmio, WT_DELAY(wt, 2),     86         hwwrite(vortex->mmio, WT_DELAY(wt, 2), 0);
 87         hwwrite(vortex->mmio, WT_DELAY(wt, 3),     87         hwwrite(vortex->mmio, WT_DELAY(wt, 3), 0);
 88                                                    88 
 89         dev_dbg(vortex->card->dev, "WT GMODE:      89         dev_dbg(vortex->card->dev, "WT GMODE: %x\n",
 90                 hwread(vortex->mmio, WT_GMODE(     90                 hwread(vortex->mmio, WT_GMODE(wt)));
 91                                                    91 
 92         hwwrite(vortex->mmio, WT_PARM(wt, 2),      92         hwwrite(vortex->mmio, WT_PARM(wt, 2), 0xffffffff);
 93         hwwrite(vortex->mmio, WT_PARM(wt, 3),      93         hwwrite(vortex->mmio, WT_PARM(wt, 3), 0xcff1c810);
 94                                                    94 
 95         voice->parm0 = voice->parm1 = 0xcfb23e     95         voice->parm0 = voice->parm1 = 0xcfb23e2f;
 96         hwwrite(vortex->mmio, WT_PARM(wt, 0),      96         hwwrite(vortex->mmio, WT_PARM(wt, 0), voice->parm0);
 97         hwwrite(vortex->mmio, WT_PARM(wt, 1),      97         hwwrite(vortex->mmio, WT_PARM(wt, 1), voice->parm1);
 98         dev_dbg(vortex->card->dev, "WT GMODE 2     98         dev_dbg(vortex->card->dev, "WT GMODE 2 : %x\n",
 99                 hwread(vortex->mmio, WT_GMODE(     99                 hwread(vortex->mmio, WT_GMODE(wt)));
100         return 0;                                 100         return 0;
101 }                                                 101 }
102                                                   102 
103                                                   103 
104 static void vortex_wt_connect(vortex_t * vorte    104 static void vortex_wt_connect(vortex_t * vortex, int en)
105 {                                                 105 {
106         int i, ii, mix;                           106         int i, ii, mix;
107                                                   107 
108 #define NR_WTROUTES 6                             108 #define NR_WTROUTES 6
109 #ifdef CHIP_AU8830                                109 #ifdef CHIP_AU8830
110 #define NR_WTBLOCKS 2                             110 #define NR_WTBLOCKS 2
111 #else                                             111 #else
112 #define NR_WTBLOCKS 1                             112 #define NR_WTBLOCKS 1
113 #endif                                            113 #endif
114                                                   114 
115         for (i = 0; i < NR_WTBLOCKS; i++) {       115         for (i = 0; i < NR_WTBLOCKS; i++) {
116                 for (ii = 0; ii < NR_WTROUTES;    116                 for (ii = 0; ii < NR_WTROUTES; ii++) {
117                         mix =                     117                         mix =
118                             vortex_adb_checkin    118                             vortex_adb_checkinout(vortex,
119                                                   119                                                   vortex->fixed_res, en,
120                                                   120                                                   VORTEX_RESOURCE_MIXIN);
121                         vortex->mixwt[(i * NR_    121                         vortex->mixwt[(i * NR_WTROUTES) + ii] = mix;
122                                                   122 
123                         vortex_route(vortex, e    123                         vortex_route(vortex, en, 0x11,
124                                      ADB_WTOUT    124                                      ADB_WTOUT(i, ii + 0x20), ADB_MIXIN(mix));
125                                                   125 
126                         vortex_connection_mixi    126                         vortex_connection_mixin_mix(vortex, en, mix,
127                                                   127                                                     vortex->mixplayb[ii % 2], 0);
128                         if (VORTEX_IS_QUAD(vor    128                         if (VORTEX_IS_QUAD(vortex))
129                                 vortex_connect    129                                 vortex_connection_mixin_mix(vortex, en,
130                                                   130                                                             mix,
131                                                   131                                                             vortex->mixplayb[2 +
132                                                   132                                                                      (ii % 2)], 0);
133                 }                                 133                 }
134         }                                         134         }
135         for (i = 0; i < NR_WT; i++) {             135         for (i = 0; i < NR_WT; i++) {
136                 hwwrite(vortex->mmio, WT_RUN(i    136                 hwwrite(vortex->mmio, WT_RUN(i), 1);
137         }                                         137         }
138 }                                                 138 }
139                                                   139 
140 /* Read WT Register */                            140 /* Read WT Register */
141 #if 0                                             141 #if 0
142 static int vortex_wt_GetReg(vortex_t * vortex,    142 static int vortex_wt_GetReg(vortex_t * vortex, char reg, int wt)
143 {                                                 143 {
144         //int eax, esi;                           144         //int eax, esi;
145                                                   145 
146         if (reg == 4) {                           146         if (reg == 4) {
147                 return hwread(vortex->mmio, WT    147                 return hwread(vortex->mmio, WT_PARM(wt, 3));
148         }                                         148         }
149         if (reg == 7) {                           149         if (reg == 7) {
150                 return hwread(vortex->mmio, WT    150                 return hwread(vortex->mmio, WT_GMODE(wt));
151         }                                         151         }
152                                                   152 
153         return 0;                                 153         return 0;
154 }                                                 154 }
155                                                   155 
156 /* WT hardware abstraction layer generic regis    156 /* WT hardware abstraction layer generic register interface. */
157 static int                                        157 static int
158 vortex_wt_SetReg2(vortex_t * vortex, unsigned     158 vortex_wt_SetReg2(vortex_t * vortex, unsigned char reg, int wt,
159                   u16 val)                        159                   u16 val)
160 {                                                 160 {
161         /*                                        161         /*
162            int eax, edx;                          162            int eax, edx;
163                                                   163 
164            if (wt >= NR_WT)  // 0x40 -> NR_WT     164            if (wt >= NR_WT)  // 0x40 -> NR_WT
165            return 0;                              165            return 0;
166                                                   166 
167            if ((reg - 0x20) > 0) {                167            if ((reg - 0x20) > 0) {
168            if ((reg - 0x21) != 0)                 168            if ((reg - 0x21) != 0) 
169            return 0;                              169            return 0;
170            eax = ((((b & 0xff) << 0xb) + (edx     170            eax = ((((b & 0xff) << 0xb) + (edx & 0xff)) << 4) + 0x208; // param 2
171            } else {                               171            } else {
172            eax = ((((b & 0xff) << 0xb) + (edx     172            eax = ((((b & 0xff) << 0xb) + (edx & 0xff)) << 4) + 0x20a; // param 3
173            }                                      173            }
174            hwwrite(vortex->mmio, eax, c);         174            hwwrite(vortex->mmio, eax, c);
175          */                                       175          */
176         return 1;                                 176         return 1;
177 }                                                 177 }
178                                                   178 
179 /*public: static void __thiscall CWTHal::SetRe    179 /*public: static void __thiscall CWTHal::SetReg(unsigned char,int,unsigned long) */
180 #endif                                            180 #endif
181 static int                                        181 static int
182 vortex_wt_SetReg(vortex_t * vortex, unsigned c    182 vortex_wt_SetReg(vortex_t * vortex, unsigned char reg, int wt,
183                  u32 val)                         183                  u32 val)
184 {                                                 184 {
185         int ecx;                                  185         int ecx;
186                                                   186 
187         if ((reg == 5) || ((reg >= 7) && (reg     187         if ((reg == 5) || ((reg >= 7) && (reg <= 10)) || (reg == 0xc)) {
188                 if (wt >= (NR_WT / NR_WT_PB))     188                 if (wt >= (NR_WT / NR_WT_PB)) {
189                         dev_warn(vortex->card-    189                         dev_warn(vortex->card->dev,
190                                  "WT SetReg: b    190                                  "WT SetReg: bank out of range. reg=0x%x, wt=%d\n",
191                                  reg, wt);        191                                  reg, wt);
192                         return 0;                 192                         return 0;
193                 }                                 193                 }
194         } else {                                  194         } else {
195                 if (wt >= NR_WT) {                195                 if (wt >= NR_WT) {
196                         dev_err(vortex->card->    196                         dev_err(vortex->card->dev,
197                                 "WT SetReg: vo    197                                 "WT SetReg: voice out of range\n");
198                         return 0;                 198                         return 0;
199                 }                                 199                 }
200         }                                         200         }
201         if (reg > 0xc)                            201         if (reg > 0xc)
202                 return 0;                         202                 return 0;
203                                                   203 
204         switch (reg) {                            204         switch (reg) {
205                 /* Voice specific parameters *    205                 /* Voice specific parameters */
206         case 0:         /* running */             206         case 0:         /* running */
207                 /*                                207                 /*
208                 pr_debug( "vortex: WT SetReg(0    208                 pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n",
209                        WT_RUN(wt), (int)val);     209                        WT_RUN(wt), (int)val);
210                 */                                210                 */
211                 hwwrite(vortex->mmio, WT_RUN(w    211                 hwwrite(vortex->mmio, WT_RUN(wt), val);
212                 return 0xc;                       212                 return 0xc;
213         case 1:         /* param 0 */             213         case 1:         /* param 0 */
214                 /*                                214                 /*
215                 pr_debug( "vortex: WT SetReg(0    215                 pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n",
216                        WT_PARM(wt,0), (int)val    216                        WT_PARM(wt,0), (int)val);
217                 */                                217                 */
218                 hwwrite(vortex->mmio, WT_PARM(    218                 hwwrite(vortex->mmio, WT_PARM(wt, 0), val);
219                 return 0xc;                       219                 return 0xc;
220         case 2:         /* param 1 */             220         case 2:         /* param 1 */
221                 /*                                221                 /*
222                 pr_debug( "vortex: WT SetReg(0    222                 pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n",
223                        WT_PARM(wt,1), (int)val    223                        WT_PARM(wt,1), (int)val);
224                 */                                224                 */
225                 hwwrite(vortex->mmio, WT_PARM(    225                 hwwrite(vortex->mmio, WT_PARM(wt, 1), val);
226                 return 0xc;                       226                 return 0xc;
227         case 3:         /* param 2 */             227         case 3:         /* param 2 */
228                 /*                                228                 /*
229                 pr_debug( "vortex: WT SetReg(0    229                 pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n",
230                        WT_PARM(wt,2), (int)val    230                        WT_PARM(wt,2), (int)val);
231                 */                                231                 */
232                 hwwrite(vortex->mmio, WT_PARM(    232                 hwwrite(vortex->mmio, WT_PARM(wt, 2), val);
233                 return 0xc;                       233                 return 0xc;
234         case 4:         /* param 3 */             234         case 4:         /* param 3 */
235                 /*                                235                 /*
236                 pr_debug( "vortex: WT SetReg(0    236                 pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n",
237                        WT_PARM(wt,3), (int)val    237                        WT_PARM(wt,3), (int)val);
238                 */                                238                 */
239                 hwwrite(vortex->mmio, WT_PARM(    239                 hwwrite(vortex->mmio, WT_PARM(wt, 3), val);
240                 return 0xc;                       240                 return 0xc;
241         case 6:         /* mute */                241         case 6:         /* mute */
242                 /*                                242                 /*
243                 pr_debug( "vortex: WT SetReg(0    243                 pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n",
244                        WT_MUTE(wt), (int)val);    244                        WT_MUTE(wt), (int)val);
245                 */                                245                 */
246                 hwwrite(vortex->mmio, WT_MUTE(    246                 hwwrite(vortex->mmio, WT_MUTE(wt), val);
247                 return 0xc;                       247                 return 0xc;
248         case 0xb:                                 248         case 0xb:
249                         /* delay */               249                         /* delay */
250                 /*                                250                 /*
251                 pr_debug( "vortex: WT SetReg(0    251                 pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n",
252                        WT_DELAY(wt,0), (int)va    252                        WT_DELAY(wt,0), (int)val);
253                 */                                253                 */
254                 hwwrite(vortex->mmio, WT_DELAY    254                 hwwrite(vortex->mmio, WT_DELAY(wt, 3), val);
255                 hwwrite(vortex->mmio, WT_DELAY    255                 hwwrite(vortex->mmio, WT_DELAY(wt, 2), val);
256                 hwwrite(vortex->mmio, WT_DELAY    256                 hwwrite(vortex->mmio, WT_DELAY(wt, 1), val);
257                 hwwrite(vortex->mmio, WT_DELAY    257                 hwwrite(vortex->mmio, WT_DELAY(wt, 0), val);
258                 return 0xc;                       258                 return 0xc;
259                 /* Global WT block parameters     259                 /* Global WT block parameters */
260         case 5:         /* sramp */               260         case 5:         /* sramp */
261                 ecx = WT_SRAMP(wt);               261                 ecx = WT_SRAMP(wt);
262                 break;                            262                 break;
263         case 8:         /* aramp */               263         case 8:         /* aramp */
264                 ecx = WT_ARAMP(wt);               264                 ecx = WT_ARAMP(wt);
265                 break;                            265                 break;
266         case 9:         /* mramp */               266         case 9:         /* mramp */
267                 ecx = WT_MRAMP(wt);               267                 ecx = WT_MRAMP(wt);
268                 break;                            268                 break;
269         case 0xa:               /* ctrl */        269         case 0xa:               /* ctrl */
270                 ecx = WT_CTRL(wt);                270                 ecx = WT_CTRL(wt);
271                 break;                            271                 break;
272         case 0xc:               /* ds_reg */      272         case 0xc:               /* ds_reg */
273                 ecx = WT_DSREG(wt);               273                 ecx = WT_DSREG(wt);
274                 break;                            274                 break;
275         default:                                  275         default:
276                 return 0;                         276                 return 0;
277         }                                         277         }
278         /*                                        278         /*
279         pr_debug( "vortex: WT SetReg(0x%x) = 0    279         pr_debug( "vortex: WT SetReg(0x%x) = 0x%08x\n", ecx, (int)val);
280         */                                        280         */
281         hwwrite(vortex->mmio, ecx, val);          281         hwwrite(vortex->mmio, ecx, val);
282         return 1;                                 282         return 1;
283 }                                                 283 }
284                                                   284 
285 static void vortex_wt_init(vortex_t * vortex)     285 static void vortex_wt_init(vortex_t * vortex)
286 {                                                 286 {
287         u32 var4, var8, varc, var10 = 0, edi;     287         u32 var4, var8, varc, var10 = 0, edi;
288                                                   288 
289         var10 &= 0xFFFFFFE3;                      289         var10 &= 0xFFFFFFE3;
290         var10 |= 0x22;                            290         var10 |= 0x22;
291         var10 &= 0xFFFFFEBF;                      291         var10 &= 0xFFFFFEBF;
292         var10 |= 0x80;                            292         var10 |= 0x80;
293         var10 |= 0x200;                           293         var10 |= 0x200;
294         var10 &= 0xfffffffe;                      294         var10 &= 0xfffffffe;
295         var10 &= 0xfffffbff;                      295         var10 &= 0xfffffbff;
296         var10 |= 0x1800;                          296         var10 |= 0x1800;
297         // var10 = 0x1AA2                         297         // var10 = 0x1AA2
298         var4 = 0x10000000;                        298         var4 = 0x10000000;
299         varc = 0x00830000;                        299         varc = 0x00830000;
300         var8 = 0x00830000;                        300         var8 = 0x00830000;
301                                                   301 
302         /* Init Bank registers. */                302         /* Init Bank registers. */
303         for (edi = 0; edi < (NR_WT / NR_WT_PB)    303         for (edi = 0; edi < (NR_WT / NR_WT_PB); edi++) {
304                 vortex_wt_SetReg(vortex, 0xc,     304                 vortex_wt_SetReg(vortex, 0xc, edi, 0);  /* ds_reg */
305                 vortex_wt_SetReg(vortex, 0xa,     305                 vortex_wt_SetReg(vortex, 0xa, edi, var10);      /* ctrl  */
306                 vortex_wt_SetReg(vortex, 0x9,     306                 vortex_wt_SetReg(vortex, 0x9, edi, var4);       /* mramp */
307                 vortex_wt_SetReg(vortex, 0x8,     307                 vortex_wt_SetReg(vortex, 0x8, edi, varc);       /* aramp */
308                 vortex_wt_SetReg(vortex, 0x5,     308                 vortex_wt_SetReg(vortex, 0x5, edi, var8);       /* sramp */
309         }                                         309         }
310         /* Init Voice registers. */               310         /* Init Voice registers. */
311         for (edi = 0; edi < NR_WT; edi++) {       311         for (edi = 0; edi < NR_WT; edi++) {
312                 vortex_wt_SetReg(vortex, 0x4,     312                 vortex_wt_SetReg(vortex, 0x4, edi, 0);  /* param 3 0x20c */
313                 vortex_wt_SetReg(vortex, 0x3,     313                 vortex_wt_SetReg(vortex, 0x3, edi, 0);  /* param 2 0x208 */
314                 vortex_wt_SetReg(vortex, 0x2,     314                 vortex_wt_SetReg(vortex, 0x2, edi, 0);  /* param 1 0x204 */
315                 vortex_wt_SetReg(vortex, 0x1,     315                 vortex_wt_SetReg(vortex, 0x1, edi, 0);  /* param 0 0x200 */
316                 vortex_wt_SetReg(vortex, 0xb,     316                 vortex_wt_SetReg(vortex, 0xb, edi, 0);  /* delay 0x400 - 0x40c */
317         }                                         317         }
318         var10 |= 1;                               318         var10 |= 1;
319         for (edi = 0; edi < (NR_WT / NR_WT_PB)    319         for (edi = 0; edi < (NR_WT / NR_WT_PB); edi++)
320                 vortex_wt_SetReg(vortex, 0xa,     320                 vortex_wt_SetReg(vortex, 0xa, edi, var10);      /* ctrl */
321 }                                                 321 }
322                                                   322 
323 /* Extract of CAdbTopology::SetVolume(struct _    323 /* Extract of CAdbTopology::SetVolume(struct _ASPVOLUME *) */
324 #if 0                                             324 #if 0
325 static void vortex_wt_SetVolume(vortex_t * vor    325 static void vortex_wt_SetVolume(vortex_t * vortex, int wt, int vol[])
326 {                                                 326 {
327         wt_voice_t *voice = &(vortex->wt_voice    327         wt_voice_t *voice = &(vortex->wt_voice[wt]);
328         int ecx = vol[1], eax = vol[0];           328         int ecx = vol[1], eax = vol[0];
329                                                   329 
330         /* This is pure guess */                  330         /* This is pure guess */
331         voice->parm0 &= 0xff00ffff;               331         voice->parm0 &= 0xff00ffff;
332         voice->parm0 |= (vol[0] & 0xff) << 0x1    332         voice->parm0 |= (vol[0] & 0xff) << 0x10;
333         voice->parm1 &= 0xff00ffff;               333         voice->parm1 &= 0xff00ffff;
334         voice->parm1 |= (vol[1] & 0xff) << 0x1    334         voice->parm1 |= (vol[1] & 0xff) << 0x10;
335                                                   335 
336         /* This is real */                        336         /* This is real */
337         hwwrite(vortex, WT_PARM(wt, 0), voice-    337         hwwrite(vortex, WT_PARM(wt, 0), voice->parm0);
338         hwwrite(vortex, WT_PARM(wt, 1), voice-    338         hwwrite(vortex, WT_PARM(wt, 1), voice->parm0);
339                                                   339 
340         if (voice->this_1D0 & 4) {                340         if (voice->this_1D0 & 4) {
341                 eax >>= 8;                        341                 eax >>= 8;
342                 ecx = eax;                        342                 ecx = eax;
343                 if (ecx < 0x80)                   343                 if (ecx < 0x80)
344                         ecx = 0x7f;               344                         ecx = 0x7f;
345                 voice->parm3 &= 0xFFFFC07F;       345                 voice->parm3 &= 0xFFFFC07F;
346                 voice->parm3 |= (ecx & 0x7f) <    346                 voice->parm3 |= (ecx & 0x7f) << 7;
347                 voice->parm3 &= 0xFFFFFF80;       347                 voice->parm3 &= 0xFFFFFF80;
348                 voice->parm3 |= (eax & 0x7f);     348                 voice->parm3 |= (eax & 0x7f);
349         } else {                                  349         } else {
350                 voice->parm3 &= 0xFFE03FFF;       350                 voice->parm3 &= 0xFFE03FFF;
351                 voice->parm3 |= (eax & 0xFE00)    351                 voice->parm3 |= (eax & 0xFE00) << 5;
352         }                                         352         }
353                                                   353 
354         hwwrite(vortex, WT_PARM(wt, 3), voice-    354         hwwrite(vortex, WT_PARM(wt, 3), voice->parm3);
355 }                                                 355 }
356                                                   356 
357 /* Extract of CAdbTopology::SetFrequency(unsig    357 /* Extract of CAdbTopology::SetFrequency(unsigned long arg_0) */
358 static void vortex_wt_SetFrequency(vortex_t *     358 static void vortex_wt_SetFrequency(vortex_t * vortex, int wt, unsigned int sr)
359 {                                                 359 {
360         wt_voice_t *voice = &(vortex->wt_voice    360         wt_voice_t *voice = &(vortex->wt_voice[wt]);
361         u32 eax, edx;                             361         u32 eax, edx;
362                                                   362 
363         //FIXME: 64 bit operation.                363         //FIXME: 64 bit operation.
364         eax = ((sr << 0xf) * 0x57619F1) & 0xff    364         eax = ((sr << 0xf) * 0x57619F1) & 0xffffffff;
365         edx = (((sr << 0xf) * 0x57619F1)) >> 0    365         edx = (((sr << 0xf) * 0x57619F1)) >> 0x20;
366                                                   366 
367         edx >>= 0xa;                              367         edx >>= 0xa;
368         edx <<= 1;                                368         edx <<= 1;
369         if (edx) {                                369         if (edx) {
370                 if (edx & 0x0FFF80000)            370                 if (edx & 0x0FFF80000)
371                         eax = 0x7fff;             371                         eax = 0x7fff;
372                 else {                            372                 else {
373                         edx <<= 0xd;              373                         edx <<= 0xd;
374                         eax = 7;                  374                         eax = 7;
375                         while ((edx & 0x800000    375                         while ((edx & 0x80000000) == 0) {
376                                 edx <<= 1;        376                                 edx <<= 1;
377                                 eax--;            377                                 eax--;
378                                 if (eax == 0)     378                                 if (eax == 0)
379                                         break;    379                                         break;
380                         }                         380                         }
381                         if (eax)                  381                         if (eax)
382                                 edx <<= 1;        382                                 edx <<= 1;
383                         eax <<= 0xc;              383                         eax <<= 0xc;
384                         edx >>= 0x14;             384                         edx >>= 0x14;
385                         eax |= edx;               385                         eax |= edx;
386                 }                                 386                 }
387         } else                                    387         } else
388                 eax = 0;                          388                 eax = 0;
389         voice->parm0 &= 0xffff0001;               389         voice->parm0 &= 0xffff0001;
390         voice->parm0 |= (eax & 0x7fff) << 1;      390         voice->parm0 |= (eax & 0x7fff) << 1;
391         voice->parm1 = voice->parm0 | 1;          391         voice->parm1 = voice->parm0 | 1;
392         // Wt: this_1D4                           392         // Wt: this_1D4
393         //AuWt::WriteReg((ulong)(this_1DC<<4)+    393         //AuWt::WriteReg((ulong)(this_1DC<<4)+0x200, (ulong)this_1E4);
394         //AuWt::WriteReg((ulong)(this_1DC<<4)+    394         //AuWt::WriteReg((ulong)(this_1DC<<4)+0x204, (ulong)this_1E8);
395         hwwrite(vortex->mmio, WT_PARM(wt, 0),     395         hwwrite(vortex->mmio, WT_PARM(wt, 0), voice->parm0);
396         hwwrite(vortex->mmio, WT_PARM(wt, 1),     396         hwwrite(vortex->mmio, WT_PARM(wt, 1), voice->parm1);
397 }                                                 397 }
398 #endif                                            398 #endif
399                                                   399 
400 /* End of File */                                 400 /* End of File */
401                                                   401 

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