1 // SPDX-License-Identifier: GPL-2.0-only <<
2 /********************************************* 1 /*****************************************************************************
3 * 2 *
4 * Copyright (C) 2008 Cedric Bregardis <cedric 3 * Copyright (C) 2008 Cedric Bregardis <cedric.bregardis@free.fr> and
5 * Jean-Christian Hassler <jhassler@free.fr> 4 * Jean-Christian Hassler <jhassler@free.fr>
6 * Copyright 1998 Emagic Soft- und Hardware Gm 5 * Copyright 1998 Emagic Soft- und Hardware GmbH
7 * Copyright 2002 Martijn Sipkema 6 * Copyright 2002 Martijn Sipkema
8 * 7 *
9 * This file is part of the Audiowerk2 ALSA dr 8 * This file is part of the Audiowerk2 ALSA driver
10 * 9 *
>> 10 * The Audiowerk2 ALSA driver is free software; you can redistribute it and/or
>> 11 * modify it under the terms of the GNU General Public License as published by
>> 12 * the Free Software Foundation; version 2.
>> 13 *
>> 14 * The Audiowerk2 ALSA driver is distributed in the hope that it will be useful,
>> 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 17 * GNU General Public License for more details.
>> 18 *
>> 19 * You should have received a copy of the GNU General Public License
>> 20 * along with the Audiowerk2 ALSA driver; if not, write to the Free Software
>> 21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
>> 22 * USA.
>> 23 *
11 ********************************************* 24 *****************************************************************************/
12 25
13 #define TSL_WS0 (1UL << 31) 26 #define TSL_WS0 (1UL << 31)
14 #define TSL_WS1 (1UL << 30) 27 #define TSL_WS1 (1UL << 30)
15 #define TSL_WS2 (1UL << 29) 28 #define TSL_WS2 (1UL << 29)
16 #define TSL_WS3 (1UL << 28) 29 #define TSL_WS3 (1UL << 28)
17 #define TSL_WS4 (1UL << 27) 30 #define TSL_WS4 (1UL << 27)
18 #define TSL_DIS_A1 (1UL << 24) 31 #define TSL_DIS_A1 (1UL << 24)
19 #define TSL_SDW_A1 (1UL << 23) 32 #define TSL_SDW_A1 (1UL << 23)
20 #define TSL_SIB_A1 (1UL << 22) 33 #define TSL_SIB_A1 (1UL << 22)
21 #define TSL_SF_A1 (1UL << 21) 34 #define TSL_SF_A1 (1UL << 21)
22 #define TSL_LF_A1 (1UL << 20) 35 #define TSL_LF_A1 (1UL << 20)
23 #define TSL_BSEL_A1 (1UL << 17) 36 #define TSL_BSEL_A1 (1UL << 17)
24 #define TSL_DOD_A1 (1UL << 15) 37 #define TSL_DOD_A1 (1UL << 15)
25 #define TSL_LOW_A1 (1UL << 14) 38 #define TSL_LOW_A1 (1UL << 14)
26 #define TSL_DIS_A2 (1UL << 11) 39 #define TSL_DIS_A2 (1UL << 11)
27 #define TSL_SDW_A2 (1UL << 10) 40 #define TSL_SDW_A2 (1UL << 10)
28 #define TSL_SIB_A2 (1UL << 9) 41 #define TSL_SIB_A2 (1UL << 9)
29 #define TSL_SF_A2 (1UL << 8) 42 #define TSL_SF_A2 (1UL << 8)
30 #define TSL_LF_A2 (1UL << 7) 43 #define TSL_LF_A2 (1UL << 7)
31 #define TSL_BSEL_A2 (1UL << 4) 44 #define TSL_BSEL_A2 (1UL << 4)
32 #define TSL_DOD_A2 (1UL << 2) 45 #define TSL_DOD_A2 (1UL << 2)
33 #define TSL_LOW_A2 (1UL << 1) 46 #define TSL_LOW_A2 (1UL << 1)
34 #define TSL_EOS (1UL << 0) 47 #define TSL_EOS (1UL << 0)
35 48
36 /* Audiowerk8 hardware setup: */ 49 /* Audiowerk8 hardware setup: */
37 /* WS0, SD4, TSL1 - Analog/ digital 50 /* WS0, SD4, TSL1 - Analog/ digital in */
38 /* WS1, SD0, TSL1 - Analog out #1, d 51 /* WS1, SD0, TSL1 - Analog out #1, digital out */
39 /* WS2, SD2, TSL1 - Analog out #2 */ 52 /* WS2, SD2, TSL1 - Analog out #2 */
40 /* WS3, SD1, TSL2 - Analog out #3 */ 53 /* WS3, SD1, TSL2 - Analog out #3 */
41 /* WS4, SD3, TSL2 - Analog out #4 */ 54 /* WS4, SD3, TSL2 - Analog out #4 */
42 55
43 /* Audiowerk8 timing: */ 56 /* Audiowerk8 timing: */
44 /* Timeslot: | 0 | 1 | 2 | 3 | 4 57 /* Timeslot: | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | ... */
45 58
46 /* A1_INPUT: */ 59 /* A1_INPUT: */
47 /* SD4: <_ADC-L_>-------<_AD 60 /* SD4: <_ADC-L_>-------<_ADC-R_>-------< */
48 /* WS0: _______________/---- 61 /* WS0: _______________/---------------\_ */
49 62
50 /* A1_OUTPUT: */ 63 /* A1_OUTPUT: */
51 /* SD0: <_1-L___>-------<_1- 64 /* SD0: <_1-L___>-------<_1-R___>-------< */
52 /* WS1: _______________/---- 65 /* WS1: _______________/---------------\_ */
53 /* SD2: >-------<_2-L___>--- 66 /* SD2: >-------<_2-L___>-------<_2-R___> */
54 /* WS2: -------\____________ 67 /* WS2: -------\_______________/--------- */
55 68
56 /* A2_OUTPUT: */ 69 /* A2_OUTPUT: */
57 /* SD1: <_3-L___>-------<_3- 70 /* SD1: <_3-L___>-------<_3-R___>-------< */
58 /* WS3: _______________/---- 71 /* WS3: _______________/---------------\_ */
59 /* SD3: >-------<_4-L___>--- 72 /* SD3: >-------<_4-L___>-------<_4-R___> */
60 /* WS4: -------\____________ 73 /* WS4: -------\_______________/--------- */
61 74
62 static const int tsl1[8] = { !! 75 static int tsl1[8] = {
63 1 * TSL_SDW_A1 | 3 * TSL_BSEL_A1 | 76 1 * TSL_SDW_A1 | 3 * TSL_BSEL_A1 |
64 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_ 77 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_LF_A1,
65 78
66 1 * TSL_SDW_A1 | 2 * TSL_BSEL_A1 | 79 1 * TSL_SDW_A1 | 2 * TSL_BSEL_A1 |
67 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1, 80 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1,
68 81
69 0 * TSL_SDW_A1 | 3 * TSL_BSEL_A1 | 82 0 * TSL_SDW_A1 | 3 * TSL_BSEL_A1 |
70 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1, 83 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1,
71 84
72 0 * TSL_SDW_A1 | 2 * TSL_BSEL_A1 | 85 0 * TSL_SDW_A1 | 2 * TSL_BSEL_A1 |
73 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1, 86 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1,
74 87
75 1 * TSL_SDW_A1 | 1 * TSL_BSEL_A1 | 88 1 * TSL_SDW_A1 | 1 * TSL_BSEL_A1 |
76 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_ 89 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0,
77 90
78 1 * TSL_SDW_A1 | 0 * TSL_BSEL_A1 | 91 1 * TSL_SDW_A1 | 0 * TSL_BSEL_A1 |
79 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_ 92 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0,
80 93
81 0 * TSL_SDW_A1 | 1 * TSL_BSEL_A1 | 94 0 * TSL_SDW_A1 | 1 * TSL_BSEL_A1 |
82 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_ 95 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0,
83 96
84 0 * TSL_SDW_A1 | 0 * TSL_BSEL_A1 | 0 * 97 0 * TSL_SDW_A1 | 0 * TSL_BSEL_A1 | 0 * TSL_DIS_A1 |
85 0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0 | T 98 0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0 | TSL_SF_A1 | TSL_EOS,
86 }; 99 };
87 100
88 static const int tsl2[8] = { !! 101 static int tsl2[8] = {
89 0 * TSL_SDW_A2 | 3 * TSL_BSEL_A2 | 2 * 102 0 * TSL_SDW_A2 | 3 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_LF_A2,
90 0 * TSL_SDW_A2 | 2 * TSL_BSEL_A2 | 2 * 103 0 * TSL_SDW_A2 | 2 * TSL_BSEL_A2 | 2 * TSL_DOD_A2,
91 0 * TSL_SDW_A2 | 3 * TSL_BSEL_A2 | 2 * 104 0 * TSL_SDW_A2 | 3 * TSL_BSEL_A2 | 2 * TSL_DOD_A2,
92 0 * TSL_SDW_A2 | 2 * TSL_BSEL_A2 | 2 * 105 0 * TSL_SDW_A2 | 2 * TSL_BSEL_A2 | 2 * TSL_DOD_A2,
93 0 * TSL_SDW_A2 | 1 * TSL_BSEL_A2 | 2 * 106 0 * TSL_SDW_A2 | 1 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_WS2,
94 0 * TSL_SDW_A2 | 0 * TSL_BSEL_A2 | 2 * 107 0 * TSL_SDW_A2 | 0 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_WS2,
95 0 * TSL_SDW_A2 | 1 * TSL_BSEL_A2 | 2 * 108 0 * TSL_SDW_A2 | 1 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_WS2,
96 0 * TSL_SDW_A2 | 0 * TSL_BSEL_A2 | 2 * 109 0 * TSL_SDW_A2 | 0 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_WS2 | TSL_EOS
97 }; 110 };
98 111
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