1 // SPDX-License-Identifier: GPL-2.0-only 1 // SPDX-License-Identifier: GPL-2.0-only
2 /********************************************* 2 /*****************************************************************************
3 * 3 *
4 * Copyright (C) 2008 Cedric Bregardis <cedric 4 * Copyright (C) 2008 Cedric Bregardis <cedric.bregardis@free.fr> and
5 * Jean-Christian Hassler <jhassler@free.fr> 5 * Jean-Christian Hassler <jhassler@free.fr>
6 * Copyright 1998 Emagic Soft- und Hardware Gm 6 * Copyright 1998 Emagic Soft- und Hardware GmbH
7 * Copyright 2002 Martijn Sipkema 7 * Copyright 2002 Martijn Sipkema
8 * 8 *
9 * This file is part of the Audiowerk2 ALSA dr 9 * This file is part of the Audiowerk2 ALSA driver
10 * 10 *
11 ********************************************* 11 *****************************************************************************/
12 12
13 #define TSL_WS0 (1UL << 31) 13 #define TSL_WS0 (1UL << 31)
14 #define TSL_WS1 (1UL << 30) 14 #define TSL_WS1 (1UL << 30)
15 #define TSL_WS2 (1UL << 29) 15 #define TSL_WS2 (1UL << 29)
16 #define TSL_WS3 (1UL << 28) 16 #define TSL_WS3 (1UL << 28)
17 #define TSL_WS4 (1UL << 27) 17 #define TSL_WS4 (1UL << 27)
18 #define TSL_DIS_A1 (1UL << 24) 18 #define TSL_DIS_A1 (1UL << 24)
19 #define TSL_SDW_A1 (1UL << 23) 19 #define TSL_SDW_A1 (1UL << 23)
20 #define TSL_SIB_A1 (1UL << 22) 20 #define TSL_SIB_A1 (1UL << 22)
21 #define TSL_SF_A1 (1UL << 21) 21 #define TSL_SF_A1 (1UL << 21)
22 #define TSL_LF_A1 (1UL << 20) 22 #define TSL_LF_A1 (1UL << 20)
23 #define TSL_BSEL_A1 (1UL << 17) 23 #define TSL_BSEL_A1 (1UL << 17)
24 #define TSL_DOD_A1 (1UL << 15) 24 #define TSL_DOD_A1 (1UL << 15)
25 #define TSL_LOW_A1 (1UL << 14) 25 #define TSL_LOW_A1 (1UL << 14)
26 #define TSL_DIS_A2 (1UL << 11) 26 #define TSL_DIS_A2 (1UL << 11)
27 #define TSL_SDW_A2 (1UL << 10) 27 #define TSL_SDW_A2 (1UL << 10)
28 #define TSL_SIB_A2 (1UL << 9) 28 #define TSL_SIB_A2 (1UL << 9)
29 #define TSL_SF_A2 (1UL << 8) 29 #define TSL_SF_A2 (1UL << 8)
30 #define TSL_LF_A2 (1UL << 7) 30 #define TSL_LF_A2 (1UL << 7)
31 #define TSL_BSEL_A2 (1UL << 4) 31 #define TSL_BSEL_A2 (1UL << 4)
32 #define TSL_DOD_A2 (1UL << 2) 32 #define TSL_DOD_A2 (1UL << 2)
33 #define TSL_LOW_A2 (1UL << 1) 33 #define TSL_LOW_A2 (1UL << 1)
34 #define TSL_EOS (1UL << 0) 34 #define TSL_EOS (1UL << 0)
35 35
36 /* Audiowerk8 hardware setup: */ 36 /* Audiowerk8 hardware setup: */
37 /* WS0, SD4, TSL1 - Analog/ digital 37 /* WS0, SD4, TSL1 - Analog/ digital in */
38 /* WS1, SD0, TSL1 - Analog out #1, d 38 /* WS1, SD0, TSL1 - Analog out #1, digital out */
39 /* WS2, SD2, TSL1 - Analog out #2 */ 39 /* WS2, SD2, TSL1 - Analog out #2 */
40 /* WS3, SD1, TSL2 - Analog out #3 */ 40 /* WS3, SD1, TSL2 - Analog out #3 */
41 /* WS4, SD3, TSL2 - Analog out #4 */ 41 /* WS4, SD3, TSL2 - Analog out #4 */
42 42
43 /* Audiowerk8 timing: */ 43 /* Audiowerk8 timing: */
44 /* Timeslot: | 0 | 1 | 2 | 3 | 4 44 /* Timeslot: | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | ... */
45 45
46 /* A1_INPUT: */ 46 /* A1_INPUT: */
47 /* SD4: <_ADC-L_>-------<_AD 47 /* SD4: <_ADC-L_>-------<_ADC-R_>-------< */
48 /* WS0: _______________/---- 48 /* WS0: _______________/---------------\_ */
49 49
50 /* A1_OUTPUT: */ 50 /* A1_OUTPUT: */
51 /* SD0: <_1-L___>-------<_1- 51 /* SD0: <_1-L___>-------<_1-R___>-------< */
52 /* WS1: _______________/---- 52 /* WS1: _______________/---------------\_ */
53 /* SD2: >-------<_2-L___>--- 53 /* SD2: >-------<_2-L___>-------<_2-R___> */
54 /* WS2: -------\____________ 54 /* WS2: -------\_______________/--------- */
55 55
56 /* A2_OUTPUT: */ 56 /* A2_OUTPUT: */
57 /* SD1: <_3-L___>-------<_3- 57 /* SD1: <_3-L___>-------<_3-R___>-------< */
58 /* WS3: _______________/---- 58 /* WS3: _______________/---------------\_ */
59 /* SD3: >-------<_4-L___>--- 59 /* SD3: >-------<_4-L___>-------<_4-R___> */
60 /* WS4: -------\____________ 60 /* WS4: -------\_______________/--------- */
61 61
62 static const int tsl1[8] = { 62 static const int tsl1[8] = {
63 1 * TSL_SDW_A1 | 3 * TSL_BSEL_A1 | 63 1 * TSL_SDW_A1 | 3 * TSL_BSEL_A1 |
64 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_ 64 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_LF_A1,
65 65
66 1 * TSL_SDW_A1 | 2 * TSL_BSEL_A1 | 66 1 * TSL_SDW_A1 | 2 * TSL_BSEL_A1 |
67 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1, 67 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1,
68 68
69 0 * TSL_SDW_A1 | 3 * TSL_BSEL_A1 | 69 0 * TSL_SDW_A1 | 3 * TSL_BSEL_A1 |
70 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1, 70 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1,
71 71
72 0 * TSL_SDW_A1 | 2 * TSL_BSEL_A1 | 72 0 * TSL_SDW_A1 | 2 * TSL_BSEL_A1 |
73 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1, 73 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1,
74 74
75 1 * TSL_SDW_A1 | 1 * TSL_BSEL_A1 | 75 1 * TSL_SDW_A1 | 1 * TSL_BSEL_A1 |
76 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_ 76 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0,
77 77
78 1 * TSL_SDW_A1 | 0 * TSL_BSEL_A1 | 78 1 * TSL_SDW_A1 | 0 * TSL_BSEL_A1 |
79 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_ 79 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0,
80 80
81 0 * TSL_SDW_A1 | 1 * TSL_BSEL_A1 | 81 0 * TSL_SDW_A1 | 1 * TSL_BSEL_A1 |
82 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_ 82 0 * TSL_DIS_A1 | 0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0,
83 83
84 0 * TSL_SDW_A1 | 0 * TSL_BSEL_A1 | 0 * 84 0 * TSL_SDW_A1 | 0 * TSL_BSEL_A1 | 0 * TSL_DIS_A1 |
85 0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0 | T 85 0 * TSL_DOD_A1 | TSL_WS1 | TSL_WS0 | TSL_SF_A1 | TSL_EOS,
86 }; 86 };
87 87
88 static const int tsl2[8] = { 88 static const int tsl2[8] = {
89 0 * TSL_SDW_A2 | 3 * TSL_BSEL_A2 | 2 * 89 0 * TSL_SDW_A2 | 3 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_LF_A2,
90 0 * TSL_SDW_A2 | 2 * TSL_BSEL_A2 | 2 * 90 0 * TSL_SDW_A2 | 2 * TSL_BSEL_A2 | 2 * TSL_DOD_A2,
91 0 * TSL_SDW_A2 | 3 * TSL_BSEL_A2 | 2 * 91 0 * TSL_SDW_A2 | 3 * TSL_BSEL_A2 | 2 * TSL_DOD_A2,
92 0 * TSL_SDW_A2 | 2 * TSL_BSEL_A2 | 2 * 92 0 * TSL_SDW_A2 | 2 * TSL_BSEL_A2 | 2 * TSL_DOD_A2,
93 0 * TSL_SDW_A2 | 1 * TSL_BSEL_A2 | 2 * 93 0 * TSL_SDW_A2 | 1 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_WS2,
94 0 * TSL_SDW_A2 | 0 * TSL_BSEL_A2 | 2 * 94 0 * TSL_SDW_A2 | 0 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_WS2,
95 0 * TSL_SDW_A2 | 1 * TSL_BSEL_A2 | 2 * 95 0 * TSL_SDW_A2 | 1 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_WS2,
96 0 * TSL_SDW_A2 | 0 * TSL_BSEL_A2 | 2 * 96 0 * TSL_SDW_A2 | 0 * TSL_BSEL_A2 | 2 * TSL_DOD_A2 | TSL_WS2 | TSL_EOS
97 }; 97 };
98 98
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