1 /* SPDX-License-Identifier: GPL-2.0-only */ <<
2 /********************************************* 1 /*****************************************************************************
3 * 2 *
4 * Copyright (C) 2008 Cedric Bregardis <cedric 3 * Copyright (C) 2008 Cedric Bregardis <cedric.bregardis@free.fr> and
5 * Jean-Christian Hassler <jhassler@free.fr> 4 * Jean-Christian Hassler <jhassler@free.fr>
6 * 5 *
7 * This file is part of the Audiowerk2 ALSA dr 6 * This file is part of the Audiowerk2 ALSA driver
>> 7 *
>> 8 * The Audiowerk2 ALSA driver is free software; you can redistribute it and/or
>> 9 * modify it under the terms of the GNU General Public License as published by
>> 10 * the Free Software Foundation; version 2.
>> 11 *
>> 12 * The Audiowerk2 ALSA driver is distributed in the hope that it will be useful,
>> 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 15 * GNU General Public License for more details.
>> 16 *
>> 17 * You should have received a copy of the GNU General Public License
>> 18 * along with the Audiowerk2 ALSA driver; if not, write to the Free Software
>> 19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
>> 20 * USA.
8 * 21 *
9 ********************************************* 22 *****************************************************************************/
10 23
11 /* SAA7146 registers */ 24 /* SAA7146 registers */
12 #define PCI_BT_A 0x4C 25 #define PCI_BT_A 0x4C
13 #define IICTFR 0x8C 26 #define IICTFR 0x8C
14 #define IICSTA 0x90 27 #define IICSTA 0x90
15 #define BaseA1_in 0x94 28 #define BaseA1_in 0x94
16 #define ProtA1_in 0x98 29 #define ProtA1_in 0x98
17 #define PageA1_in 0x9C 30 #define PageA1_in 0x9C
18 #define BaseA1_out 0xA0 31 #define BaseA1_out 0xA0
19 #define ProtA1_out 0xA4 32 #define ProtA1_out 0xA4
20 #define PageA1_out 0xA8 33 #define PageA1_out 0xA8
21 #define BaseA2_in 0xAC 34 #define BaseA2_in 0xAC
22 #define ProtA2_in 0xB0 35 #define ProtA2_in 0xB0
23 #define PageA2_in 0xB4 36 #define PageA2_in 0xB4
24 #define BaseA2_out 0xB8 37 #define BaseA2_out 0xB8
25 #define ProtA2_out 0xBC 38 #define ProtA2_out 0xBC
26 #define PageA2_out 0xC0 39 #define PageA2_out 0xC0
27 #define IER 0xDC 40 #define IER 0xDC
28 #define GPIO_CTRL 0xE0 41 #define GPIO_CTRL 0xE0
29 #define ACON1 0xF4 42 #define ACON1 0xF4
30 #define ACON2 0xF8 43 #define ACON2 0xF8
31 #define MC1 0xFC 44 #define MC1 0xFC
32 #define MC2 0x100 45 #define MC2 0x100
33 #define ISR 0x10C 46 #define ISR 0x10C
34 #define PSR 0x110 47 #define PSR 0x110
35 #define SSR 0x114 48 #define SSR 0x114
36 #define PCI_ADP1 0x12C 49 #define PCI_ADP1 0x12C
37 #define PCI_ADP2 0x130 50 #define PCI_ADP2 0x130
38 #define PCI_ADP3 0x134 51 #define PCI_ADP3 0x134
39 #define PCI_ADP4 0x138 52 #define PCI_ADP4 0x138
40 #define LEVEL_REP 0x140 53 #define LEVEL_REP 0x140
41 #define FB_BUFFER1 0x144 54 #define FB_BUFFER1 0x144
42 #define FB_BUFFER2 0x148 55 #define FB_BUFFER2 0x148
43 #define TSL1 0x180 56 #define TSL1 0x180
44 #define TSL2 0x1C0 57 #define TSL2 0x1C0
45 58
46 #define ME (1UL << 11) 59 #define ME (1UL << 11)
47 #define LIMIT (1UL << 4) 60 #define LIMIT (1UL << 4)
48 #define PV (1UL << 3) 61 #define PV (1UL << 3)
49 62
50 /* PSR/ISR/IER */ 63 /* PSR/ISR/IER */
51 #define PPEF (1UL << 31) 64 #define PPEF (1UL << 31)
52 #define PABO (1UL << 30) 65 #define PABO (1UL << 30)
53 #define IIC_S (1UL << 17) 66 #define IIC_S (1UL << 17)
54 #define IIC_E (1UL << 16) 67 #define IIC_E (1UL << 16)
55 #define A2_in (1UL << 15) 68 #define A2_in (1UL << 15)
56 #define A2_out (1UL << 14) 69 #define A2_out (1UL << 14)
57 #define A1_in (1UL << 13) 70 #define A1_in (1UL << 13)
58 #define A1_out (1UL << 12) 71 #define A1_out (1UL << 12)
59 #define AFOU (1UL << 11) 72 #define AFOU (1UL << 11)
60 #define PIN3 (1UL << 6) 73 #define PIN3 (1UL << 6)
61 #define PIN2 (1UL << 5) 74 #define PIN2 (1UL << 5)
62 #define PIN1 (1UL << 4) 75 #define PIN1 (1UL << 4)
63 #define PIN0 (1UL << 3) 76 #define PIN0 (1UL << 3)
64 #define ECS (1UL << 2) 77 #define ECS (1UL << 2)
65 #define EC3S (1UL << 1) 78 #define EC3S (1UL << 1)
66 #define EC0S (1UL << 0) 79 #define EC0S (1UL << 0)
67 80
68 /* SSR */ 81 /* SSR */
69 #define PRQ (1UL << 31) 82 #define PRQ (1UL << 31)
70 #define PMA (1UL << 30) 83 #define PMA (1UL << 30)
71 #define IIC_EA (1UL << 21) 84 #define IIC_EA (1UL << 21)
72 #define IIC_EW (1UL << 20) 85 #define IIC_EW (1UL << 20)
73 #define IIC_ER (1UL << 19) 86 #define IIC_ER (1UL << 19)
74 #define IIC_EL (1UL << 18) 87 #define IIC_EL (1UL << 18)
75 #define IIC_EF (1UL << 17) 88 #define IIC_EF (1UL << 17)
76 #define AF2_in (1UL << 10) 89 #define AF2_in (1UL << 10)
77 #define AF2_out (1UL << 9) 90 #define AF2_out (1UL << 9)
78 #define AF1_in (1UL << 8) 91 #define AF1_in (1UL << 8)
79 #define AF1_out (1UL << 7) 92 #define AF1_out (1UL << 7)
80 #define EC5S (1UL << 3) 93 #define EC5S (1UL << 3)
81 #define EC4S (1UL << 2) 94 #define EC4S (1UL << 2)
82 #define EC2S (1UL << 1) 95 #define EC2S (1UL << 1)
83 #define EC1S (1UL << 0) 96 #define EC1S (1UL << 0)
84 97
85 /* PCI_BT_A */ 98 /* PCI_BT_A */
86 #define BurstA1_in (1UL << 26) 99 #define BurstA1_in (1UL << 26)
87 #define ThreshA1_in (1UL << 24) 100 #define ThreshA1_in (1UL << 24)
88 #define BurstA1_out (1UL << 18) 101 #define BurstA1_out (1UL << 18)
89 #define ThreshA1_out (1UL << 16) 102 #define ThreshA1_out (1UL << 16)
90 #define BurstA2_in (1UL << 10) 103 #define BurstA2_in (1UL << 10)
91 #define ThreshA2_in (1UL << 8) 104 #define ThreshA2_in (1UL << 8)
92 #define BurstA2_out (1UL << 2) 105 #define BurstA2_out (1UL << 2)
93 #define ThreshA2_out (1UL << 0) 106 #define ThreshA2_out (1UL << 0)
94 107
95 /* MC1 */ 108 /* MC1 */
96 #define MRST_N (1UL << 15) 109 #define MRST_N (1UL << 15)
97 #define EAP (1UL << 9) 110 #define EAP (1UL << 9)
98 #define EI2C (1UL << 8) 111 #define EI2C (1UL << 8)
99 #define TR_E_A2_OUT (1UL << 3) 112 #define TR_E_A2_OUT (1UL << 3)
100 #define TR_E_A2_IN (1UL << 2) 113 #define TR_E_A2_IN (1UL << 2)
101 #define TR_E_A1_OUT (1UL << 1) 114 #define TR_E_A1_OUT (1UL << 1)
102 #define TR_E_A1_IN (1UL << 0) 115 #define TR_E_A1_IN (1UL << 0)
103 116
104 /* MC2 */ 117 /* MC2 */
105 #define UPLD_IIC (1UL << 0) 118 #define UPLD_IIC (1UL << 0)
106 119
107 /* ACON1 */ 120 /* ACON1 */
108 #define AUDIO_MODE (1UL << 29) 121 #define AUDIO_MODE (1UL << 29)
109 #define MAXLEVEL (1UL << 22) 122 #define MAXLEVEL (1UL << 22)
110 #define A1_SWAP (1UL << 21) 123 #define A1_SWAP (1UL << 21)
111 #define A2_SWAP (1UL << 20) 124 #define A2_SWAP (1UL << 20)
112 #define WS0_CTRL (1UL << 18) 125 #define WS0_CTRL (1UL << 18)
113 #define WS0_SYNC (1UL << 16) 126 #define WS0_SYNC (1UL << 16)
114 #define WS1_CTRL (1UL << 14) 127 #define WS1_CTRL (1UL << 14)
115 #define WS1_SYNC (1UL << 12) 128 #define WS1_SYNC (1UL << 12)
116 #define WS2_CTRL (1UL << 10) 129 #define WS2_CTRL (1UL << 10)
117 #define WS2_SYNC (1UL << 8) 130 #define WS2_SYNC (1UL << 8)
118 #define WS3_CTRL (1UL << 6) 131 #define WS3_CTRL (1UL << 6)
119 #define WS3_SYNC (1UL << 4) 132 #define WS3_SYNC (1UL << 4)
120 #define WS4_CTRL (1UL << 2) 133 #define WS4_CTRL (1UL << 2)
121 #define WS4_SYNC (1UL << 0) 134 #define WS4_SYNC (1UL << 0)
122 135
123 /* ACON2 */ 136 /* ACON2 */
124 #define A1_CLKSRC (1UL << 27) 137 #define A1_CLKSRC (1UL << 27)
125 #define A2_CLKSRC (1UL << 22) 138 #define A2_CLKSRC (1UL << 22)
126 #define INVERT_BCLK1 (1UL << 21) 139 #define INVERT_BCLK1 (1UL << 21)
127 #define INVERT_BCLK2 (1UL << 20) 140 #define INVERT_BCLK2 (1UL << 20)
128 #define BCLK1_OEN (1UL << 19) 141 #define BCLK1_OEN (1UL << 19)
129 #define BCLK2_OEN (1UL << 18) 142 #define BCLK2_OEN (1UL << 18)
130 143
131 /* IICSTA */ 144 /* IICSTA */
132 #define IICCC (1UL << 8) 145 #define IICCC (1UL << 8)
133 #define ABORT (1UL << 7) 146 #define ABORT (1UL << 7)
134 #define SPERR (1UL << 6) 147 #define SPERR (1UL << 6)
135 #define APERR (1UL << 5) 148 #define APERR (1UL << 5)
136 #define DTERR (1UL << 4) 149 #define DTERR (1UL << 4)
137 #define DRERR (1UL << 3) 150 #define DRERR (1UL << 3)
138 #define AL (1UL << 2) 151 #define AL (1UL << 2)
139 #define ERR (1UL << 1) 152 #define ERR (1UL << 1)
140 #define BUSY (1UL << 0) 153 #define BUSY (1UL << 0)
141 154
142 /* IICTFR */ 155 /* IICTFR */
143 #define BYTE2 (1UL << 24) 156 #define BYTE2 (1UL << 24)
144 #define BYTE1 (1UL << 16) 157 #define BYTE1 (1UL << 16)
145 #define BYTE0 (1UL << 8) 158 #define BYTE0 (1UL << 8)
146 #define ATRR2 (1UL << 6) 159 #define ATRR2 (1UL << 6)
147 #define ATRR1 (1UL << 4) 160 #define ATRR1 (1UL << 4)
148 #define ATRR0 (1UL << 2) 161 #define ATRR0 (1UL << 2)
149 #define ERR (1UL << 1) 162 #define ERR (1UL << 1)
150 #define BUSY (1UL << 0) 163 #define BUSY (1UL << 0)
151 164
152 #define START 3 165 #define START 3
153 #define CONT 2 166 #define CONT 2
154 #define STOP 1 167 #define STOP 1
155 #define NOP 0 168 #define NOP 0
156 169
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