1 /* SPDX-License-Identifier: GPL-2.0-or-later * 1
2 /*
3 * Copyright (c) 2004 James Courtier-Dutton <
4 * Driver CA0106 chips. e.g. Sound Blaster Au
5 * Version: 0.0.22
6 *
7 * FEATURES currently supported:
8 * See ca0106_main.c for features.
9 *
10 * Changelog:
11 * Support interrupts per period.
12 * Removed noise from Center/LFE channel wh
13 * Rename and remove mixer controls.
14 * 0.0.6
15 * Use separate card based DMA buffer for p
16 * 0.0.7
17 * Change remove and rename ctrls into list
18 * 0.0.8
19 * Try to fix capture sources.
20 * 0.0.9
21 * Fix AC3 output.
22 * Enable S32_LE format support.
23 * 0.0.10
24 * Enable playback 48000 and 96000 rates. (
25 * 0.0.11
26 * Add Model name recognition.
27 * 0.0.12
28 * Correct interrupt timing. interrupt at e
29 * Remove redundent "voice" handling.
30 * 0.0.13
31 * Single trigger call for multi channels.
32 * 0.0.14
33 * Set limits based on what the sound card
34 * playback periods_min=2, periods_max=8
35 * capture hw constraints require period_si
36 * playback hw constraints require period_s
37 * 0.0.15
38 * Separated ca0106.c into separate functio
39 * 0.0.16
40 * Implement 192000 sample rate.
41 * 0.0.17
42 * Add support for SB0410 and SB0413.
43 * 0.0.18
44 * Modified Copyright message.
45 * 0.0.19
46 * Added I2C and SPI registers. Filled in i
47 * 0.0.20
48 * Added GPIO info for SB Live 24bit.
49 * 0.0.21
50 * Implement support for Line-in capture on
51 * 0.0.22
52 * Add support for mute control on SB Live
53 *
54 * This code was initially based on code from
55 * Copyright (c) by Francisco Moraes <fmoraes
56 */
57
58 /*********************************************
59 /* PCI function 0 registers, address = <val> +
60 /*********************************************
61
62 #define CA0106_PTR 0x00
63
64
65
66
67 #define CA0106_DATA 0x04
68
69
70 #define CA0106_IPR 0x08
71
72
73 #define IPR_MIDI_RX_B 0x00020000
74 #define IPR_MIDI_TX_B 0x00010000
75 #define IPR_SPDIF_IN_USER 0x00004000
76 #define IPR_SPDIF_OUT_USER 0x00002000
77 #define IPR_SPDIF_OUT_FRAME 0x00001000
78 #define IPR_SPI 0x00000800
79 #define IPR_I2C_EEPROM 0x00000400
80 #define IPR_I2C_DAC 0x00000200
81 #define IPR_AI 0x00000100
82 #define IPR_GPI 0x00000080
83 #define IPR_SRC_LOCKED 0x00000040
84 #define IPR_SPDIF_STATUS 0x00000020
85 #define IPR_TIMER2 0x00000010
86 #define IPR_TIMER1 0x00000008
87 #define IPR_MIDI_RX_A 0x00000004
88 #define IPR_MIDI_TX_A 0x00000002
89 #define IPR_PCI 0x00000001
90
91 #define CA0106_INTE 0x0c
92
93 #define INTE_MIDI_RX_B 0x00020000
94 #define INTE_MIDI_TX_B 0x00010000
95 #define INTE_SPDIF_IN_USER 0x00004000
96 #define INTE_SPDIF_OUT_USER 0x00002000
97 #define INTE_SPDIF_OUT_FRAME 0x00001000
98 #define INTE_SPI 0x00000800
99 #define INTE_I2C_EEPROM 0x00000400
100 #define INTE_I2C_DAC 0x00000200
101 #define INTE_AI 0x00000100
102 #define INTE_GPI 0x00000080
103 #define INTE_SRC_LOCKED 0x00000040
104 #define INTE_SPDIF_STATUS 0x00000020
105 #define INTE_TIMER2 0x00000010
106 #define INTE_TIMER1 0x00000008
107 #define INTE_MIDI_RX_A 0x00000004
108 #define INTE_MIDI_TX_A 0x00000002
109 #define INTE_PCI 0x00000001
110
111 #define CA0106_UNKNOWN10 0x10
112 #define CA0106_HCFG 0x14
113
114
115 #define HCFG_STAC 0x10000000
116 #define HCFG_CAPTURE_I2S_BYPASS 0x08000000
117 #define HCFG_CAPTURE_SPDIF_BYPASS 0x04000000
118 #define HCFG_PLAYBACK_I2S_BYPASS 0x02000000
119 #define HCFG_FORCE_LOCK 0x01000000
120 #define HCFG_PLAYBACK_ATTENUATION 0x00006000
121 #define HCFG_PLAYBACK_DITHER 0x00001000
122 #define HCFG_PLAYBACK_S32_LE 0x00000800
123 #define HCFG_CAPTURE_S32_LE 0x00000400
124 #define HCFG_8_CHANNEL_PLAY 0x00000200
125 #define HCFG_8_CHANNEL_CAPTURE 0x00000100
126 #define HCFG_MONO 0x00000080
127 #define HCFG_I2S_OUTPUT 0x00000010
128 #define HCFG_AC97 0x00000008
129 #define HCFG_LOCK_PLAYBACK_CACHE 0x00000004
130
131 #define HCFG_LOCK_CAPTURE_CACHE 0x00000002
132
133 #define HCFG_AUDIOENABLE 0x00000001
134
135
136 #define CA0106_GPIO 0x18
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155 #define CA0106_AC97DATA 0x1c
156
157 #define CA0106_AC97ADDRESS 0x1e
158
159 /*********************************************
160 /* CA0106 pointer-offset register set, accesse
161 /*********************************************
162
163 /* Initially all registers from 0x00 to 0x3f h
164 #define PLAYBACK_LIST_ADDR 0x00
165
166
167
168
169
170
171 #define PLAYBACK_LIST_SIZE 0x01
172
173 #define PLAYBACK_LIST_PTR 0x02
174
175 #define PLAYBACK_UNKNOWN3 0x03
176 #define PLAYBACK_DMA_ADDR 0x04
177
178 #define PLAYBACK_PERIOD_SIZE 0x05
179
180 #define PLAYBACK_POINTER 0x06
181
182 #define PLAYBACK_PERIOD_END_ADDR 0x07
183
184 #define PLAYBACK_FIFO_OFFSET_ADDRESS 0x08
185
186 #define PLAYBACK_UNKNOWN9 0x09
187 #define CAPTURE_DMA_ADDR 0x10
188
189 #define CAPTURE_BUFFER_SIZE 0x11
190
191 #define CAPTURE_POINTER 0x12
192
193 #define CAPTURE_FIFO_OFFSET_ADDRESS 0x13
194
195 #define PLAYBACK_LAST_SAMPLE 0x20
196 /* 0x21 - 0x3f unused */
197 #define BASIC_INTERRUPT 0x40
198
199
200
201
202
203
204
205
206
207 /* The Digital out jack is shared with the Cen
208 * The jack has 4 poles. I will call 1 - Tip,
209 * For Analogue: 1 -> Center Speaker, 2 -> Sub
210 * For Digital: 1 -> Front SPDIF, 2 -> Rear SP
211 * Standard 4 pole Video A/V cable with RCA ou
212 * So, from this you can see that you cannot u
213 */
214 /* The Front SPDIF PCM gets mixed with samples
215 * The Rear SPDIF can be used for Stereo PCM a
216 * The Center/LFE SPDIF cannot be used for AC3
217 * Summary: For ALSA we use the Rear channel f
218 */
219 /* A standard 2 pole mono mini-jack to RCA plu
220 * A standard 3 pole stereo mini-jack to 2 RCA
221 */
222 #define SPCS0 0x41
223 #define SPCS1 0x42
224 #define SPCS2 0x43
225 #define SPCS3 0x44
226
227 #define SPCS_CLKACCYMASK 0x30000000
228 #define SPCS_CLKACCY_1000PPM 0x00000000
229 #define SPCS_CLKACCY_50PPM 0x10000000
230 #define SPCS_CLKACCY_VARIABLE 0x20000000
231 #define SPCS_SAMPLERATEMASK 0x0f000000
232 #define SPCS_SAMPLERATE_44 0x00000000
233 #define SPCS_SAMPLERATE_48 0x02000000
234 #define SPCS_SAMPLERATE_32 0x03000000
235 #define SPCS_CHANNELNUMMASK 0x00f00000
236 #define SPCS_CHANNELNUM_UNSPEC 0x00000000
237 #define SPCS_CHANNELNUM_LEFT 0x00100000
238 #define SPCS_CHANNELNUM_RIGHT 0x00200000
239 #define SPCS_SOURCENUMMASK 0x000f0000
240 #define SPCS_SOURCENUM_UNSPEC 0x00000000
241 #define SPCS_GENERATIONSTATUS 0x00008000
242 #define SPCS_CATEGORYCODEMASK 0x00007f00
243 #define SPCS_MODEMASK 0x000000c0
244 #define SPCS_EMPHASISMASK 0x00000038
245 #define SPCS_EMPHASIS_NONE 0x00000000
246 #define SPCS_EMPHASIS_50_15 0x00000008
247 #define SPCS_COPYRIGHT 0x00000004
248 #define SPCS_NOTAUDIODATA 0x00000002
249 #define SPCS_PROFESSIONAL 0x00000001
250
251
252 #define SPCS_WORD_LENGTH_MASK 0x0000000f
253 #define SPCS_WORD_LENGTH_16 0x00000008
254 #define SPCS_WORD_LENGTH_17 0x00000006
255 #define SPCS_WORD_LENGTH_18 0x00000004
256 #define SPCS_WORD_LENGTH_19 0x00000002
257 #define SPCS_WORD_LENGTH_20A 0x0000000a
258 #define SPCS_WORD_LENGTH_20 0x00000009
259 #define SPCS_WORD_LENGTH_21 0x00000007
260 #define SPCS_WORD_LENGTH_22 0x00000005
261 #define SPCS_WORD_LENGTH_23 0x00000003
262 #define SPCS_WORD_LENGTH_24 0x0000000b
263 #define SPCS_ORIGINAL_SAMPLE_RATE_MASK 0x0000
264 #define SPCS_ORIGINAL_SAMPLE_RATE_NONE 0x0000
265 #define SPCS_ORIGINAL_SAMPLE_RATE_16000 0x0000
266 #define SPCS_ORIGINAL_SAMPLE_RATE_RES1 0x0000
267 #define SPCS_ORIGINAL_SAMPLE_RATE_32000 0x0000
268 #define SPCS_ORIGINAL_SAMPLE_RATE_12000 0x0000
269 #define SPCS_ORIGINAL_SAMPLE_RATE_11025 0x0000
270 #define SPCS_ORIGINAL_SAMPLE_RATE_8000 0x0000
271 #define SPCS_ORIGINAL_SAMPLE_RATE_RES2 0x0000
272 #define SPCS_ORIGINAL_SAMPLE_RATE_192000 0x000
273 #define SPCS_ORIGINAL_SAMPLE_RATE_24000 0x0000
274 #define SPCS_ORIGINAL_SAMPLE_RATE_96000 0x0000
275 #define SPCS_ORIGINAL_SAMPLE_RATE_48000 0x0000
276 #define SPCS_ORIGINAL_SAMPLE_RATE_176400 0x000
277 #define SPCS_ORIGINAL_SAMPLE_RATE_22050 0x0000
278 #define SPCS_ORIGINAL_SAMPLE_RATE_88200 0x0000
279 #define SPCS_ORIGINAL_SAMPLE_RATE_44100 0x0000
280
281 #define SPDIF_SELECT1 0x45
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304 #define WATERMARK 0x46
305 #define SPDIF_INPUT_STATUS 0x49
306
307
308
309
310
311
312 #define CAPTURE_CACHE_DATA 0x50
313 #define CAPTURE_SOURCE 0x60
314 #define CAPTURE_SOURCE_CHANNEL0 0xf0000000
315 #define CAPTURE_SOURCE_CHANNEL1 0x0f000000
316 #define CAPTURE_SOURCE_CHANNEL2 0x00f00000
317 #define CAPTURE_SOURCE_CHANNEL3 0x000f0000
318 #define CAPTURE_SOURCE_RECORD_MAP 0x0000ffff
319
320
321
322
323
324
325
326
327
328
329
330
331 #define CAPTURE_VOLUME1 0x61
332 #define CAPTURE_VOLUME2 0x62
333
334 #define PLAYBACK_ROUTING1 0x63
335 #define ROUTING1_REAR 0x77000000
336 #define ROUTING1_NULL 0x00770000
337 #define ROUTING1_CENTER_LFE 0x00007700
338 #define ROUTING1_FRONT 0x00000077
339
340
341
342
343
344
345
346
347
348
349
350
351 #define PLAYBACK_ROUTING2 0x64
352
353
354
355
356
357
358
359
360
361
362
363 #define PLAYBACK_MUTE 0x65
364
365
366
367
368
369
370 #define PLAYBACK_VOLUME1 0x66
371
372
373
374
375
376
377
378
379 #define CAPTURE_ROUTING1 0x67
380
381 #define CAPTURE_ROUTING2 0x68
382
383 #define CAPTURE_MUTE 0x69
384
385 #define PLAYBACK_VOLUME2 0x6a
386
387 #define UNKNOWN6b 0x6b
388 #define MIDI_UART_A_DATA 0x6c
389 #define MIDI_UART_A_CMD 0x6d
390 #define MIDI_UART_B_DATA 0x6e
391 #define MIDI_UART_B_CMD 0x6f
392
393 /* unique channel identifier for midi->channel
394
395 #define CA0106_MIDI_CHAN_A 0x1
396 #define CA0106_MIDI_CHAN_B 0x2
397
398 /* from mpu401 */
399
400 #define CA0106_MIDI_INPUT_AVAIL 0x80
401 #define CA0106_MIDI_OUTPUT_READY 0x40
402 #define CA0106_MPU401_RESET 0xff
403 #define CA0106_MPU401_ENTER_UART 0x3f
404 #define CA0106_MPU401_ACK 0xfe
405
406 #define SAMPLE_RATE_TRACKER_STATUS 0x70
407
408
409
410
411
412 #define CAPTURE_CONTROL 0x71
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447 #define SPDIF_SELECT2 0x72
448 #define ROUTING2_FRONT_MASK 0x00010000
449 #define ROUTING2_CENTER_LFE_MASK 0x00020000
450 #define ROUTING2_REAR_MASK 0x00080000
451
452
453
454
455
456 #define UNKNOWN73 0x73
457 #define CHIP_VERSION 0x74
458 #define EXTENDED_INT_MASK 0x75
459
460
461
462
463
464
465
466
467
468
469
470
471 #define EXTENDED_INT 0x76
472
473
474 #define COUNTER77 0x77
475 #define COUNTER78 0x78
476 #define EXTENDED_INT_TIMER 0x79
477
478 #define SPI 0x7a
479 #define I2C_A 0x7b
480 #define I2C_D0 0x7c
481 #define I2C_D1 0x7d
482 //I2C values
483 #define I2C_A_ADC_ADD_MASK 0x000000fe
484 #define I2C_A_ADC_RW_MASK 0x00000001
485 #define I2C_A_ADC_TRANS_MASK 0x00000010
486 #define I2C_A_ADC_ABORT_MASK 0x00000020
487 #define I2C_A_ADC_LAST_MASK 0x00000040
488 #define I2C_A_ADC_BYTE_MASK 0x00000080
489
490 #define I2C_A_ADC_ADD 0x00000034
491 #define I2C_A_ADC_READ 0x00000001
492 #define I2C_A_ADC_START 0x00000100
493 #define I2C_A_ADC_ABORT 0x00000200
494 #define I2C_A_ADC_LAST 0x00000400
495 #define I2C_A_ADC_BYTE 0x00000800
496
497 #define I2C_D_ADC_REG_MASK 0xfe000000
498 #define I2C_D_ADC_DAT_MASK 0x01ff0000
499
500 #define ADC_TIMEOUT 0x00000007
501 #define ADC_IFC_CTRL 0x0000000b
502 #define ADC_MASTER 0x0000000c
503 #define ADC_POWER 0x0000000d
504 #define ADC_ATTEN_ADCL 0x0000000e
505 #define ADC_ATTEN_ADCR 0x0000000f
506 #define ADC_ALC_CTRL1 0x00000010
507 #define ADC_ALC_CTRL2 0x00000011
508 #define ADC_ALC_CTRL3 0x00000012
509 #define ADC_NOISE_CTRL 0x00000013
510 #define ADC_LIMIT_CTRL 0x00000014
511 #define ADC_MUX 0x00000015
512
513 #if 0
514 /* FIXME: Not tested yet. */
515 #define ADC_GAIN_MASK 0x000000ff
516 #define ADC_ZERODB 0x000000cf
517 #define ADC_MUTE_MASK 0x000000c0
518 #define ADC_MUTE 0x000000c0
519 #define ADC_OSR 0x00000008
520 #define ADC_TIMEOUT_DISABLE 0x00000008
521 #define ADC_HPF_DISABLE 0x00000100
522 #define ADC_TRANWIN_MASK 0x00000070
523 #endif
524
525 #define ADC_MUX_MASK 0x0000000f
526 #define ADC_MUX_PHONE 0x00000001
527 #define ADC_MUX_MIC 0x00000002
528 #define ADC_MUX_LINEIN 0x00000004
529 #define ADC_MUX_AUX 0x00000008
530
531 #define SET_CHANNEL 0 /* Testing channel outp
532 #define PCM_FRONT_CHANNEL 0
533 #define PCM_REAR_CHANNEL 1
534 #define PCM_CENTER_LFE_CHANNEL 2
535 #define PCM_UNKNOWN_CHANNEL 3
536 #define CONTROL_FRONT_CHANNEL 0
537 #define CONTROL_REAR_CHANNEL 3
538 #define CONTROL_CENTER_LFE_CHANNEL 1
539 #define CONTROL_UNKNOWN_CHANNEL 2
540
541
542 /* Based on WM8768 Datasheet Rev 4.2 page 32 *
543 #define SPI_REG_MASK 0x1ff /* 16-bit SPI
544 #define SPI_REG_SHIFT 9 /* followed by
545
546 #define SPI_LDA1_REG 0 /* dig
547 #define SPI_RDA1_REG 1
548 #define SPI_LDA2_REG 4
549 #define SPI_RDA2_REG 5
550 #define SPI_LDA3_REG 6
551 #define SPI_RDA3_REG 7
552 #define SPI_LDA4_REG 13
553 #define SPI_RDA4_REG 14
554 #define SPI_MASTDA_REG 8
555
556 #define SPI_DA_BIT_UPDATE (1<<8) /* upd
557 #define SPI_DA_BIT_0dB 0xff /* 0 d
558 #define SPI_DA_BIT_infdB 0x00 /* inf
559
560 #define SPI_PL_REG 2
561 #define SPI_PL_BIT_L_M (0<<5) /* lef
562 #define SPI_PL_BIT_L_L (1<<5) /* lef
563 #define SPI_PL_BIT_L_R (2<<5) /* lef
564 #define SPI_PL_BIT_L_C (3<<5) /* lef
565 #define SPI_PL_BIT_R_M (0<<7) /* rig
566 #define SPI_PL_BIT_R_L (1<<7) /* rig
567 #define SPI_PL_BIT_R_R (2<<7) /* rig
568 #define SPI_PL_BIT_R_C (3<<7) /* rig
569 #define SPI_IZD_REG 2
570 #define SPI_IZD_BIT (0<<4) /* inf
571
572 #define SPI_FMT_REG 3
573 #define SPI_FMT_BIT_RJ (0<<0) /* rig
574 #define SPI_FMT_BIT_LJ (1<<0) /* lef
575 #define SPI_FMT_BIT_I2S (2<<0) /* I2S
576 #define SPI_FMT_BIT_DSP (3<<0) /* DSP
577 #define SPI_LRP_REG 3
578 #define SPI_LRP_BIT (1<<2) /* inv
579 #define SPI_BCP_REG 3
580 #define SPI_BCP_BIT (1<<3) /* inv
581 #define SPI_IWL_REG 3
582 #define SPI_IWL_BIT_16 (0<<4) /* 16-
583 #define SPI_IWL_BIT_20 (1<<4) /* 20-
584 #define SPI_IWL_BIT_24 (2<<4) /* 24-
585 #define SPI_IWL_BIT_32 (3<<4) /* 32-
586
587 #define SPI_MS_REG 10
588 #define SPI_MS_BIT (1<<5) /* mas
589 #define SPI_RATE_REG 10 /* onl
590 #define SPI_RATE_BIT_128 (0<<6) /* MCL
591 #define SPI_RATE_BIT_192 (1<<6)
592 #define SPI_RATE_BIT_256 (2<<6)
593 #define SPI_RATE_BIT_384 (3<<6)
594 #define SPI_RATE_BIT_512 (4<<6)
595 #define SPI_RATE_BIT_768 (5<<6)
596
597 /* They really do label the bit for the 4th ch
598 #define SPI_DMUTE0_REG 9
599 #define SPI_DMUTE1_REG 9
600 #define SPI_DMUTE2_REG 9
601 #define SPI_DMUTE4_REG 15
602 #define SPI_DMUTE0_BIT (1<<3)
603 #define SPI_DMUTE1_BIT (1<<4)
604 #define SPI_DMUTE2_BIT (1<<5)
605 #define SPI_DMUTE4_BIT (1<<2)
606
607 #define SPI_PHASE0_REG 3
608 #define SPI_PHASE1_REG 3
609 #define SPI_PHASE2_REG 3
610 #define SPI_PHASE4_REG 15
611 #define SPI_PHASE0_BIT (1<<6)
612 #define SPI_PHASE1_BIT (1<<7)
613 #define SPI_PHASE2_BIT (1<<8)
614 #define SPI_PHASE4_BIT (1<<3)
615
616 #define SPI_PDWN_REG 2 /* pow
617 #define SPI_PDWN_BIT (1<<2)
618 #define SPI_DACD0_REG 10 /* pow
619 #define SPI_DACD1_REG 10
620 #define SPI_DACD2_REG 10
621 #define SPI_DACD4_REG 15
622 #define SPI_DACD0_BIT (1<<1)
623 #define SPI_DACD1_BIT (1<<2)
624 #define SPI_DACD2_BIT (1<<3)
625 #define SPI_DACD4_BIT (1<<0) /* dat
626
627 #define SPI_PWRDNALL_REG 10 /* pow
628 #define SPI_PWRDNALL_BIT (1<<4)
629
630 #include "ca_midi.h"
631
632 struct snd_ca0106;
633
634 struct snd_ca0106_channel {
635 struct snd_ca0106 *emu;
636 int number;
637 int use;
638 void (*interrupt)(struct snd_ca0106 *e
639 struct snd_ca0106_pcm *epcm;
640 };
641
642 struct snd_ca0106_pcm {
643 struct snd_ca0106 *emu;
644 struct snd_pcm_substream *substream;
645 int channel_id;
646 unsigned short running;
647 };
648
649 struct snd_ca0106_details {
650 u32 serial;
651 char * name;
652 int ac97; /* ac97 = 0 -> Select
653 ac97 = 1 -> Default
654 int gpio_type; /* gpio_type = 1 -> sh
655 gpio_type = 2 -> sh
656 int i2c_adc; /* with i2c_adc=1, the
657 controls, phone, mi
658 u16 spi_dac; /* spi_dac = 0 -> no s
659 spi_dac = 0x<front>
660 -> specifies DAC id
661 };
662
663 // definition of the chip-specific record
664 struct snd_ca0106 {
665 struct snd_card *card;
666 const struct snd_ca0106_details *detai
667 struct pci_dev *pci;
668
669 unsigned long port;
670 int irq;
671
672 unsigned int serial; /* ser
673 unsigned short model; /* sub
674
675 spinlock_t emu_lock;
676
677 struct snd_ac97 *ac97;
678 struct snd_pcm *pcm[4];
679
680 struct snd_ca0106_channel playback_cha
681 struct snd_ca0106_channel capture_chan
682 u32 spdif_bits[4]; /* s/pd
683 u32 spdif_str_bits[4]; /* s/pd
684 int spdif_enable;
685 int capture_source;
686 int i2c_capture_source;
687 u8 i2c_capture_volume[4][2];
688 int capture_mic_line_in;
689
690 struct snd_dma_buffer *buffer;
691
692 struct snd_ca_midi midi;
693 struct snd_ca_midi midi2;
694
695 u16 spi_dac_reg[16];
696
697 #ifdef CONFIG_PM_SLEEP
698 #define NUM_SAVED_VOLUMES 9
699 unsigned int saved_vol[NUM_SAVED_VOLUM
700 #endif
701 };
702
703 int snd_ca0106_mixer(struct snd_ca0106 *emu);
704 int snd_ca0106_proc_init(struct snd_ca0106 * e
705
706 unsigned int snd_ca0106_ptr_read(struct snd_ca
707 unsigned int
708 unsigned int
709
710 void snd_ca0106_ptr_write(struct snd_ca0106 *e
711 unsigned int reg,
712 unsigned int chn,
713 unsigned int data);
714
715 int snd_ca0106_i2c_write(struct snd_ca0106 *em
716
717 int snd_ca0106_spi_write(struct snd_ca0106 * e
718 unsigned in
719
720 #ifdef CONFIG_PM_SLEEP
721 void snd_ca0106_mixer_suspend(struct snd_ca010
722 void snd_ca0106_mixer_resume(struct snd_ca0106
723 #else
724 #define snd_ca0106_mixer_suspend(chip) do { }
725 #define snd_ca0106_mixer_resume(chip) do { }
726 #endif
727
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.