1 // SPDX-License-Identifier: GPL-2.0-only !! 1 /**
2 /* <<
3 * Copyright (C) 2008, Creative Technology Ltd 2 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
4 * 3 *
>> 4 * This source file is released under GPL v2 license (no other versions).
>> 5 * See the COPYING file included in the main directory of this source
>> 6 * distribution for the license terms and conditions.
>> 7 *
5 * @File cthw20k1.c 8 * @File cthw20k1.c
6 * 9 *
7 * @Brief 10 * @Brief
8 * This file contains the implementation of ha 11 * This file contains the implementation of hardware access methord for 20k1.
9 * 12 *
10 * @Author Liu Chun 13 * @Author Liu Chun
11 * @Date Jun 24 2008 14 * @Date Jun 24 2008
>> 15 *
12 */ 16 */
13 17
14 #include <linux/types.h> 18 #include <linux/types.h>
15 #include <linux/slab.h> 19 #include <linux/slab.h>
16 #include <linux/pci.h> 20 #include <linux/pci.h>
17 #include <linux/io.h> 21 #include <linux/io.h>
18 #include <linux/string.h> 22 #include <linux/string.h>
19 #include <linux/spinlock.h> 23 #include <linux/spinlock.h>
20 #include <linux/kernel.h> 24 #include <linux/kernel.h>
21 #include <linux/interrupt.h> 25 #include <linux/interrupt.h>
22 #include <linux/delay.h> 26 #include <linux/delay.h>
23 #include "cthw20k1.h" 27 #include "cthw20k1.h"
24 #include "ct20k1reg.h" 28 #include "ct20k1reg.h"
25 29
26 struct hw20k1 { 30 struct hw20k1 {
27 struct hw hw; 31 struct hw hw;
28 spinlock_t reg_20k1_lock; 32 spinlock_t reg_20k1_lock;
29 spinlock_t reg_pci_lock; 33 spinlock_t reg_pci_lock;
30 }; 34 };
31 35
32 static u32 hw_read_20kx(struct hw *hw, u32 reg 36 static u32 hw_read_20kx(struct hw *hw, u32 reg);
33 static void hw_write_20kx(struct hw *hw, u32 r 37 static void hw_write_20kx(struct hw *hw, u32 reg, u32 data);
34 static u32 hw_read_pci(struct hw *hw, u32 reg) 38 static u32 hw_read_pci(struct hw *hw, u32 reg);
35 static void hw_write_pci(struct hw *hw, u32 re 39 static void hw_write_pci(struct hw *hw, u32 reg, u32 data);
36 40
37 /* 41 /*
38 * Type definition block. 42 * Type definition block.
39 * The layout of control structures can be dir 43 * The layout of control structures can be directly applied on 20k2 chip.
40 */ 44 */
41 45
42 /* 46 /*
43 * SRC control block definitions. 47 * SRC control block definitions.
44 */ 48 */
45 49
46 /* SRC resource control block */ 50 /* SRC resource control block */
47 #define SRCCTL_STATE 0x00000007 51 #define SRCCTL_STATE 0x00000007
48 #define SRCCTL_BM 0x00000008 52 #define SRCCTL_BM 0x00000008
49 #define SRCCTL_RSR 0x00000030 53 #define SRCCTL_RSR 0x00000030
50 #define SRCCTL_SF 0x000001C0 54 #define SRCCTL_SF 0x000001C0
51 #define SRCCTL_WR 0x00000200 55 #define SRCCTL_WR 0x00000200
52 #define SRCCTL_PM 0x00000400 56 #define SRCCTL_PM 0x00000400
53 #define SRCCTL_ROM 0x00001800 57 #define SRCCTL_ROM 0x00001800
54 #define SRCCTL_VO 0x00002000 58 #define SRCCTL_VO 0x00002000
55 #define SRCCTL_ST 0x00004000 59 #define SRCCTL_ST 0x00004000
56 #define SRCCTL_IE 0x00008000 60 #define SRCCTL_IE 0x00008000
57 #define SRCCTL_ILSZ 0x000F0000 61 #define SRCCTL_ILSZ 0x000F0000
58 #define SRCCTL_BP 0x00100000 62 #define SRCCTL_BP 0x00100000
59 63
60 #define SRCCCR_CISZ 0x000007FF 64 #define SRCCCR_CISZ 0x000007FF
61 #define SRCCCR_CWA 0x001FF800 65 #define SRCCCR_CWA 0x001FF800
62 #define SRCCCR_D 0x00200000 66 #define SRCCCR_D 0x00200000
63 #define SRCCCR_RS 0x01C00000 67 #define SRCCCR_RS 0x01C00000
64 #define SRCCCR_NAL 0x3E000000 68 #define SRCCCR_NAL 0x3E000000
65 #define SRCCCR_RA 0xC0000000 69 #define SRCCCR_RA 0xC0000000
66 70
67 #define SRCCA_CA 0x03FFFFFF 71 #define SRCCA_CA 0x03FFFFFF
68 #define SRCCA_RS 0x1C000000 72 #define SRCCA_RS 0x1C000000
69 #define SRCCA_NAL 0xE0000000 73 #define SRCCA_NAL 0xE0000000
70 74
71 #define SRCSA_SA 0x03FFFFFF 75 #define SRCSA_SA 0x03FFFFFF
72 76
73 #define SRCLA_LA 0x03FFFFFF 77 #define SRCLA_LA 0x03FFFFFF
74 78
75 /* Mixer Parameter Ring ram Low and Hight regi 79 /* Mixer Parameter Ring ram Low and Hight register.
76 * Fixed-point value in 8.24 format for parame 80 * Fixed-point value in 8.24 format for parameter channel */
77 #define MPRLH_PITCH 0xFFFFFFFF 81 #define MPRLH_PITCH 0xFFFFFFFF
78 82
79 /* SRC resource register dirty flags */ 83 /* SRC resource register dirty flags */
80 union src_dirty { 84 union src_dirty {
81 struct { 85 struct {
82 u16 ctl:1; 86 u16 ctl:1;
83 u16 ccr:1; 87 u16 ccr:1;
84 u16 sa:1; 88 u16 sa:1;
85 u16 la:1; 89 u16 la:1;
86 u16 ca:1; 90 u16 ca:1;
87 u16 mpr:1; 91 u16 mpr:1;
88 u16 czbfs:1; /* Clear Z-Buf 92 u16 czbfs:1; /* Clear Z-Buffers */
89 u16 rsv:9; 93 u16 rsv:9;
90 } bf; 94 } bf;
91 u16 data; 95 u16 data;
92 }; 96 };
93 97
94 struct src_rsc_ctrl_blk { 98 struct src_rsc_ctrl_blk {
95 unsigned int ctl; 99 unsigned int ctl;
96 unsigned int ccr; 100 unsigned int ccr;
97 unsigned int ca; 101 unsigned int ca;
98 unsigned int sa; 102 unsigned int sa;
99 unsigned int la; 103 unsigned int la;
100 unsigned int mpr; 104 unsigned int mpr;
101 union src_dirty dirty; 105 union src_dirty dirty;
102 }; 106 };
103 107
104 /* SRC manager control block */ 108 /* SRC manager control block */
105 union src_mgr_dirty { 109 union src_mgr_dirty {
106 struct { 110 struct {
107 u16 enb0:1; 111 u16 enb0:1;
108 u16 enb1:1; 112 u16 enb1:1;
109 u16 enb2:1; 113 u16 enb2:1;
110 u16 enb3:1; 114 u16 enb3:1;
111 u16 enb4:1; 115 u16 enb4:1;
112 u16 enb5:1; 116 u16 enb5:1;
113 u16 enb6:1; 117 u16 enb6:1;
114 u16 enb7:1; 118 u16 enb7:1;
115 u16 enbsa:1; 119 u16 enbsa:1;
116 u16 rsv:7; 120 u16 rsv:7;
117 } bf; 121 } bf;
118 u16 data; 122 u16 data;
119 }; 123 };
120 124
121 struct src_mgr_ctrl_blk { 125 struct src_mgr_ctrl_blk {
122 unsigned int enbsa; 126 unsigned int enbsa;
123 unsigned int enb[8]; 127 unsigned int enb[8];
124 union src_mgr_dirty dirty; 128 union src_mgr_dirty dirty;
125 }; 129 };
126 130
127 /* SRCIMP manager control block */ 131 /* SRCIMP manager control block */
128 #define SRCAIM_ARC 0x00000FFF 132 #define SRCAIM_ARC 0x00000FFF
129 #define SRCAIM_NXT 0x00FF0000 133 #define SRCAIM_NXT 0x00FF0000
130 #define SRCAIM_SRC 0xFF000000 134 #define SRCAIM_SRC 0xFF000000
131 135
132 struct srcimap { 136 struct srcimap {
133 unsigned int srcaim; 137 unsigned int srcaim;
134 unsigned int idx; 138 unsigned int idx;
135 }; 139 };
136 140
137 /* SRCIMP manager register dirty flags */ 141 /* SRCIMP manager register dirty flags */
138 union srcimp_mgr_dirty { 142 union srcimp_mgr_dirty {
139 struct { 143 struct {
140 u16 srcimap:1; 144 u16 srcimap:1;
141 u16 rsv:15; 145 u16 rsv:15;
142 } bf; 146 } bf;
143 u16 data; 147 u16 data;
144 }; 148 };
145 149
146 struct srcimp_mgr_ctrl_blk { 150 struct srcimp_mgr_ctrl_blk {
147 struct srcimap srcimap; 151 struct srcimap srcimap;
148 union srcimp_mgr_dirty dirty; 152 union srcimp_mgr_dirty dirty;
149 }; 153 };
150 154
151 /* 155 /*
152 * Function implementation block. 156 * Function implementation block.
153 */ 157 */
154 158
155 static int src_get_rsc_ctrl_blk(void **rblk) 159 static int src_get_rsc_ctrl_blk(void **rblk)
156 { 160 {
157 struct src_rsc_ctrl_blk *blk; 161 struct src_rsc_ctrl_blk *blk;
158 162
159 *rblk = NULL; 163 *rblk = NULL;
160 blk = kzalloc(sizeof(*blk), GFP_KERNEL 164 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
161 if (!blk) 165 if (!blk)
162 return -ENOMEM; 166 return -ENOMEM;
163 167
164 *rblk = blk; 168 *rblk = blk;
165 169
166 return 0; 170 return 0;
167 } 171 }
168 172
169 static int src_put_rsc_ctrl_blk(void *blk) 173 static int src_put_rsc_ctrl_blk(void *blk)
170 { 174 {
171 kfree(blk); !! 175 kfree((struct src_rsc_ctrl_blk *)blk);
172 176
173 return 0; 177 return 0;
174 } 178 }
175 179
176 static int src_set_state(void *blk, unsigned i 180 static int src_set_state(void *blk, unsigned int state)
177 { 181 {
178 struct src_rsc_ctrl_blk *ctl = blk; 182 struct src_rsc_ctrl_blk *ctl = blk;
179 183
180 set_field(&ctl->ctl, SRCCTL_STATE, sta 184 set_field(&ctl->ctl, SRCCTL_STATE, state);
181 ctl->dirty.bf.ctl = 1; 185 ctl->dirty.bf.ctl = 1;
182 return 0; 186 return 0;
183 } 187 }
184 188
185 static int src_set_bm(void *blk, unsigned int 189 static int src_set_bm(void *blk, unsigned int bm)
186 { 190 {
187 struct src_rsc_ctrl_blk *ctl = blk; 191 struct src_rsc_ctrl_blk *ctl = blk;
188 192
189 set_field(&ctl->ctl, SRCCTL_BM, bm); 193 set_field(&ctl->ctl, SRCCTL_BM, bm);
190 ctl->dirty.bf.ctl = 1; 194 ctl->dirty.bf.ctl = 1;
191 return 0; 195 return 0;
192 } 196 }
193 197
194 static int src_set_rsr(void *blk, unsigned int 198 static int src_set_rsr(void *blk, unsigned int rsr)
195 { 199 {
196 struct src_rsc_ctrl_blk *ctl = blk; 200 struct src_rsc_ctrl_blk *ctl = blk;
197 201
198 set_field(&ctl->ctl, SRCCTL_RSR, rsr); 202 set_field(&ctl->ctl, SRCCTL_RSR, rsr);
199 ctl->dirty.bf.ctl = 1; 203 ctl->dirty.bf.ctl = 1;
200 return 0; 204 return 0;
201 } 205 }
202 206
203 static int src_set_sf(void *blk, unsigned int 207 static int src_set_sf(void *blk, unsigned int sf)
204 { 208 {
205 struct src_rsc_ctrl_blk *ctl = blk; 209 struct src_rsc_ctrl_blk *ctl = blk;
206 210
207 set_field(&ctl->ctl, SRCCTL_SF, sf); 211 set_field(&ctl->ctl, SRCCTL_SF, sf);
208 ctl->dirty.bf.ctl = 1; 212 ctl->dirty.bf.ctl = 1;
209 return 0; 213 return 0;
210 } 214 }
211 215
212 static int src_set_wr(void *blk, unsigned int 216 static int src_set_wr(void *blk, unsigned int wr)
213 { 217 {
214 struct src_rsc_ctrl_blk *ctl = blk; 218 struct src_rsc_ctrl_blk *ctl = blk;
215 219
216 set_field(&ctl->ctl, SRCCTL_WR, wr); 220 set_field(&ctl->ctl, SRCCTL_WR, wr);
217 ctl->dirty.bf.ctl = 1; 221 ctl->dirty.bf.ctl = 1;
218 return 0; 222 return 0;
219 } 223 }
220 224
221 static int src_set_pm(void *blk, unsigned int 225 static int src_set_pm(void *blk, unsigned int pm)
222 { 226 {
223 struct src_rsc_ctrl_blk *ctl = blk; 227 struct src_rsc_ctrl_blk *ctl = blk;
224 228
225 set_field(&ctl->ctl, SRCCTL_PM, pm); 229 set_field(&ctl->ctl, SRCCTL_PM, pm);
226 ctl->dirty.bf.ctl = 1; 230 ctl->dirty.bf.ctl = 1;
227 return 0; 231 return 0;
228 } 232 }
229 233
230 static int src_set_rom(void *blk, unsigned int 234 static int src_set_rom(void *blk, unsigned int rom)
231 { 235 {
232 struct src_rsc_ctrl_blk *ctl = blk; 236 struct src_rsc_ctrl_blk *ctl = blk;
233 237
234 set_field(&ctl->ctl, SRCCTL_ROM, rom); 238 set_field(&ctl->ctl, SRCCTL_ROM, rom);
235 ctl->dirty.bf.ctl = 1; 239 ctl->dirty.bf.ctl = 1;
236 return 0; 240 return 0;
237 } 241 }
238 242
239 static int src_set_vo(void *blk, unsigned int 243 static int src_set_vo(void *blk, unsigned int vo)
240 { 244 {
241 struct src_rsc_ctrl_blk *ctl = blk; 245 struct src_rsc_ctrl_blk *ctl = blk;
242 246
243 set_field(&ctl->ctl, SRCCTL_VO, vo); 247 set_field(&ctl->ctl, SRCCTL_VO, vo);
244 ctl->dirty.bf.ctl = 1; 248 ctl->dirty.bf.ctl = 1;
245 return 0; 249 return 0;
246 } 250 }
247 251
248 static int src_set_st(void *blk, unsigned int 252 static int src_set_st(void *blk, unsigned int st)
249 { 253 {
250 struct src_rsc_ctrl_blk *ctl = blk; 254 struct src_rsc_ctrl_blk *ctl = blk;
251 255
252 set_field(&ctl->ctl, SRCCTL_ST, st); 256 set_field(&ctl->ctl, SRCCTL_ST, st);
253 ctl->dirty.bf.ctl = 1; 257 ctl->dirty.bf.ctl = 1;
254 return 0; 258 return 0;
255 } 259 }
256 260
257 static int src_set_ie(void *blk, unsigned int 261 static int src_set_ie(void *blk, unsigned int ie)
258 { 262 {
259 struct src_rsc_ctrl_blk *ctl = blk; 263 struct src_rsc_ctrl_blk *ctl = blk;
260 264
261 set_field(&ctl->ctl, SRCCTL_IE, ie); 265 set_field(&ctl->ctl, SRCCTL_IE, ie);
262 ctl->dirty.bf.ctl = 1; 266 ctl->dirty.bf.ctl = 1;
263 return 0; 267 return 0;
264 } 268 }
265 269
266 static int src_set_ilsz(void *blk, unsigned in 270 static int src_set_ilsz(void *blk, unsigned int ilsz)
267 { 271 {
268 struct src_rsc_ctrl_blk *ctl = blk; 272 struct src_rsc_ctrl_blk *ctl = blk;
269 273
270 set_field(&ctl->ctl, SRCCTL_ILSZ, ilsz 274 set_field(&ctl->ctl, SRCCTL_ILSZ, ilsz);
271 ctl->dirty.bf.ctl = 1; 275 ctl->dirty.bf.ctl = 1;
272 return 0; 276 return 0;
273 } 277 }
274 278
275 static int src_set_bp(void *blk, unsigned int 279 static int src_set_bp(void *blk, unsigned int bp)
276 { 280 {
277 struct src_rsc_ctrl_blk *ctl = blk; 281 struct src_rsc_ctrl_blk *ctl = blk;
278 282
279 set_field(&ctl->ctl, SRCCTL_BP, bp); 283 set_field(&ctl->ctl, SRCCTL_BP, bp);
280 ctl->dirty.bf.ctl = 1; 284 ctl->dirty.bf.ctl = 1;
281 return 0; 285 return 0;
282 } 286 }
283 287
284 static int src_set_cisz(void *blk, unsigned in 288 static int src_set_cisz(void *blk, unsigned int cisz)
285 { 289 {
286 struct src_rsc_ctrl_blk *ctl = blk; 290 struct src_rsc_ctrl_blk *ctl = blk;
287 291
288 set_field(&ctl->ccr, SRCCCR_CISZ, cisz 292 set_field(&ctl->ccr, SRCCCR_CISZ, cisz);
289 ctl->dirty.bf.ccr = 1; 293 ctl->dirty.bf.ccr = 1;
290 return 0; 294 return 0;
291 } 295 }
292 296
293 static int src_set_ca(void *blk, unsigned int 297 static int src_set_ca(void *blk, unsigned int ca)
294 { 298 {
295 struct src_rsc_ctrl_blk *ctl = blk; 299 struct src_rsc_ctrl_blk *ctl = blk;
296 300
297 set_field(&ctl->ca, SRCCA_CA, ca); 301 set_field(&ctl->ca, SRCCA_CA, ca);
298 ctl->dirty.bf.ca = 1; 302 ctl->dirty.bf.ca = 1;
299 return 0; 303 return 0;
300 } 304 }
301 305
302 static int src_set_sa(void *blk, unsigned int 306 static int src_set_sa(void *blk, unsigned int sa)
303 { 307 {
304 struct src_rsc_ctrl_blk *ctl = blk; 308 struct src_rsc_ctrl_blk *ctl = blk;
305 309
306 set_field(&ctl->sa, SRCSA_SA, sa); 310 set_field(&ctl->sa, SRCSA_SA, sa);
307 ctl->dirty.bf.sa = 1; 311 ctl->dirty.bf.sa = 1;
308 return 0; 312 return 0;
309 } 313 }
310 314
311 static int src_set_la(void *blk, unsigned int 315 static int src_set_la(void *blk, unsigned int la)
312 { 316 {
313 struct src_rsc_ctrl_blk *ctl = blk; 317 struct src_rsc_ctrl_blk *ctl = blk;
314 318
315 set_field(&ctl->la, SRCLA_LA, la); 319 set_field(&ctl->la, SRCLA_LA, la);
316 ctl->dirty.bf.la = 1; 320 ctl->dirty.bf.la = 1;
317 return 0; 321 return 0;
318 } 322 }
319 323
320 static int src_set_pitch(void *blk, unsigned i 324 static int src_set_pitch(void *blk, unsigned int pitch)
321 { 325 {
322 struct src_rsc_ctrl_blk *ctl = blk; 326 struct src_rsc_ctrl_blk *ctl = blk;
323 327
324 set_field(&ctl->mpr, MPRLH_PITCH, pitc 328 set_field(&ctl->mpr, MPRLH_PITCH, pitch);
325 ctl->dirty.bf.mpr = 1; 329 ctl->dirty.bf.mpr = 1;
326 return 0; 330 return 0;
327 } 331 }
328 332
329 static int src_set_clear_zbufs(void *blk, unsi 333 static int src_set_clear_zbufs(void *blk, unsigned int clear)
330 { 334 {
331 ((struct src_rsc_ctrl_blk *)blk)->dirt 335 ((struct src_rsc_ctrl_blk *)blk)->dirty.bf.czbfs = (clear ? 1 : 0);
332 return 0; 336 return 0;
333 } 337 }
334 338
335 static int src_set_dirty(void *blk, unsigned i 339 static int src_set_dirty(void *blk, unsigned int flags)
336 { 340 {
337 ((struct src_rsc_ctrl_blk *)blk)->dirt 341 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
338 return 0; 342 return 0;
339 } 343 }
340 344
341 static int src_set_dirty_all(void *blk) 345 static int src_set_dirty_all(void *blk)
342 { 346 {
343 ((struct src_rsc_ctrl_blk *)blk)->dirt 347 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
344 return 0; 348 return 0;
345 } 349 }
346 350
347 #define AR_SLOT_SIZE 4096 351 #define AR_SLOT_SIZE 4096
348 #define AR_SLOT_BLOCK_SIZE 16 352 #define AR_SLOT_BLOCK_SIZE 16
349 #define AR_PTS_PITCH 6 353 #define AR_PTS_PITCH 6
350 #define AR_PARAM_SRC_OFFSET 0x60 354 #define AR_PARAM_SRC_OFFSET 0x60
351 355
352 static unsigned int src_param_pitch_mixer(unsi 356 static unsigned int src_param_pitch_mixer(unsigned int src_idx)
353 { 357 {
354 return ((src_idx << 4) + AR_PTS_PITCH 358 return ((src_idx << 4) + AR_PTS_PITCH + AR_SLOT_SIZE
355 - AR_PARAM_SRC_OFFSET) 359 - AR_PARAM_SRC_OFFSET) % AR_SLOT_SIZE;
356 360
357 } 361 }
358 362
359 static int src_commit_write(struct hw *hw, uns 363 static int src_commit_write(struct hw *hw, unsigned int idx, void *blk)
360 { 364 {
361 struct src_rsc_ctrl_blk *ctl = blk; 365 struct src_rsc_ctrl_blk *ctl = blk;
362 int i; 366 int i;
363 367
364 if (ctl->dirty.bf.czbfs) { 368 if (ctl->dirty.bf.czbfs) {
365 /* Clear Z-Buffer registers */ 369 /* Clear Z-Buffer registers */
366 for (i = 0; i < 8; i++) 370 for (i = 0; i < 8; i++)
367 hw_write_20kx(hw, SRCU 371 hw_write_20kx(hw, SRCUPZ+idx*0x100+i*0x4, 0);
368 372
369 for (i = 0; i < 4; i++) 373 for (i = 0; i < 4; i++)
370 hw_write_20kx(hw, SRCD 374 hw_write_20kx(hw, SRCDN0Z+idx*0x100+i*0x4, 0);
371 375
372 for (i = 0; i < 8; i++) 376 for (i = 0; i < 8; i++)
373 hw_write_20kx(hw, SRCD 377 hw_write_20kx(hw, SRCDN1Z+idx*0x100+i*0x4, 0);
374 378
375 ctl->dirty.bf.czbfs = 0; 379 ctl->dirty.bf.czbfs = 0;
376 } 380 }
377 if (ctl->dirty.bf.mpr) { 381 if (ctl->dirty.bf.mpr) {
378 /* Take the parameter mixer re 382 /* Take the parameter mixer resource in the same group as that
379 * the idx src is in for simpl 383 * the idx src is in for simplicity. Unlike src, all conjugate
380 * parameter mixer resources m 384 * parameter mixer resources must be programmed for
381 * corresponding conjugate src 385 * corresponding conjugate src resources. */
382 unsigned int pm_idx = src_para 386 unsigned int pm_idx = src_param_pitch_mixer(idx);
383 hw_write_20kx(hw, PRING_LO_HI+ 387 hw_write_20kx(hw, PRING_LO_HI+4*pm_idx, ctl->mpr);
384 hw_write_20kx(hw, PMOPLO+8*pm_ 388 hw_write_20kx(hw, PMOPLO+8*pm_idx, 0x3);
385 hw_write_20kx(hw, PMOPHI+8*pm_ 389 hw_write_20kx(hw, PMOPHI+8*pm_idx, 0x0);
386 ctl->dirty.bf.mpr = 0; 390 ctl->dirty.bf.mpr = 0;
387 } 391 }
388 if (ctl->dirty.bf.sa) { 392 if (ctl->dirty.bf.sa) {
389 hw_write_20kx(hw, SRCSA+idx*0x 393 hw_write_20kx(hw, SRCSA+idx*0x100, ctl->sa);
390 ctl->dirty.bf.sa = 0; 394 ctl->dirty.bf.sa = 0;
391 } 395 }
392 if (ctl->dirty.bf.la) { 396 if (ctl->dirty.bf.la) {
393 hw_write_20kx(hw, SRCLA+idx*0x 397 hw_write_20kx(hw, SRCLA+idx*0x100, ctl->la);
394 ctl->dirty.bf.la = 0; 398 ctl->dirty.bf.la = 0;
395 } 399 }
396 if (ctl->dirty.bf.ca) { 400 if (ctl->dirty.bf.ca) {
397 hw_write_20kx(hw, SRCCA+idx*0x 401 hw_write_20kx(hw, SRCCA+idx*0x100, ctl->ca);
398 ctl->dirty.bf.ca = 0; 402 ctl->dirty.bf.ca = 0;
399 } 403 }
400 404
401 /* Write srccf register */ 405 /* Write srccf register */
402 hw_write_20kx(hw, SRCCF+idx*0x100, 0x0 406 hw_write_20kx(hw, SRCCF+idx*0x100, 0x0);
403 407
404 if (ctl->dirty.bf.ccr) { 408 if (ctl->dirty.bf.ccr) {
405 hw_write_20kx(hw, SRCCCR+idx*0 409 hw_write_20kx(hw, SRCCCR+idx*0x100, ctl->ccr);
406 ctl->dirty.bf.ccr = 0; 410 ctl->dirty.bf.ccr = 0;
407 } 411 }
408 if (ctl->dirty.bf.ctl) { 412 if (ctl->dirty.bf.ctl) {
409 hw_write_20kx(hw, SRCCTL+idx*0 413 hw_write_20kx(hw, SRCCTL+idx*0x100, ctl->ctl);
410 ctl->dirty.bf.ctl = 0; 414 ctl->dirty.bf.ctl = 0;
411 } 415 }
412 416
413 return 0; 417 return 0;
414 } 418 }
415 419
416 static int src_get_ca(struct hw *hw, unsigned 420 static int src_get_ca(struct hw *hw, unsigned int idx, void *blk)
417 { 421 {
418 struct src_rsc_ctrl_blk *ctl = blk; 422 struct src_rsc_ctrl_blk *ctl = blk;
419 423
420 ctl->ca = hw_read_20kx(hw, SRCCA+idx*0 424 ctl->ca = hw_read_20kx(hw, SRCCA+idx*0x100);
421 ctl->dirty.bf.ca = 0; 425 ctl->dirty.bf.ca = 0;
422 426
423 return get_field(ctl->ca, SRCCA_CA); 427 return get_field(ctl->ca, SRCCA_CA);
424 } 428 }
425 429
426 static unsigned int src_get_dirty(void *blk) 430 static unsigned int src_get_dirty(void *blk)
427 { 431 {
428 return ((struct src_rsc_ctrl_blk *)blk 432 return ((struct src_rsc_ctrl_blk *)blk)->dirty.data;
429 } 433 }
430 434
431 static unsigned int src_dirty_conj_mask(void) 435 static unsigned int src_dirty_conj_mask(void)
432 { 436 {
433 return 0x20; 437 return 0x20;
434 } 438 }
435 439
436 static int src_mgr_enbs_src(void *blk, unsigne 440 static int src_mgr_enbs_src(void *blk, unsigned int idx)
437 { 441 {
438 ((struct src_mgr_ctrl_blk *)blk)->enbs 442 ((struct src_mgr_ctrl_blk *)blk)->enbsa = ~(0x0);
439 ((struct src_mgr_ctrl_blk *)blk)->dirt 443 ((struct src_mgr_ctrl_blk *)blk)->dirty.bf.enbsa = 1;
440 ((struct src_mgr_ctrl_blk *)blk)->enb[ 444 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
441 return 0; 445 return 0;
442 } 446 }
443 447
444 static int src_mgr_enb_src(void *blk, unsigned 448 static int src_mgr_enb_src(void *blk, unsigned int idx)
445 { 449 {
446 ((struct src_mgr_ctrl_blk *)blk)->enb[ 450 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
447 ((struct src_mgr_ctrl_blk *)blk)->dirt 451 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
448 return 0; 452 return 0;
449 } 453 }
450 454
451 static int src_mgr_dsb_src(void *blk, unsigned 455 static int src_mgr_dsb_src(void *blk, unsigned int idx)
452 { 456 {
453 ((struct src_mgr_ctrl_blk *)blk)->enb[ 457 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] &= ~(0x1 << (idx%32));
454 ((struct src_mgr_ctrl_blk *)blk)->dirt 458 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
455 return 0; 459 return 0;
456 } 460 }
457 461
458 static int src_mgr_commit_write(struct hw *hw, 462 static int src_mgr_commit_write(struct hw *hw, void *blk)
459 { 463 {
460 struct src_mgr_ctrl_blk *ctl = blk; 464 struct src_mgr_ctrl_blk *ctl = blk;
461 int i; 465 int i;
462 unsigned int ret; 466 unsigned int ret;
463 467
464 if (ctl->dirty.bf.enbsa) { 468 if (ctl->dirty.bf.enbsa) {
465 do { 469 do {
466 ret = hw_read_20kx(hw, 470 ret = hw_read_20kx(hw, SRCENBSTAT);
467 } while (ret & 0x1); 471 } while (ret & 0x1);
468 hw_write_20kx(hw, SRCENBS, ctl 472 hw_write_20kx(hw, SRCENBS, ctl->enbsa);
469 ctl->dirty.bf.enbsa = 0; 473 ctl->dirty.bf.enbsa = 0;
470 } 474 }
471 for (i = 0; i < 8; i++) { 475 for (i = 0; i < 8; i++) {
472 if ((ctl->dirty.data & (0x1 << 476 if ((ctl->dirty.data & (0x1 << i))) {
473 hw_write_20kx(hw, SRCE 477 hw_write_20kx(hw, SRCENB+(i*0x100), ctl->enb[i]);
474 ctl->dirty.data &= ~(0 478 ctl->dirty.data &= ~(0x1 << i);
475 } 479 }
476 } 480 }
477 481
478 return 0; 482 return 0;
479 } 483 }
480 484
481 static int src_mgr_get_ctrl_blk(void **rblk) 485 static int src_mgr_get_ctrl_blk(void **rblk)
482 { 486 {
483 struct src_mgr_ctrl_blk *blk; 487 struct src_mgr_ctrl_blk *blk;
484 488
485 *rblk = NULL; 489 *rblk = NULL;
486 blk = kzalloc(sizeof(*blk), GFP_KERNEL 490 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
487 if (!blk) 491 if (!blk)
488 return -ENOMEM; 492 return -ENOMEM;
489 493
490 *rblk = blk; 494 *rblk = blk;
491 495
492 return 0; 496 return 0;
493 } 497 }
494 498
495 static int src_mgr_put_ctrl_blk(void *blk) 499 static int src_mgr_put_ctrl_blk(void *blk)
496 { 500 {
497 kfree(blk); !! 501 kfree((struct src_mgr_ctrl_blk *)blk);
498 502
499 return 0; 503 return 0;
500 } 504 }
501 505
502 static int srcimp_mgr_get_ctrl_blk(void **rblk 506 static int srcimp_mgr_get_ctrl_blk(void **rblk)
503 { 507 {
504 struct srcimp_mgr_ctrl_blk *blk; 508 struct srcimp_mgr_ctrl_blk *blk;
505 509
506 *rblk = NULL; 510 *rblk = NULL;
507 blk = kzalloc(sizeof(*blk), GFP_KERNEL 511 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
508 if (!blk) 512 if (!blk)
509 return -ENOMEM; 513 return -ENOMEM;
510 514
511 *rblk = blk; 515 *rblk = blk;
512 516
513 return 0; 517 return 0;
514 } 518 }
515 519
516 static int srcimp_mgr_put_ctrl_blk(void *blk) 520 static int srcimp_mgr_put_ctrl_blk(void *blk)
517 { 521 {
518 kfree(blk); !! 522 kfree((struct srcimp_mgr_ctrl_blk *)blk);
519 523
520 return 0; 524 return 0;
521 } 525 }
522 526
523 static int srcimp_mgr_set_imaparc(void *blk, u 527 static int srcimp_mgr_set_imaparc(void *blk, unsigned int slot)
524 { 528 {
525 struct srcimp_mgr_ctrl_blk *ctl = blk; 529 struct srcimp_mgr_ctrl_blk *ctl = blk;
526 530
527 set_field(&ctl->srcimap.srcaim, SRCAIM 531 set_field(&ctl->srcimap.srcaim, SRCAIM_ARC, slot);
528 ctl->dirty.bf.srcimap = 1; 532 ctl->dirty.bf.srcimap = 1;
529 return 0; 533 return 0;
530 } 534 }
531 535
532 static int srcimp_mgr_set_imapuser(void *blk, 536 static int srcimp_mgr_set_imapuser(void *blk, unsigned int user)
533 { 537 {
534 struct srcimp_mgr_ctrl_blk *ctl = blk; 538 struct srcimp_mgr_ctrl_blk *ctl = blk;
535 539
536 set_field(&ctl->srcimap.srcaim, SRCAIM 540 set_field(&ctl->srcimap.srcaim, SRCAIM_SRC, user);
537 ctl->dirty.bf.srcimap = 1; 541 ctl->dirty.bf.srcimap = 1;
538 return 0; 542 return 0;
539 } 543 }
540 544
541 static int srcimp_mgr_set_imapnxt(void *blk, u 545 static int srcimp_mgr_set_imapnxt(void *blk, unsigned int next)
542 { 546 {
543 struct srcimp_mgr_ctrl_blk *ctl = blk; 547 struct srcimp_mgr_ctrl_blk *ctl = blk;
544 548
545 set_field(&ctl->srcimap.srcaim, SRCAIM 549 set_field(&ctl->srcimap.srcaim, SRCAIM_NXT, next);
546 ctl->dirty.bf.srcimap = 1; 550 ctl->dirty.bf.srcimap = 1;
547 return 0; 551 return 0;
548 } 552 }
549 553
550 static int srcimp_mgr_set_imapaddr(void *blk, 554 static int srcimp_mgr_set_imapaddr(void *blk, unsigned int addr)
551 { 555 {
552 struct srcimp_mgr_ctrl_blk *ctl = blk; 556 struct srcimp_mgr_ctrl_blk *ctl = blk;
553 557
554 ctl->srcimap.idx = addr; 558 ctl->srcimap.idx = addr;
555 ctl->dirty.bf.srcimap = 1; 559 ctl->dirty.bf.srcimap = 1;
556 return 0; 560 return 0;
557 } 561 }
558 562
559 static int srcimp_mgr_commit_write(struct hw * 563 static int srcimp_mgr_commit_write(struct hw *hw, void *blk)
560 { 564 {
561 struct srcimp_mgr_ctrl_blk *ctl = blk; 565 struct srcimp_mgr_ctrl_blk *ctl = blk;
562 566
563 if (ctl->dirty.bf.srcimap) { 567 if (ctl->dirty.bf.srcimap) {
564 hw_write_20kx(hw, SRCIMAP+ctl- 568 hw_write_20kx(hw, SRCIMAP+ctl->srcimap.idx*0x100,
565 569 ctl->srcimap.srcaim);
566 ctl->dirty.bf.srcimap = 0; 570 ctl->dirty.bf.srcimap = 0;
567 } 571 }
568 572
569 return 0; 573 return 0;
570 } 574 }
571 575
572 /* 576 /*
573 * AMIXER control block definitions. 577 * AMIXER control block definitions.
574 */ 578 */
575 579
576 #define AMOPLO_M 0x00000003 580 #define AMOPLO_M 0x00000003
577 #define AMOPLO_X 0x0003FFF0 581 #define AMOPLO_X 0x0003FFF0
578 #define AMOPLO_Y 0xFFFC0000 582 #define AMOPLO_Y 0xFFFC0000
579 583
580 #define AMOPHI_SADR 0x000000FF 584 #define AMOPHI_SADR 0x000000FF
581 #define AMOPHI_SE 0x80000000 585 #define AMOPHI_SE 0x80000000
582 586
583 /* AMIXER resource register dirty flags */ 587 /* AMIXER resource register dirty flags */
584 union amixer_dirty { 588 union amixer_dirty {
585 struct { 589 struct {
586 u16 amoplo:1; 590 u16 amoplo:1;
587 u16 amophi:1; 591 u16 amophi:1;
588 u16 rsv:14; 592 u16 rsv:14;
589 } bf; 593 } bf;
590 u16 data; 594 u16 data;
591 }; 595 };
592 596
593 /* AMIXER resource control block */ 597 /* AMIXER resource control block */
594 struct amixer_rsc_ctrl_blk { 598 struct amixer_rsc_ctrl_blk {
595 unsigned int amoplo; 599 unsigned int amoplo;
596 unsigned int amophi; 600 unsigned int amophi;
597 union amixer_dirty dirty; 601 union amixer_dirty dirty;
598 }; 602 };
599 603
600 static int amixer_set_mode(void *blk, unsigned 604 static int amixer_set_mode(void *blk, unsigned int mode)
601 { 605 {
602 struct amixer_rsc_ctrl_blk *ctl = blk; 606 struct amixer_rsc_ctrl_blk *ctl = blk;
603 607
604 set_field(&ctl->amoplo, AMOPLO_M, mode 608 set_field(&ctl->amoplo, AMOPLO_M, mode);
605 ctl->dirty.bf.amoplo = 1; 609 ctl->dirty.bf.amoplo = 1;
606 return 0; 610 return 0;
607 } 611 }
608 612
609 static int amixer_set_iv(void *blk, unsigned i 613 static int amixer_set_iv(void *blk, unsigned int iv)
610 { 614 {
611 /* 20k1 amixer does not have this fiel 615 /* 20k1 amixer does not have this field */
612 return 0; 616 return 0;
613 } 617 }
614 618
615 static int amixer_set_x(void *blk, unsigned in 619 static int amixer_set_x(void *blk, unsigned int x)
616 { 620 {
617 struct amixer_rsc_ctrl_blk *ctl = blk; 621 struct amixer_rsc_ctrl_blk *ctl = blk;
618 622
619 set_field(&ctl->amoplo, AMOPLO_X, x); 623 set_field(&ctl->amoplo, AMOPLO_X, x);
620 ctl->dirty.bf.amoplo = 1; 624 ctl->dirty.bf.amoplo = 1;
621 return 0; 625 return 0;
622 } 626 }
623 627
624 static int amixer_set_y(void *blk, unsigned in 628 static int amixer_set_y(void *blk, unsigned int y)
625 { 629 {
626 struct amixer_rsc_ctrl_blk *ctl = blk; 630 struct amixer_rsc_ctrl_blk *ctl = blk;
627 631
628 set_field(&ctl->amoplo, AMOPLO_Y, y); 632 set_field(&ctl->amoplo, AMOPLO_Y, y);
629 ctl->dirty.bf.amoplo = 1; 633 ctl->dirty.bf.amoplo = 1;
630 return 0; 634 return 0;
631 } 635 }
632 636
633 static int amixer_set_sadr(void *blk, unsigned 637 static int amixer_set_sadr(void *blk, unsigned int sadr)
634 { 638 {
635 struct amixer_rsc_ctrl_blk *ctl = blk; 639 struct amixer_rsc_ctrl_blk *ctl = blk;
636 640
637 set_field(&ctl->amophi, AMOPHI_SADR, s 641 set_field(&ctl->amophi, AMOPHI_SADR, sadr);
638 ctl->dirty.bf.amophi = 1; 642 ctl->dirty.bf.amophi = 1;
639 return 0; 643 return 0;
640 } 644 }
641 645
642 static int amixer_set_se(void *blk, unsigned i 646 static int amixer_set_se(void *blk, unsigned int se)
643 { 647 {
644 struct amixer_rsc_ctrl_blk *ctl = blk; 648 struct amixer_rsc_ctrl_blk *ctl = blk;
645 649
646 set_field(&ctl->amophi, AMOPHI_SE, se) 650 set_field(&ctl->amophi, AMOPHI_SE, se);
647 ctl->dirty.bf.amophi = 1; 651 ctl->dirty.bf.amophi = 1;
648 return 0; 652 return 0;
649 } 653 }
650 654
651 static int amixer_set_dirty(void *blk, unsigne 655 static int amixer_set_dirty(void *blk, unsigned int flags)
652 { 656 {
653 ((struct amixer_rsc_ctrl_blk *)blk)->d 657 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
654 return 0; 658 return 0;
655 } 659 }
656 660
657 static int amixer_set_dirty_all(void *blk) 661 static int amixer_set_dirty_all(void *blk)
658 { 662 {
659 ((struct amixer_rsc_ctrl_blk *)blk)->d 663 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
660 return 0; 664 return 0;
661 } 665 }
662 666
663 static int amixer_commit_write(struct hw *hw, 667 static int amixer_commit_write(struct hw *hw, unsigned int idx, void *blk)
664 { 668 {
665 struct amixer_rsc_ctrl_blk *ctl = blk; 669 struct amixer_rsc_ctrl_blk *ctl = blk;
666 670
667 if (ctl->dirty.bf.amoplo || ctl->dirty 671 if (ctl->dirty.bf.amoplo || ctl->dirty.bf.amophi) {
668 hw_write_20kx(hw, AMOPLO+idx*8 672 hw_write_20kx(hw, AMOPLO+idx*8, ctl->amoplo);
669 ctl->dirty.bf.amoplo = 0; 673 ctl->dirty.bf.amoplo = 0;
670 hw_write_20kx(hw, AMOPHI+idx*8 674 hw_write_20kx(hw, AMOPHI+idx*8, ctl->amophi);
671 ctl->dirty.bf.amophi = 0; 675 ctl->dirty.bf.amophi = 0;
672 } 676 }
673 677
674 return 0; 678 return 0;
675 } 679 }
676 680
677 static int amixer_get_y(void *blk) 681 static int amixer_get_y(void *blk)
678 { 682 {
679 struct amixer_rsc_ctrl_blk *ctl = blk; 683 struct amixer_rsc_ctrl_blk *ctl = blk;
680 684
681 return get_field(ctl->amoplo, AMOPLO_Y 685 return get_field(ctl->amoplo, AMOPLO_Y);
682 } 686 }
683 687
684 static unsigned int amixer_get_dirty(void *blk 688 static unsigned int amixer_get_dirty(void *blk)
685 { 689 {
686 return ((struct amixer_rsc_ctrl_blk *) 690 return ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data;
687 } 691 }
688 692
689 static int amixer_rsc_get_ctrl_blk(void **rblk 693 static int amixer_rsc_get_ctrl_blk(void **rblk)
690 { 694 {
691 struct amixer_rsc_ctrl_blk *blk; 695 struct amixer_rsc_ctrl_blk *blk;
692 696
693 *rblk = NULL; 697 *rblk = NULL;
694 blk = kzalloc(sizeof(*blk), GFP_KERNEL 698 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
695 if (!blk) 699 if (!blk)
696 return -ENOMEM; 700 return -ENOMEM;
697 701
698 *rblk = blk; 702 *rblk = blk;
699 703
700 return 0; 704 return 0;
701 } 705 }
702 706
703 static int amixer_rsc_put_ctrl_blk(void *blk) 707 static int amixer_rsc_put_ctrl_blk(void *blk)
704 { 708 {
705 kfree(blk); !! 709 kfree((struct amixer_rsc_ctrl_blk *)blk);
706 710
707 return 0; 711 return 0;
708 } 712 }
709 713
710 static int amixer_mgr_get_ctrl_blk(void **rblk 714 static int amixer_mgr_get_ctrl_blk(void **rblk)
711 { 715 {
712 /*amixer_mgr_ctrl_blk_t *blk;*/ 716 /*amixer_mgr_ctrl_blk_t *blk;*/
713 717
714 *rblk = NULL; 718 *rblk = NULL;
715 /*blk = kzalloc(sizeof(*blk), GFP_KERN 719 /*blk = kzalloc(sizeof(*blk), GFP_KERNEL);
716 if (!blk) 720 if (!blk)
717 return -ENOMEM; 721 return -ENOMEM;
718 722
719 *rblk = blk;*/ 723 *rblk = blk;*/
720 724
721 return 0; 725 return 0;
722 } 726 }
723 727
724 static int amixer_mgr_put_ctrl_blk(void *blk) 728 static int amixer_mgr_put_ctrl_blk(void *blk)
725 { 729 {
726 /*kfree((amixer_mgr_ctrl_blk_t *)blk); 730 /*kfree((amixer_mgr_ctrl_blk_t *)blk);*/
727 731
728 return 0; 732 return 0;
729 } 733 }
730 734
731 /* 735 /*
732 * DAIO control block definitions. 736 * DAIO control block definitions.
733 */ 737 */
734 738
735 /* Receiver Sample Rate Tracker Control regist 739 /* Receiver Sample Rate Tracker Control register */
736 #define SRTCTL_SRCR 0x000000FF 740 #define SRTCTL_SRCR 0x000000FF
737 #define SRTCTL_SRCL 0x0000FF00 741 #define SRTCTL_SRCL 0x0000FF00
738 #define SRTCTL_RSR 0x00030000 742 #define SRTCTL_RSR 0x00030000
739 #define SRTCTL_DRAT 0x000C0000 743 #define SRTCTL_DRAT 0x000C0000
740 #define SRTCTL_RLE 0x10000000 744 #define SRTCTL_RLE 0x10000000
741 #define SRTCTL_RLP 0x20000000 745 #define SRTCTL_RLP 0x20000000
742 #define SRTCTL_EC 0x40000000 746 #define SRTCTL_EC 0x40000000
743 #define SRTCTL_ET 0x80000000 747 #define SRTCTL_ET 0x80000000
744 748
745 /* DAIO Receiver register dirty flags */ 749 /* DAIO Receiver register dirty flags */
746 union dai_dirty { 750 union dai_dirty {
747 struct { 751 struct {
748 u16 srtctl:1; 752 u16 srtctl:1;
749 u16 rsv:15; 753 u16 rsv:15;
750 } bf; 754 } bf;
751 u16 data; 755 u16 data;
752 }; 756 };
753 757
754 /* DAIO Receiver control block */ 758 /* DAIO Receiver control block */
755 struct dai_ctrl_blk { 759 struct dai_ctrl_blk {
756 unsigned int srtctl; 760 unsigned int srtctl;
757 union dai_dirty dirty; 761 union dai_dirty dirty;
758 }; 762 };
759 763
760 /* S/PDIF Transmitter register dirty flags */ 764 /* S/PDIF Transmitter register dirty flags */
761 union dao_dirty { 765 union dao_dirty {
762 struct { 766 struct {
763 u16 spos:1; 767 u16 spos:1;
764 u16 rsv:15; 768 u16 rsv:15;
765 } bf; 769 } bf;
766 u16 data; 770 u16 data;
767 }; 771 };
768 772
769 /* S/PDIF Transmitter control block */ 773 /* S/PDIF Transmitter control block */
770 struct dao_ctrl_blk { 774 struct dao_ctrl_blk {
771 unsigned int spos; /* S/PDIF Output 775 unsigned int spos; /* S/PDIF Output Channel Status Register */
772 union dao_dirty dirty; 776 union dao_dirty dirty;
773 }; 777 };
774 778
775 /* Audio Input Mapper RAM */ 779 /* Audio Input Mapper RAM */
776 #define AIM_ARC 0x00000FFF 780 #define AIM_ARC 0x00000FFF
777 #define AIM_NXT 0x007F0000 781 #define AIM_NXT 0x007F0000
778 782
779 struct daoimap { 783 struct daoimap {
780 unsigned int aim; 784 unsigned int aim;
781 unsigned int idx; 785 unsigned int idx;
782 }; 786 };
783 787
784 /* I2S Transmitter/Receiver Control register * 788 /* I2S Transmitter/Receiver Control register */
785 #define I2SCTL_EA 0x00000004 789 #define I2SCTL_EA 0x00000004
786 #define I2SCTL_EI 0x00000010 790 #define I2SCTL_EI 0x00000010
787 791
788 /* S/PDIF Transmitter Control register */ 792 /* S/PDIF Transmitter Control register */
789 #define SPOCTL_OE 0x00000001 793 #define SPOCTL_OE 0x00000001
790 #define SPOCTL_OS 0x0000000E 794 #define SPOCTL_OS 0x0000000E
791 #define SPOCTL_RIV 0x00000010 795 #define SPOCTL_RIV 0x00000010
792 #define SPOCTL_LIV 0x00000020 796 #define SPOCTL_LIV 0x00000020
793 #define SPOCTL_SR 0x000000C0 797 #define SPOCTL_SR 0x000000C0
794 798
795 /* S/PDIF Receiver Control register */ 799 /* S/PDIF Receiver Control register */
796 #define SPICTL_EN 0x00000001 800 #define SPICTL_EN 0x00000001
797 #define SPICTL_I24 0x00000002 801 #define SPICTL_I24 0x00000002
798 #define SPICTL_IB 0x00000004 802 #define SPICTL_IB 0x00000004
799 #define SPICTL_SM 0x00000008 803 #define SPICTL_SM 0x00000008
800 #define SPICTL_VM 0x00000010 804 #define SPICTL_VM 0x00000010
801 805
802 /* DAIO manager register dirty flags */ 806 /* DAIO manager register dirty flags */
803 union daio_mgr_dirty { 807 union daio_mgr_dirty {
804 struct { 808 struct {
805 u32 i2soctl:4; 809 u32 i2soctl:4;
806 u32 i2sictl:4; 810 u32 i2sictl:4;
807 u32 spoctl:4; 811 u32 spoctl:4;
808 u32 spictl:4; 812 u32 spictl:4;
809 u32 daoimap:1; 813 u32 daoimap:1;
810 u32 rsv:15; 814 u32 rsv:15;
811 } bf; 815 } bf;
812 u32 data; 816 u32 data;
813 }; 817 };
814 818
815 /* DAIO manager control block */ 819 /* DAIO manager control block */
816 struct daio_mgr_ctrl_blk { 820 struct daio_mgr_ctrl_blk {
817 unsigned int i2sctl; 821 unsigned int i2sctl;
818 unsigned int spoctl; 822 unsigned int spoctl;
819 unsigned int spictl; 823 unsigned int spictl;
820 struct daoimap daoimap; 824 struct daoimap daoimap;
821 union daio_mgr_dirty dirty; 825 union daio_mgr_dirty dirty;
822 }; 826 };
823 827
824 static int dai_srt_set_srcr(void *blk, unsigne 828 static int dai_srt_set_srcr(void *blk, unsigned int src)
825 { 829 {
826 struct dai_ctrl_blk *ctl = blk; 830 struct dai_ctrl_blk *ctl = blk;
827 831
828 set_field(&ctl->srtctl, SRTCTL_SRCR, s 832 set_field(&ctl->srtctl, SRTCTL_SRCR, src);
829 ctl->dirty.bf.srtctl = 1; 833 ctl->dirty.bf.srtctl = 1;
830 return 0; 834 return 0;
831 } 835 }
832 836
833 static int dai_srt_set_srcl(void *blk, unsigne 837 static int dai_srt_set_srcl(void *blk, unsigned int src)
834 { 838 {
835 struct dai_ctrl_blk *ctl = blk; 839 struct dai_ctrl_blk *ctl = blk;
836 840
837 set_field(&ctl->srtctl, SRTCTL_SRCL, s 841 set_field(&ctl->srtctl, SRTCTL_SRCL, src);
838 ctl->dirty.bf.srtctl = 1; 842 ctl->dirty.bf.srtctl = 1;
839 return 0; 843 return 0;
840 } 844 }
841 845
842 static int dai_srt_set_rsr(void *blk, unsigned 846 static int dai_srt_set_rsr(void *blk, unsigned int rsr)
843 { 847 {
844 struct dai_ctrl_blk *ctl = blk; 848 struct dai_ctrl_blk *ctl = blk;
845 849
846 set_field(&ctl->srtctl, SRTCTL_RSR, rs 850 set_field(&ctl->srtctl, SRTCTL_RSR, rsr);
847 ctl->dirty.bf.srtctl = 1; 851 ctl->dirty.bf.srtctl = 1;
848 return 0; 852 return 0;
849 } 853 }
850 854
851 static int dai_srt_set_drat(void *blk, unsigne 855 static int dai_srt_set_drat(void *blk, unsigned int drat)
852 { 856 {
853 struct dai_ctrl_blk *ctl = blk; 857 struct dai_ctrl_blk *ctl = blk;
854 858
855 set_field(&ctl->srtctl, SRTCTL_DRAT, d 859 set_field(&ctl->srtctl, SRTCTL_DRAT, drat);
856 ctl->dirty.bf.srtctl = 1; 860 ctl->dirty.bf.srtctl = 1;
857 return 0; 861 return 0;
858 } 862 }
859 863
860 static int dai_srt_set_ec(void *blk, unsigned 864 static int dai_srt_set_ec(void *blk, unsigned int ec)
861 { 865 {
862 struct dai_ctrl_blk *ctl = blk; 866 struct dai_ctrl_blk *ctl = blk;
863 867
864 set_field(&ctl->srtctl, SRTCTL_EC, ec 868 set_field(&ctl->srtctl, SRTCTL_EC, ec ? 1 : 0);
865 ctl->dirty.bf.srtctl = 1; 869 ctl->dirty.bf.srtctl = 1;
866 return 0; 870 return 0;
867 } 871 }
868 872
869 static int dai_srt_set_et(void *blk, unsigned 873 static int dai_srt_set_et(void *blk, unsigned int et)
870 { 874 {
871 struct dai_ctrl_blk *ctl = blk; 875 struct dai_ctrl_blk *ctl = blk;
872 876
873 set_field(&ctl->srtctl, SRTCTL_ET, et 877 set_field(&ctl->srtctl, SRTCTL_ET, et ? 1 : 0);
874 ctl->dirty.bf.srtctl = 1; 878 ctl->dirty.bf.srtctl = 1;
875 return 0; 879 return 0;
876 } 880 }
877 881
878 static int dai_commit_write(struct hw *hw, uns 882 static int dai_commit_write(struct hw *hw, unsigned int idx, void *blk)
879 { 883 {
880 struct dai_ctrl_blk *ctl = blk; 884 struct dai_ctrl_blk *ctl = blk;
881 885
882 if (ctl->dirty.bf.srtctl) { 886 if (ctl->dirty.bf.srtctl) {
883 if (idx < 4) { 887 if (idx < 4) {
884 /* S/PDIF SRTs */ 888 /* S/PDIF SRTs */
885 hw_write_20kx(hw, SRTS 889 hw_write_20kx(hw, SRTSCTL+0x4*idx, ctl->srtctl);
886 } else { 890 } else {
887 /* I2S SRT */ 891 /* I2S SRT */
888 hw_write_20kx(hw, SRTI 892 hw_write_20kx(hw, SRTICTL, ctl->srtctl);
889 } 893 }
890 ctl->dirty.bf.srtctl = 0; 894 ctl->dirty.bf.srtctl = 0;
891 } 895 }
892 896
893 return 0; 897 return 0;
894 } 898 }
895 899
896 static int dai_get_ctrl_blk(void **rblk) 900 static int dai_get_ctrl_blk(void **rblk)
897 { 901 {
898 struct dai_ctrl_blk *blk; 902 struct dai_ctrl_blk *blk;
899 903
900 *rblk = NULL; 904 *rblk = NULL;
901 blk = kzalloc(sizeof(*blk), GFP_KERNEL 905 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
902 if (!blk) 906 if (!blk)
903 return -ENOMEM; 907 return -ENOMEM;
904 908
905 *rblk = blk; 909 *rblk = blk;
906 910
907 return 0; 911 return 0;
908 } 912 }
909 913
910 static int dai_put_ctrl_blk(void *blk) 914 static int dai_put_ctrl_blk(void *blk)
911 { 915 {
912 kfree(blk); !! 916 kfree((struct dai_ctrl_blk *)blk);
913 917
914 return 0; 918 return 0;
915 } 919 }
916 920
917 static int dao_set_spos(void *blk, unsigned in 921 static int dao_set_spos(void *blk, unsigned int spos)
918 { 922 {
919 ((struct dao_ctrl_blk *)blk)->spos = s 923 ((struct dao_ctrl_blk *)blk)->spos = spos;
920 ((struct dao_ctrl_blk *)blk)->dirty.bf 924 ((struct dao_ctrl_blk *)blk)->dirty.bf.spos = 1;
921 return 0; 925 return 0;
922 } 926 }
923 927
924 static int dao_commit_write(struct hw *hw, uns 928 static int dao_commit_write(struct hw *hw, unsigned int idx, void *blk)
925 { 929 {
926 struct dao_ctrl_blk *ctl = blk; 930 struct dao_ctrl_blk *ctl = blk;
927 931
928 if (ctl->dirty.bf.spos) { 932 if (ctl->dirty.bf.spos) {
929 if (idx < 4) { 933 if (idx < 4) {
930 /* S/PDIF SPOSx */ 934 /* S/PDIF SPOSx */
931 hw_write_20kx(hw, SPOS 935 hw_write_20kx(hw, SPOS+0x4*idx, ctl->spos);
932 } 936 }
933 ctl->dirty.bf.spos = 0; 937 ctl->dirty.bf.spos = 0;
934 } 938 }
935 939
936 return 0; 940 return 0;
937 } 941 }
938 942
939 static int dao_get_spos(void *blk, unsigned in 943 static int dao_get_spos(void *blk, unsigned int *spos)
940 { 944 {
941 *spos = ((struct dao_ctrl_blk *)blk)-> 945 *spos = ((struct dao_ctrl_blk *)blk)->spos;
942 return 0; 946 return 0;
943 } 947 }
944 948
945 static int dao_get_ctrl_blk(void **rblk) 949 static int dao_get_ctrl_blk(void **rblk)
946 { 950 {
947 struct dao_ctrl_blk *blk; 951 struct dao_ctrl_blk *blk;
948 952
949 *rblk = NULL; 953 *rblk = NULL;
950 blk = kzalloc(sizeof(*blk), GFP_KERNEL 954 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
951 if (!blk) 955 if (!blk)
952 return -ENOMEM; 956 return -ENOMEM;
953 957
954 *rblk = blk; 958 *rblk = blk;
955 959
956 return 0; 960 return 0;
957 } 961 }
958 962
959 static int dao_put_ctrl_blk(void *blk) 963 static int dao_put_ctrl_blk(void *blk)
960 { 964 {
961 kfree(blk); !! 965 kfree((struct dao_ctrl_blk *)blk);
962 966
963 return 0; 967 return 0;
964 } 968 }
965 969
966 static int daio_mgr_enb_dai(void *blk, unsigne 970 static int daio_mgr_enb_dai(void *blk, unsigned int idx)
967 { 971 {
968 struct daio_mgr_ctrl_blk *ctl = blk; 972 struct daio_mgr_ctrl_blk *ctl = blk;
969 973
970 if (idx < 4) { 974 if (idx < 4) {
971 /* S/PDIF input */ 975 /* S/PDIF input */
972 set_field(&ctl->spictl, SPICTL 976 set_field(&ctl->spictl, SPICTL_EN << (idx*8), 1);
973 ctl->dirty.bf.spictl |= (0x1 < 977 ctl->dirty.bf.spictl |= (0x1 << idx);
974 } else { 978 } else {
975 /* I2S input */ 979 /* I2S input */
976 idx %= 4; 980 idx %= 4;
977 set_field(&ctl->i2sctl, I2SCTL 981 set_field(&ctl->i2sctl, I2SCTL_EI << (idx*8), 1);
978 ctl->dirty.bf.i2sictl |= (0x1 982 ctl->dirty.bf.i2sictl |= (0x1 << idx);
979 } 983 }
980 return 0; 984 return 0;
981 } 985 }
982 986
983 static int daio_mgr_dsb_dai(void *blk, unsigne 987 static int daio_mgr_dsb_dai(void *blk, unsigned int idx)
984 { 988 {
985 struct daio_mgr_ctrl_blk *ctl = blk; 989 struct daio_mgr_ctrl_blk *ctl = blk;
986 990
987 if (idx < 4) { 991 if (idx < 4) {
988 /* S/PDIF input */ 992 /* S/PDIF input */
989 set_field(&ctl->spictl, SPICTL 993 set_field(&ctl->spictl, SPICTL_EN << (idx*8), 0);
990 ctl->dirty.bf.spictl |= (0x1 < 994 ctl->dirty.bf.spictl |= (0x1 << idx);
991 } else { 995 } else {
992 /* I2S input */ 996 /* I2S input */
993 idx %= 4; 997 idx %= 4;
994 set_field(&ctl->i2sctl, I2SCTL 998 set_field(&ctl->i2sctl, I2SCTL_EI << (idx*8), 0);
995 ctl->dirty.bf.i2sictl |= (0x1 999 ctl->dirty.bf.i2sictl |= (0x1 << idx);
996 } 1000 }
997 return 0; 1001 return 0;
998 } 1002 }
999 1003
1000 static int daio_mgr_enb_dao(void *blk, unsign 1004 static int daio_mgr_enb_dao(void *blk, unsigned int idx)
1001 { 1005 {
1002 struct daio_mgr_ctrl_blk *ctl = blk; 1006 struct daio_mgr_ctrl_blk *ctl = blk;
1003 1007
1004 if (idx < 4) { 1008 if (idx < 4) {
1005 /* S/PDIF output */ 1009 /* S/PDIF output */
1006 set_field(&ctl->spoctl, SPOCT 1010 set_field(&ctl->spoctl, SPOCTL_OE << (idx*8), 1);
1007 ctl->dirty.bf.spoctl |= (0x1 1011 ctl->dirty.bf.spoctl |= (0x1 << idx);
1008 } else { 1012 } else {
1009 /* I2S output */ 1013 /* I2S output */
1010 idx %= 4; 1014 idx %= 4;
1011 set_field(&ctl->i2sctl, I2SCT 1015 set_field(&ctl->i2sctl, I2SCTL_EA << (idx*8), 1);
1012 ctl->dirty.bf.i2soctl |= (0x1 1016 ctl->dirty.bf.i2soctl |= (0x1 << idx);
1013 } 1017 }
1014 return 0; 1018 return 0;
1015 } 1019 }
1016 1020
1017 static int daio_mgr_dsb_dao(void *blk, unsign 1021 static int daio_mgr_dsb_dao(void *blk, unsigned int idx)
1018 { 1022 {
1019 struct daio_mgr_ctrl_blk *ctl = blk; 1023 struct daio_mgr_ctrl_blk *ctl = blk;
1020 1024
1021 if (idx < 4) { 1025 if (idx < 4) {
1022 /* S/PDIF output */ 1026 /* S/PDIF output */
1023 set_field(&ctl->spoctl, SPOCT 1027 set_field(&ctl->spoctl, SPOCTL_OE << (idx*8), 0);
1024 ctl->dirty.bf.spoctl |= (0x1 1028 ctl->dirty.bf.spoctl |= (0x1 << idx);
1025 } else { 1029 } else {
1026 /* I2S output */ 1030 /* I2S output */
1027 idx %= 4; 1031 idx %= 4;
1028 set_field(&ctl->i2sctl, I2SCT 1032 set_field(&ctl->i2sctl, I2SCTL_EA << (idx*8), 0);
1029 ctl->dirty.bf.i2soctl |= (0x1 1033 ctl->dirty.bf.i2soctl |= (0x1 << idx);
1030 } 1034 }
1031 return 0; 1035 return 0;
1032 } 1036 }
1033 1037
1034 static int daio_mgr_dao_init(void *blk, unsig 1038 static int daio_mgr_dao_init(void *blk, unsigned int idx, unsigned int conf)
1035 { 1039 {
1036 struct daio_mgr_ctrl_blk *ctl = blk; 1040 struct daio_mgr_ctrl_blk *ctl = blk;
1037 1041
1038 if (idx < 4) { 1042 if (idx < 4) {
1039 /* S/PDIF output */ 1043 /* S/PDIF output */
1040 switch ((conf & 0x7)) { 1044 switch ((conf & 0x7)) {
1041 case 0: 1045 case 0:
1042 set_field(&ctl->spoct 1046 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 3);
1043 break; /* CDIF */ 1047 break; /* CDIF */
1044 case 1: 1048 case 1:
1045 set_field(&ctl->spoct 1049 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 0);
1046 break; 1050 break;
1047 case 2: 1051 case 2:
1048 set_field(&ctl->spoct 1052 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 1);
1049 break; 1053 break;
1050 case 4: 1054 case 4:
1051 set_field(&ctl->spoct 1055 set_field(&ctl->spoctl, SPOCTL_SR << (idx*8), 2);
1052 break; 1056 break;
1053 default: 1057 default:
1054 break; 1058 break;
1055 } 1059 }
1056 set_field(&ctl->spoctl, SPOCT 1060 set_field(&ctl->spoctl, SPOCTL_LIV << (idx*8),
1057 (conf >> 4) & 0x1); 1061 (conf >> 4) & 0x1); /* Non-audio */
1058 set_field(&ctl->spoctl, SPOCT 1062 set_field(&ctl->spoctl, SPOCTL_RIV << (idx*8),
1059 (conf >> 4) & 0x1); 1063 (conf >> 4) & 0x1); /* Non-audio */
1060 set_field(&ctl->spoctl, SPOCT 1064 set_field(&ctl->spoctl, SPOCTL_OS << (idx*8),
1061 ((conf >> 3) & 0x1) 1065 ((conf >> 3) & 0x1) ? 2 : 2); /* Raw */
1062 1066
1063 ctl->dirty.bf.spoctl |= (0x1 1067 ctl->dirty.bf.spoctl |= (0x1 << idx);
1064 } else { 1068 } else {
1065 /* I2S output */ 1069 /* I2S output */
1066 /*idx %= 4; */ 1070 /*idx %= 4; */
1067 } 1071 }
1068 return 0; 1072 return 0;
1069 } 1073 }
1070 1074
1071 static int daio_mgr_set_imaparc(void *blk, un 1075 static int daio_mgr_set_imaparc(void *blk, unsigned int slot)
1072 { 1076 {
1073 struct daio_mgr_ctrl_blk *ctl = blk; 1077 struct daio_mgr_ctrl_blk *ctl = blk;
1074 1078
1075 set_field(&ctl->daoimap.aim, AIM_ARC, 1079 set_field(&ctl->daoimap.aim, AIM_ARC, slot);
1076 ctl->dirty.bf.daoimap = 1; 1080 ctl->dirty.bf.daoimap = 1;
1077 return 0; 1081 return 0;
1078 } 1082 }
1079 1083
1080 static int daio_mgr_set_imapnxt(void *blk, un 1084 static int daio_mgr_set_imapnxt(void *blk, unsigned int next)
1081 { 1085 {
1082 struct daio_mgr_ctrl_blk *ctl = blk; 1086 struct daio_mgr_ctrl_blk *ctl = blk;
1083 1087
1084 set_field(&ctl->daoimap.aim, AIM_NXT, 1088 set_field(&ctl->daoimap.aim, AIM_NXT, next);
1085 ctl->dirty.bf.daoimap = 1; 1089 ctl->dirty.bf.daoimap = 1;
1086 return 0; 1090 return 0;
1087 } 1091 }
1088 1092
1089 static int daio_mgr_set_imapaddr(void *blk, u 1093 static int daio_mgr_set_imapaddr(void *blk, unsigned int addr)
1090 { 1094 {
1091 struct daio_mgr_ctrl_blk *ctl = blk; 1095 struct daio_mgr_ctrl_blk *ctl = blk;
1092 1096
1093 ctl->daoimap.idx = addr; 1097 ctl->daoimap.idx = addr;
1094 ctl->dirty.bf.daoimap = 1; 1098 ctl->dirty.bf.daoimap = 1;
1095 return 0; 1099 return 0;
1096 } 1100 }
1097 1101
1098 static int daio_mgr_commit_write(struct hw *h 1102 static int daio_mgr_commit_write(struct hw *hw, void *blk)
1099 { 1103 {
1100 struct daio_mgr_ctrl_blk *ctl = blk; 1104 struct daio_mgr_ctrl_blk *ctl = blk;
1101 int i; 1105 int i;
1102 1106
1103 if (ctl->dirty.bf.i2sictl || ctl->dir 1107 if (ctl->dirty.bf.i2sictl || ctl->dirty.bf.i2soctl) {
1104 for (i = 0; i < 4; i++) { 1108 for (i = 0; i < 4; i++) {
1105 if ((ctl->dirty.bf.i2 1109 if ((ctl->dirty.bf.i2sictl & (0x1 << i)))
1106 ctl->dirty.bf 1110 ctl->dirty.bf.i2sictl &= ~(0x1 << i);
1107 1111
1108 if ((ctl->dirty.bf.i2 1112 if ((ctl->dirty.bf.i2soctl & (0x1 << i)))
1109 ctl->dirty.bf 1113 ctl->dirty.bf.i2soctl &= ~(0x1 << i);
1110 } 1114 }
1111 hw_write_20kx(hw, I2SCTL, ctl 1115 hw_write_20kx(hw, I2SCTL, ctl->i2sctl);
1112 mdelay(1); 1116 mdelay(1);
1113 } 1117 }
1114 if (ctl->dirty.bf.spoctl) { 1118 if (ctl->dirty.bf.spoctl) {
1115 for (i = 0; i < 4; i++) { 1119 for (i = 0; i < 4; i++) {
1116 if ((ctl->dirty.bf.sp 1120 if ((ctl->dirty.bf.spoctl & (0x1 << i)))
1117 ctl->dirty.bf 1121 ctl->dirty.bf.spoctl &= ~(0x1 << i);
1118 } 1122 }
1119 hw_write_20kx(hw, SPOCTL, ctl 1123 hw_write_20kx(hw, SPOCTL, ctl->spoctl);
1120 mdelay(1); 1124 mdelay(1);
1121 } 1125 }
1122 if (ctl->dirty.bf.spictl) { 1126 if (ctl->dirty.bf.spictl) {
1123 for (i = 0; i < 4; i++) { 1127 for (i = 0; i < 4; i++) {
1124 if ((ctl->dirty.bf.sp 1128 if ((ctl->dirty.bf.spictl & (0x1 << i)))
1125 ctl->dirty.bf 1129 ctl->dirty.bf.spictl &= ~(0x1 << i);
1126 } 1130 }
1127 hw_write_20kx(hw, SPICTL, ctl 1131 hw_write_20kx(hw, SPICTL, ctl->spictl);
1128 mdelay(1); 1132 mdelay(1);
1129 } 1133 }
1130 if (ctl->dirty.bf.daoimap) { 1134 if (ctl->dirty.bf.daoimap) {
1131 hw_write_20kx(hw, DAOIMAP+ctl 1135 hw_write_20kx(hw, DAOIMAP+ctl->daoimap.idx*4,
1132 ctl-> 1136 ctl->daoimap.aim);
1133 ctl->dirty.bf.daoimap = 0; 1137 ctl->dirty.bf.daoimap = 0;
1134 } 1138 }
1135 1139
1136 return 0; 1140 return 0;
1137 } 1141 }
1138 1142
1139 static int daio_mgr_get_ctrl_blk(struct hw *h 1143 static int daio_mgr_get_ctrl_blk(struct hw *hw, void **rblk)
1140 { 1144 {
1141 struct daio_mgr_ctrl_blk *blk; 1145 struct daio_mgr_ctrl_blk *blk;
1142 1146
1143 *rblk = NULL; 1147 *rblk = NULL;
1144 blk = kzalloc(sizeof(*blk), GFP_KERNE 1148 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
1145 if (!blk) 1149 if (!blk)
1146 return -ENOMEM; 1150 return -ENOMEM;
1147 1151
1148 blk->i2sctl = hw_read_20kx(hw, I2SCTL 1152 blk->i2sctl = hw_read_20kx(hw, I2SCTL);
1149 blk->spoctl = hw_read_20kx(hw, SPOCTL 1153 blk->spoctl = hw_read_20kx(hw, SPOCTL);
1150 blk->spictl = hw_read_20kx(hw, SPICTL 1154 blk->spictl = hw_read_20kx(hw, SPICTL);
1151 1155
1152 *rblk = blk; 1156 *rblk = blk;
1153 1157
1154 return 0; 1158 return 0;
1155 } 1159 }
1156 1160
1157 static int daio_mgr_put_ctrl_blk(void *blk) 1161 static int daio_mgr_put_ctrl_blk(void *blk)
1158 { 1162 {
1159 kfree(blk); !! 1163 kfree((struct daio_mgr_ctrl_blk *)blk);
1160 1164
1161 return 0; 1165 return 0;
1162 } 1166 }
1163 1167
1164 /* Timer interrupt */ 1168 /* Timer interrupt */
1165 static int set_timer_irq(struct hw *hw, int e 1169 static int set_timer_irq(struct hw *hw, int enable)
1166 { 1170 {
1167 hw_write_20kx(hw, GIE, enable ? IT_IN 1171 hw_write_20kx(hw, GIE, enable ? IT_INT : 0);
1168 return 0; 1172 return 0;
1169 } 1173 }
1170 1174
1171 static int set_timer_tick(struct hw *hw, unsi 1175 static int set_timer_tick(struct hw *hw, unsigned int ticks)
1172 { 1176 {
1173 if (ticks) 1177 if (ticks)
1174 ticks |= TIMR_IE | TIMR_IP; 1178 ticks |= TIMR_IE | TIMR_IP;
1175 hw_write_20kx(hw, TIMR, ticks); 1179 hw_write_20kx(hw, TIMR, ticks);
1176 return 0; 1180 return 0;
1177 } 1181 }
1178 1182
1179 static unsigned int get_wc(struct hw *hw) 1183 static unsigned int get_wc(struct hw *hw)
1180 { 1184 {
1181 return hw_read_20kx(hw, WC); 1185 return hw_read_20kx(hw, WC);
1182 } 1186 }
1183 1187
1184 /* Card hardware initialization block */ 1188 /* Card hardware initialization block */
1185 struct dac_conf { 1189 struct dac_conf {
1186 unsigned int msr; /* master sample ra 1190 unsigned int msr; /* master sample rate in rsrs */
1187 }; 1191 };
1188 1192
1189 struct adc_conf { 1193 struct adc_conf {
1190 unsigned int msr; /* master sam 1194 unsigned int msr; /* master sample rate in rsrs */
1191 unsigned char input; /* the input 1195 unsigned char input; /* the input source of ADC */
1192 unsigned char mic20db; /* boost mic 1196 unsigned char mic20db; /* boost mic by 20db if input is microphone */
1193 }; 1197 };
1194 1198
1195 struct daio_conf { 1199 struct daio_conf {
1196 unsigned int msr; /* master sample ra 1200 unsigned int msr; /* master sample rate in rsrs */
1197 }; 1201 };
1198 1202
1199 struct trn_conf { 1203 struct trn_conf {
1200 unsigned long vm_pgt_phys; 1204 unsigned long vm_pgt_phys;
1201 }; 1205 };
1202 1206
1203 static int hw_daio_init(struct hw *hw, const 1207 static int hw_daio_init(struct hw *hw, const struct daio_conf *info)
1204 { 1208 {
1205 u32 i2sorg; 1209 u32 i2sorg;
1206 u32 spdorg; 1210 u32 spdorg;
1207 1211
1208 /* Read I2S CTL. Keep original value 1212 /* Read I2S CTL. Keep original value. */
1209 /*i2sorg = hw_read_20kx(hw, I2SCTL);* 1213 /*i2sorg = hw_read_20kx(hw, I2SCTL);*/
1210 i2sorg = 0x94040404; /* enable all au 1214 i2sorg = 0x94040404; /* enable all audio out and I2S-D input */
1211 /* Program I2S with proper master sam 1215 /* Program I2S with proper master sample rate and enable
1212 * the correct I2S channel. */ 1216 * the correct I2S channel. */
1213 i2sorg &= 0xfffffffc; 1217 i2sorg &= 0xfffffffc;
1214 1218
1215 /* Enable S/PDIF-out-A in fixed 24-bi 1219 /* Enable S/PDIF-out-A in fixed 24-bit data
1216 * format and default to 48kHz. */ 1220 * format and default to 48kHz. */
1217 /* Disable all before doing any chang 1221 /* Disable all before doing any changes. */
1218 hw_write_20kx(hw, SPOCTL, 0x0); 1222 hw_write_20kx(hw, SPOCTL, 0x0);
1219 spdorg = 0x05; 1223 spdorg = 0x05;
1220 1224
1221 switch (info->msr) { 1225 switch (info->msr) {
1222 case 1: 1226 case 1:
1223 i2sorg |= 1; 1227 i2sorg |= 1;
1224 spdorg |= (0x0 << 6); 1228 spdorg |= (0x0 << 6);
1225 break; 1229 break;
1226 case 2: 1230 case 2:
1227 i2sorg |= 2; 1231 i2sorg |= 2;
1228 spdorg |= (0x1 << 6); 1232 spdorg |= (0x1 << 6);
1229 break; 1233 break;
1230 case 4: 1234 case 4:
1231 i2sorg |= 3; 1235 i2sorg |= 3;
1232 spdorg |= (0x2 << 6); 1236 spdorg |= (0x2 << 6);
1233 break; 1237 break;
1234 default: 1238 default:
1235 i2sorg |= 1; 1239 i2sorg |= 1;
1236 break; 1240 break;
1237 } 1241 }
1238 1242
1239 hw_write_20kx(hw, I2SCTL, i2sorg); 1243 hw_write_20kx(hw, I2SCTL, i2sorg);
1240 hw_write_20kx(hw, SPOCTL, spdorg); 1244 hw_write_20kx(hw, SPOCTL, spdorg);
1241 1245
1242 /* Enable S/PDIF-in-A in fixed 24-bit 1246 /* Enable S/PDIF-in-A in fixed 24-bit data format. */
1243 /* Disable all before doing any chang 1247 /* Disable all before doing any changes. */
1244 hw_write_20kx(hw, SPICTL, 0x0); 1248 hw_write_20kx(hw, SPICTL, 0x0);
1245 mdelay(1); 1249 mdelay(1);
1246 spdorg = 0x0a0a0a0a; 1250 spdorg = 0x0a0a0a0a;
1247 hw_write_20kx(hw, SPICTL, spdorg); 1251 hw_write_20kx(hw, SPICTL, spdorg);
1248 mdelay(1); 1252 mdelay(1);
1249 1253
1250 return 0; 1254 return 0;
1251 } 1255 }
1252 1256
1253 /* TRANSPORT operations */ 1257 /* TRANSPORT operations */
1254 static int hw_trn_init(struct hw *hw, const s 1258 static int hw_trn_init(struct hw *hw, const struct trn_conf *info)
1255 { 1259 {
1256 u32 trnctl; 1260 u32 trnctl;
1257 u32 ptp_phys_low, ptp_phys_high; 1261 u32 ptp_phys_low, ptp_phys_high;
1258 1262
1259 /* Set up device page table */ 1263 /* Set up device page table */
1260 if ((~0UL) == info->vm_pgt_phys) { 1264 if ((~0UL) == info->vm_pgt_phys) {
1261 dev_err(hw->card->dev, 1265 dev_err(hw->card->dev,
1262 "Wrong device page ta 1266 "Wrong device page table page address!\n");
1263 return -1; 1267 return -1;
1264 } 1268 }
1265 1269
1266 trnctl = 0x13; /* 32-bit, 4k-size pa 1270 trnctl = 0x13; /* 32-bit, 4k-size page */
1267 ptp_phys_low = (u32)info->vm_pgt_phys 1271 ptp_phys_low = (u32)info->vm_pgt_phys;
1268 ptp_phys_high = upper_32_bits(info->v 1272 ptp_phys_high = upper_32_bits(info->vm_pgt_phys);
1269 if (sizeof(void *) == 8) /* 64bit add 1273 if (sizeof(void *) == 8) /* 64bit address */
1270 trnctl |= (1 << 2); 1274 trnctl |= (1 << 2);
1271 #if 0 /* Only 4k h/w pages for simplicitiy */ 1275 #if 0 /* Only 4k h/w pages for simplicitiy */
1272 #if PAGE_SIZE == 8192 1276 #if PAGE_SIZE == 8192
1273 trnctl |= (1<<5); 1277 trnctl |= (1<<5);
1274 #endif 1278 #endif
1275 #endif 1279 #endif
1276 hw_write_20kx(hw, PTPALX, ptp_phys_lo 1280 hw_write_20kx(hw, PTPALX, ptp_phys_low);
1277 hw_write_20kx(hw, PTPAHX, ptp_phys_hi 1281 hw_write_20kx(hw, PTPAHX, ptp_phys_high);
1278 hw_write_20kx(hw, TRNCTL, trnctl); 1282 hw_write_20kx(hw, TRNCTL, trnctl);
1279 hw_write_20kx(hw, TRNIS, 0x200c01); / 1283 hw_write_20kx(hw, TRNIS, 0x200c01); /* really needed? */
1280 1284
1281 return 0; 1285 return 0;
1282 } 1286 }
1283 1287
1284 /* Card initialization */ 1288 /* Card initialization */
1285 #define GCTL_EAC 0x00000001 1289 #define GCTL_EAC 0x00000001
1286 #define GCTL_EAI 0x00000002 1290 #define GCTL_EAI 0x00000002
1287 #define GCTL_BEP 0x00000004 1291 #define GCTL_BEP 0x00000004
1288 #define GCTL_BES 0x00000008 1292 #define GCTL_BES 0x00000008
1289 #define GCTL_DSP 0x00000010 1293 #define GCTL_DSP 0x00000010
1290 #define GCTL_DBP 0x00000020 1294 #define GCTL_DBP 0x00000020
1291 #define GCTL_ABP 0x00000040 1295 #define GCTL_ABP 0x00000040
1292 #define GCTL_TBP 0x00000080 1296 #define GCTL_TBP 0x00000080
1293 #define GCTL_SBP 0x00000100 1297 #define GCTL_SBP 0x00000100
1294 #define GCTL_FBP 0x00000200 1298 #define GCTL_FBP 0x00000200
1295 #define GCTL_XA 0x00000400 1299 #define GCTL_XA 0x00000400
1296 #define GCTL_ET 0x00000800 1300 #define GCTL_ET 0x00000800
1297 #define GCTL_PR 0x00001000 1301 #define GCTL_PR 0x00001000
1298 #define GCTL_MRL 0x00002000 1302 #define GCTL_MRL 0x00002000
1299 #define GCTL_SDE 0x00004000 1303 #define GCTL_SDE 0x00004000
1300 #define GCTL_SDI 0x00008000 1304 #define GCTL_SDI 0x00008000
1301 #define GCTL_SM 0x00010000 1305 #define GCTL_SM 0x00010000
1302 #define GCTL_SR 0x00020000 1306 #define GCTL_SR 0x00020000
1303 #define GCTL_SD 0x00040000 1307 #define GCTL_SD 0x00040000
1304 #define GCTL_SE 0x00080000 1308 #define GCTL_SE 0x00080000
1305 #define GCTL_AID 0x00100000 1309 #define GCTL_AID 0x00100000
1306 1310
1307 static int hw_pll_init(struct hw *hw, unsigne 1311 static int hw_pll_init(struct hw *hw, unsigned int rsr)
1308 { 1312 {
1309 unsigned int pllctl; 1313 unsigned int pllctl;
1310 int i; 1314 int i;
1311 1315
1312 pllctl = (48000 == rsr) ? 0x1480a001 1316 pllctl = (48000 == rsr) ? 0x1480a001 : 0x1480a731;
1313 for (i = 0; i < 3; i++) { 1317 for (i = 0; i < 3; i++) {
1314 if (hw_read_20kx(hw, PLLCTL) 1318 if (hw_read_20kx(hw, PLLCTL) == pllctl)
1315 break; 1319 break;
1316 1320
1317 hw_write_20kx(hw, PLLCTL, pll 1321 hw_write_20kx(hw, PLLCTL, pllctl);
1318 msleep(40); 1322 msleep(40);
1319 } 1323 }
1320 if (i >= 3) { 1324 if (i >= 3) {
1321 dev_alert(hw->card->dev, "PLL 1325 dev_alert(hw->card->dev, "PLL initialization failed!!!\n");
1322 return -EBUSY; 1326 return -EBUSY;
1323 } 1327 }
1324 1328
1325 return 0; 1329 return 0;
1326 } 1330 }
1327 1331
1328 static int hw_auto_init(struct hw *hw) 1332 static int hw_auto_init(struct hw *hw)
1329 { 1333 {
1330 unsigned int gctl; 1334 unsigned int gctl;
1331 int i; 1335 int i;
1332 1336
1333 gctl = hw_read_20kx(hw, GCTL); 1337 gctl = hw_read_20kx(hw, GCTL);
1334 set_field(&gctl, GCTL_EAI, 0); 1338 set_field(&gctl, GCTL_EAI, 0);
1335 hw_write_20kx(hw, GCTL, gctl); 1339 hw_write_20kx(hw, GCTL, gctl);
1336 set_field(&gctl, GCTL_EAI, 1); 1340 set_field(&gctl, GCTL_EAI, 1);
1337 hw_write_20kx(hw, GCTL, gctl); 1341 hw_write_20kx(hw, GCTL, gctl);
1338 mdelay(10); 1342 mdelay(10);
1339 for (i = 0; i < 400000; i++) { 1343 for (i = 0; i < 400000; i++) {
1340 gctl = hw_read_20kx(hw, GCTL) 1344 gctl = hw_read_20kx(hw, GCTL);
1341 if (get_field(gctl, GCTL_AID) 1345 if (get_field(gctl, GCTL_AID))
1342 break; 1346 break;
1343 } 1347 }
1344 if (!get_field(gctl, GCTL_AID)) { 1348 if (!get_field(gctl, GCTL_AID)) {
1345 dev_alert(hw->card->dev, "Car 1349 dev_alert(hw->card->dev, "Card Auto-init failed!!!\n");
1346 return -EBUSY; 1350 return -EBUSY;
1347 } 1351 }
1348 1352
1349 return 0; 1353 return 0;
1350 } 1354 }
1351 1355
1352 static int i2c_unlock(struct hw *hw) 1356 static int i2c_unlock(struct hw *hw)
1353 { 1357 {
1354 if ((hw_read_pci(hw, 0xcc) & 0xff) == 1358 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
1355 return 0; 1359 return 0;
1356 1360
1357 hw_write_pci(hw, 0xcc, 0x8c); 1361 hw_write_pci(hw, 0xcc, 0x8c);
1358 hw_write_pci(hw, 0xcc, 0x0e); 1362 hw_write_pci(hw, 0xcc, 0x0e);
1359 if ((hw_read_pci(hw, 0xcc) & 0xff) == 1363 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
1360 return 0; 1364 return 0;
1361 1365
1362 hw_write_pci(hw, 0xcc, 0xee); 1366 hw_write_pci(hw, 0xcc, 0xee);
1363 hw_write_pci(hw, 0xcc, 0xaa); 1367 hw_write_pci(hw, 0xcc, 0xaa);
1364 if ((hw_read_pci(hw, 0xcc) & 0xff) == 1368 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
1365 return 0; 1369 return 0;
1366 1370
1367 return -1; 1371 return -1;
1368 } 1372 }
1369 1373
1370 static void i2c_lock(struct hw *hw) 1374 static void i2c_lock(struct hw *hw)
1371 { 1375 {
1372 if ((hw_read_pci(hw, 0xcc) & 0xff) == 1376 if ((hw_read_pci(hw, 0xcc) & 0xff) == 0xaa)
1373 hw_write_pci(hw, 0xcc, 0x00); 1377 hw_write_pci(hw, 0xcc, 0x00);
1374 } 1378 }
1375 1379
1376 static void i2c_write(struct hw *hw, u32 devi 1380 static void i2c_write(struct hw *hw, u32 device, u32 addr, u32 data)
1377 { 1381 {
1378 unsigned int ret; 1382 unsigned int ret;
1379 1383
1380 do { 1384 do {
1381 ret = hw_read_pci(hw, 0xEC); 1385 ret = hw_read_pci(hw, 0xEC);
1382 } while (!(ret & 0x800000)); 1386 } while (!(ret & 0x800000));
1383 hw_write_pci(hw, 0xE0, device); 1387 hw_write_pci(hw, 0xE0, device);
1384 hw_write_pci(hw, 0xE4, (data << 8) | 1388 hw_write_pci(hw, 0xE4, (data << 8) | (addr & 0xff));
1385 } 1389 }
1386 1390
1387 /* DAC operations */ 1391 /* DAC operations */
1388 1392
1389 static int hw_reset_dac(struct hw *hw) 1393 static int hw_reset_dac(struct hw *hw)
1390 { 1394 {
1391 u32 i; 1395 u32 i;
1392 u16 gpioorg; 1396 u16 gpioorg;
1393 unsigned int ret; 1397 unsigned int ret;
1394 1398
1395 if (i2c_unlock(hw)) 1399 if (i2c_unlock(hw))
1396 return -1; 1400 return -1;
1397 1401
1398 do { 1402 do {
1399 ret = hw_read_pci(hw, 0xEC); 1403 ret = hw_read_pci(hw, 0xEC);
1400 } while (!(ret & 0x800000)); 1404 } while (!(ret & 0x800000));
1401 hw_write_pci(hw, 0xEC, 0x05); /* wri 1405 hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */
1402 1406
1403 /* To be effective, need to reset the 1407 /* To be effective, need to reset the DAC twice. */
1404 for (i = 0; i < 2; i++) { 1408 for (i = 0; i < 2; i++) {
1405 /* set gpio */ 1409 /* set gpio */
1406 msleep(100); 1410 msleep(100);
1407 gpioorg = (u16)hw_read_20kx(h 1411 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1408 gpioorg &= 0xfffd; 1412 gpioorg &= 0xfffd;
1409 hw_write_20kx(hw, GPIO, gpioo 1413 hw_write_20kx(hw, GPIO, gpioorg);
1410 mdelay(1); 1414 mdelay(1);
1411 hw_write_20kx(hw, GPIO, gpioo 1415 hw_write_20kx(hw, GPIO, gpioorg | 0x2);
1412 } 1416 }
1413 1417
1414 i2c_write(hw, 0x00180080, 0x01, 0x80) 1418 i2c_write(hw, 0x00180080, 0x01, 0x80);
1415 i2c_write(hw, 0x00180080, 0x02, 0x10) 1419 i2c_write(hw, 0x00180080, 0x02, 0x10);
1416 1420
1417 i2c_lock(hw); 1421 i2c_lock(hw);
1418 1422
1419 return 0; 1423 return 0;
1420 } 1424 }
1421 1425
1422 static int hw_dac_init(struct hw *hw, const s 1426 static int hw_dac_init(struct hw *hw, const struct dac_conf *info)
1423 { 1427 {
1424 u32 data; 1428 u32 data;
1425 u16 gpioorg; 1429 u16 gpioorg;
1426 unsigned int ret; 1430 unsigned int ret;
1427 1431
1428 if (hw->model == CTSB055X) { 1432 if (hw->model == CTSB055X) {
1429 /* SB055x, unmute outputs */ 1433 /* SB055x, unmute outputs */
1430 gpioorg = (u16)hw_read_20kx(h 1434 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1431 gpioorg &= 0xffbf; /* se 1435 gpioorg &= 0xffbf; /* set GPIO6 to low */
1432 gpioorg |= 2; /* se 1436 gpioorg |= 2; /* set GPIO1 to high */
1433 hw_write_20kx(hw, GPIO, gpioo 1437 hw_write_20kx(hw, GPIO, gpioorg);
1434 return 0; 1438 return 0;
1435 } 1439 }
1436 1440
1437 /* mute outputs */ 1441 /* mute outputs */
1438 gpioorg = (u16)hw_read_20kx(hw, GPIO) 1442 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1439 gpioorg &= 0xffbf; 1443 gpioorg &= 0xffbf;
1440 hw_write_20kx(hw, GPIO, gpioorg); 1444 hw_write_20kx(hw, GPIO, gpioorg);
1441 1445
1442 hw_reset_dac(hw); 1446 hw_reset_dac(hw);
1443 1447
1444 if (i2c_unlock(hw)) 1448 if (i2c_unlock(hw))
1445 return -1; 1449 return -1;
1446 1450
1447 hw_write_pci(hw, 0xEC, 0x05); /* wri 1451 hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */
1448 do { 1452 do {
1449 ret = hw_read_pci(hw, 0xEC); 1453 ret = hw_read_pci(hw, 0xEC);
1450 } while (!(ret & 0x800000)); 1454 } while (!(ret & 0x800000));
1451 1455
1452 switch (info->msr) { 1456 switch (info->msr) {
1453 case 1: 1457 case 1:
1454 data = 0x24; 1458 data = 0x24;
1455 break; 1459 break;
1456 case 2: 1460 case 2:
1457 data = 0x25; 1461 data = 0x25;
1458 break; 1462 break;
1459 case 4: 1463 case 4:
1460 data = 0x26; 1464 data = 0x26;
1461 break; 1465 break;
1462 default: 1466 default:
1463 data = 0x24; 1467 data = 0x24;
1464 break; 1468 break;
1465 } 1469 }
1466 1470
1467 i2c_write(hw, 0x00180080, 0x06, data) 1471 i2c_write(hw, 0x00180080, 0x06, data);
1468 i2c_write(hw, 0x00180080, 0x09, data) 1472 i2c_write(hw, 0x00180080, 0x09, data);
1469 i2c_write(hw, 0x00180080, 0x0c, data) 1473 i2c_write(hw, 0x00180080, 0x0c, data);
1470 i2c_write(hw, 0x00180080, 0x0f, data) 1474 i2c_write(hw, 0x00180080, 0x0f, data);
1471 1475
1472 i2c_lock(hw); 1476 i2c_lock(hw);
1473 1477
1474 /* unmute outputs */ 1478 /* unmute outputs */
1475 gpioorg = (u16)hw_read_20kx(hw, GPIO) 1479 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1476 gpioorg = gpioorg | 0x40; 1480 gpioorg = gpioorg | 0x40;
1477 hw_write_20kx(hw, GPIO, gpioorg); 1481 hw_write_20kx(hw, GPIO, gpioorg);
1478 1482
1479 return 0; 1483 return 0;
1480 } 1484 }
1481 1485
1482 /* ADC operations */ 1486 /* ADC operations */
1483 1487
1484 static int is_adc_input_selected_SB055x(struc 1488 static int is_adc_input_selected_SB055x(struct hw *hw, enum ADCSRC type)
1485 { 1489 {
1486 return 0; 1490 return 0;
1487 } 1491 }
1488 1492
1489 static int is_adc_input_selected_SBx(struct h 1493 static int is_adc_input_selected_SBx(struct hw *hw, enum ADCSRC type)
1490 { 1494 {
1491 u32 data; 1495 u32 data;
1492 1496
1493 data = hw_read_20kx(hw, GPIO); 1497 data = hw_read_20kx(hw, GPIO);
1494 switch (type) { 1498 switch (type) {
1495 case ADC_MICIN: 1499 case ADC_MICIN:
1496 data = ((data & (0x1<<7)) && 1500 data = ((data & (0x1<<7)) && (data & (0x1<<8)));
1497 break; 1501 break;
1498 case ADC_LINEIN: 1502 case ADC_LINEIN:
1499 data = (!(data & (0x1<<7)) && 1503 data = (!(data & (0x1<<7)) && (data & (0x1<<8)));
1500 break; 1504 break;
1501 case ADC_NONE: /* Digital I/O */ 1505 case ADC_NONE: /* Digital I/O */
1502 data = (!(data & (0x1<<8))); 1506 data = (!(data & (0x1<<8)));
1503 break; 1507 break;
1504 default: 1508 default:
1505 data = 0; 1509 data = 0;
1506 } 1510 }
1507 return data; 1511 return data;
1508 } 1512 }
1509 1513
1510 static int is_adc_input_selected_hendrix(stru 1514 static int is_adc_input_selected_hendrix(struct hw *hw, enum ADCSRC type)
1511 { 1515 {
1512 u32 data; 1516 u32 data;
1513 1517
1514 data = hw_read_20kx(hw, GPIO); 1518 data = hw_read_20kx(hw, GPIO);
1515 switch (type) { 1519 switch (type) {
1516 case ADC_MICIN: 1520 case ADC_MICIN:
1517 data = (data & (0x1 << 7)) ? 1521 data = (data & (0x1 << 7)) ? 1 : 0;
1518 break; 1522 break;
1519 case ADC_LINEIN: 1523 case ADC_LINEIN:
1520 data = (data & (0x1 << 7)) ? 1524 data = (data & (0x1 << 7)) ? 0 : 1;
1521 break; 1525 break;
1522 default: 1526 default:
1523 data = 0; 1527 data = 0;
1524 } 1528 }
1525 return data; 1529 return data;
1526 } 1530 }
1527 1531
1528 static int hw_is_adc_input_selected(struct hw 1532 static int hw_is_adc_input_selected(struct hw *hw, enum ADCSRC type)
1529 { 1533 {
1530 switch (hw->model) { 1534 switch (hw->model) {
1531 case CTSB055X: 1535 case CTSB055X:
1532 return is_adc_input_selected_ 1536 return is_adc_input_selected_SB055x(hw, type);
1533 case CTSB073X: 1537 case CTSB073X:
1534 return is_adc_input_selected_ 1538 return is_adc_input_selected_hendrix(hw, type);
1535 case CTUAA: 1539 case CTUAA:
1536 return is_adc_input_selected_ 1540 return is_adc_input_selected_hendrix(hw, type);
1537 default: 1541 default:
1538 return is_adc_input_selected_ 1542 return is_adc_input_selected_SBx(hw, type);
1539 } 1543 }
1540 } 1544 }
1541 1545
1542 static int 1546 static int
1543 adc_input_select_SB055x(struct hw *hw, enum A 1547 adc_input_select_SB055x(struct hw *hw, enum ADCSRC type, unsigned char boost)
1544 { 1548 {
1545 u32 data; 1549 u32 data;
1546 1550
1547 /* 1551 /*
1548 * check and set the following GPIO b 1552 * check and set the following GPIO bits accordingly
1549 * ADC_Gain = GPIO2 1553 * ADC_Gain = GPIO2
1550 * DRM_off = GPIO3 1554 * DRM_off = GPIO3
1551 * Mic_Pwr_on = GPIO7 1555 * Mic_Pwr_on = GPIO7
1552 * Digital_IO_Sel = GPIO8 1556 * Digital_IO_Sel = GPIO8
1553 * Mic_Sw = GPIO9 1557 * Mic_Sw = GPIO9
1554 * Aux/MicLine_Sw = GPIO12 1558 * Aux/MicLine_Sw = GPIO12
1555 */ 1559 */
1556 data = hw_read_20kx(hw, GPIO); 1560 data = hw_read_20kx(hw, GPIO);
1557 data &= 0xec73; 1561 data &= 0xec73;
1558 switch (type) { 1562 switch (type) {
1559 case ADC_MICIN: 1563 case ADC_MICIN:
1560 data |= (0x1<<7) | (0x1<<8) | 1564 data |= (0x1<<7) | (0x1<<8) | (0x1<<9) ;
1561 data |= boost ? (0x1<<2) : 0; 1565 data |= boost ? (0x1<<2) : 0;
1562 break; 1566 break;
1563 case ADC_LINEIN: 1567 case ADC_LINEIN:
1564 data |= (0x1<<8); 1568 data |= (0x1<<8);
1565 break; 1569 break;
1566 case ADC_AUX: 1570 case ADC_AUX:
1567 data |= (0x1<<8) | (0x1<<12); 1571 data |= (0x1<<8) | (0x1<<12);
1568 break; 1572 break;
1569 case ADC_NONE: 1573 case ADC_NONE:
1570 data |= (0x1<<12); /* set to 1574 data |= (0x1<<12); /* set to digital */
1571 break; 1575 break;
1572 default: 1576 default:
1573 return -1; 1577 return -1;
1574 } 1578 }
1575 1579
1576 hw_write_20kx(hw, GPIO, data); 1580 hw_write_20kx(hw, GPIO, data);
1577 1581
1578 return 0; 1582 return 0;
1579 } 1583 }
1580 1584
1581 1585
1582 static int 1586 static int
1583 adc_input_select_SBx(struct hw *hw, enum ADCS 1587 adc_input_select_SBx(struct hw *hw, enum ADCSRC type, unsigned char boost)
1584 { 1588 {
1585 u32 data; 1589 u32 data;
1586 u32 i2c_data; 1590 u32 i2c_data;
1587 unsigned int ret; 1591 unsigned int ret;
1588 1592
1589 if (i2c_unlock(hw)) 1593 if (i2c_unlock(hw))
1590 return -1; 1594 return -1;
1591 1595
1592 do { 1596 do {
1593 ret = hw_read_pci(hw, 0xEC); 1597 ret = hw_read_pci(hw, 0xEC);
1594 } while (!(ret & 0x800000)); /* i2c r 1598 } while (!(ret & 0x800000)); /* i2c ready poll */
1595 /* set i2c access mode as Direct Cont 1599 /* set i2c access mode as Direct Control */
1596 hw_write_pci(hw, 0xEC, 0x05); 1600 hw_write_pci(hw, 0xEC, 0x05);
1597 1601
1598 data = hw_read_20kx(hw, GPIO); 1602 data = hw_read_20kx(hw, GPIO);
1599 switch (type) { 1603 switch (type) {
1600 case ADC_MICIN: 1604 case ADC_MICIN:
1601 data |= ((0x1 << 7) | (0x1 << 1605 data |= ((0x1 << 7) | (0x1 << 8));
1602 i2c_data = 0x1; /* Mic-in */ 1606 i2c_data = 0x1; /* Mic-in */
1603 break; 1607 break;
1604 case ADC_LINEIN: 1608 case ADC_LINEIN:
1605 data &= ~(0x1 << 7); 1609 data &= ~(0x1 << 7);
1606 data |= (0x1 << 8); 1610 data |= (0x1 << 8);
1607 i2c_data = 0x2; /* Line-in */ 1611 i2c_data = 0x2; /* Line-in */
1608 break; 1612 break;
1609 case ADC_NONE: 1613 case ADC_NONE:
1610 data &= ~(0x1 << 8); 1614 data &= ~(0x1 << 8);
1611 i2c_data = 0x0; /* set to Dig 1615 i2c_data = 0x0; /* set to Digital */
1612 break; 1616 break;
1613 default: 1617 default:
1614 i2c_lock(hw); 1618 i2c_lock(hw);
1615 return -1; 1619 return -1;
1616 } 1620 }
1617 hw_write_20kx(hw, GPIO, data); 1621 hw_write_20kx(hw, GPIO, data);
1618 i2c_write(hw, 0x001a0080, 0x2a, i2c_d 1622 i2c_write(hw, 0x001a0080, 0x2a, i2c_data);
1619 if (boost) { 1623 if (boost) {
1620 i2c_write(hw, 0x001a0080, 0x1 1624 i2c_write(hw, 0x001a0080, 0x1c, 0xe7); /* +12dB boost */
1621 i2c_write(hw, 0x001a0080, 0x1 1625 i2c_write(hw, 0x001a0080, 0x1e, 0xe7); /* +12dB boost */
1622 } else { 1626 } else {
1623 i2c_write(hw, 0x001a0080, 0x1 1627 i2c_write(hw, 0x001a0080, 0x1c, 0xcf); /* No boost */
1624 i2c_write(hw, 0x001a0080, 0x1 1628 i2c_write(hw, 0x001a0080, 0x1e, 0xcf); /* No boost */
1625 } 1629 }
1626 1630
1627 i2c_lock(hw); 1631 i2c_lock(hw);
1628 1632
1629 return 0; 1633 return 0;
1630 } 1634 }
1631 1635
1632 static int 1636 static int
1633 adc_input_select_hendrix(struct hw *hw, enum 1637 adc_input_select_hendrix(struct hw *hw, enum ADCSRC type, unsigned char boost)
1634 { 1638 {
1635 u32 data; 1639 u32 data;
1636 u32 i2c_data; 1640 u32 i2c_data;
1637 unsigned int ret; 1641 unsigned int ret;
1638 1642
1639 if (i2c_unlock(hw)) 1643 if (i2c_unlock(hw))
1640 return -1; 1644 return -1;
1641 1645
1642 do { 1646 do {
1643 ret = hw_read_pci(hw, 0xEC); 1647 ret = hw_read_pci(hw, 0xEC);
1644 } while (!(ret & 0x800000)); /* i2c r 1648 } while (!(ret & 0x800000)); /* i2c ready poll */
1645 /* set i2c access mode as Direct Cont 1649 /* set i2c access mode as Direct Control */
1646 hw_write_pci(hw, 0xEC, 0x05); 1650 hw_write_pci(hw, 0xEC, 0x05);
1647 1651
1648 data = hw_read_20kx(hw, GPIO); 1652 data = hw_read_20kx(hw, GPIO);
1649 switch (type) { 1653 switch (type) {
1650 case ADC_MICIN: 1654 case ADC_MICIN:
1651 data |= (0x1 << 7); 1655 data |= (0x1 << 7);
1652 i2c_data = 0x1; /* Mic-in */ 1656 i2c_data = 0x1; /* Mic-in */
1653 break; 1657 break;
1654 case ADC_LINEIN: 1658 case ADC_LINEIN:
1655 data &= ~(0x1 << 7); 1659 data &= ~(0x1 << 7);
1656 i2c_data = 0x2; /* Line-in */ 1660 i2c_data = 0x2; /* Line-in */
1657 break; 1661 break;
1658 default: 1662 default:
1659 i2c_lock(hw); 1663 i2c_lock(hw);
1660 return -1; 1664 return -1;
1661 } 1665 }
1662 hw_write_20kx(hw, GPIO, data); 1666 hw_write_20kx(hw, GPIO, data);
1663 i2c_write(hw, 0x001a0080, 0x2a, i2c_d 1667 i2c_write(hw, 0x001a0080, 0x2a, i2c_data);
1664 if (boost) { 1668 if (boost) {
1665 i2c_write(hw, 0x001a0080, 0x1 1669 i2c_write(hw, 0x001a0080, 0x1c, 0xe7); /* +12dB boost */
1666 i2c_write(hw, 0x001a0080, 0x1 1670 i2c_write(hw, 0x001a0080, 0x1e, 0xe7); /* +12dB boost */
1667 } else { 1671 } else {
1668 i2c_write(hw, 0x001a0080, 0x1 1672 i2c_write(hw, 0x001a0080, 0x1c, 0xcf); /* No boost */
1669 i2c_write(hw, 0x001a0080, 0x1 1673 i2c_write(hw, 0x001a0080, 0x1e, 0xcf); /* No boost */
1670 } 1674 }
1671 1675
1672 i2c_lock(hw); 1676 i2c_lock(hw);
1673 1677
1674 return 0; 1678 return 0;
1675 } 1679 }
1676 1680
1677 static int hw_adc_input_select(struct hw *hw, 1681 static int hw_adc_input_select(struct hw *hw, enum ADCSRC type)
1678 { 1682 {
1679 int state = type == ADC_MICIN; 1683 int state = type == ADC_MICIN;
1680 1684
1681 switch (hw->model) { 1685 switch (hw->model) {
1682 case CTSB055X: 1686 case CTSB055X:
1683 return adc_input_select_SB055 1687 return adc_input_select_SB055x(hw, type, state);
1684 case CTSB073X: 1688 case CTSB073X:
1685 return adc_input_select_hendr 1689 return adc_input_select_hendrix(hw, type, state);
1686 case CTUAA: 1690 case CTUAA:
1687 return adc_input_select_hendr 1691 return adc_input_select_hendrix(hw, type, state);
1688 default: 1692 default:
1689 return adc_input_select_SBx(h 1693 return adc_input_select_SBx(hw, type, state);
1690 } 1694 }
1691 } 1695 }
1692 1696
1693 static int adc_init_SB055x(struct hw *hw, int 1697 static int adc_init_SB055x(struct hw *hw, int input, int mic20db)
1694 { 1698 {
1695 return adc_input_select_SB055x(hw, in 1699 return adc_input_select_SB055x(hw, input, mic20db);
1696 } 1700 }
1697 1701
1698 static int adc_init_SBx(struct hw *hw, int in 1702 static int adc_init_SBx(struct hw *hw, int input, int mic20db)
1699 { 1703 {
1700 u16 gpioorg; 1704 u16 gpioorg;
1701 u16 input_source; 1705 u16 input_source;
1702 u32 adcdata; 1706 u32 adcdata;
1703 unsigned int ret; 1707 unsigned int ret;
1704 1708
1705 input_source = 0x100; /* default to 1709 input_source = 0x100; /* default to analog */
1706 switch (input) { 1710 switch (input) {
1707 case ADC_MICIN: 1711 case ADC_MICIN:
1708 adcdata = 0x1; 1712 adcdata = 0x1;
1709 input_source = 0x180; /* set 1713 input_source = 0x180; /* set GPIO7 to select Mic */
1710 break; 1714 break;
1711 case ADC_LINEIN: 1715 case ADC_LINEIN:
1712 adcdata = 0x2; 1716 adcdata = 0x2;
1713 break; 1717 break;
1714 case ADC_VIDEO: 1718 case ADC_VIDEO:
1715 adcdata = 0x4; 1719 adcdata = 0x4;
1716 break; 1720 break;
1717 case ADC_AUX: 1721 case ADC_AUX:
1718 adcdata = 0x8; 1722 adcdata = 0x8;
1719 break; 1723 break;
1720 case ADC_NONE: 1724 case ADC_NONE:
1721 adcdata = 0x0; 1725 adcdata = 0x0;
1722 input_source = 0x0; /* set t 1726 input_source = 0x0; /* set to Digital */
1723 break; 1727 break;
1724 default: 1728 default:
1725 adcdata = 0x0; 1729 adcdata = 0x0;
1726 break; 1730 break;
1727 } 1731 }
1728 1732
1729 if (i2c_unlock(hw)) 1733 if (i2c_unlock(hw))
1730 return -1; 1734 return -1;
1731 1735
1732 do { 1736 do {
1733 ret = hw_read_pci(hw, 0xEC); 1737 ret = hw_read_pci(hw, 0xEC);
1734 } while (!(ret & 0x800000)); /* i2c r 1738 } while (!(ret & 0x800000)); /* i2c ready poll */
1735 hw_write_pci(hw, 0xEC, 0x05); /* wri 1739 hw_write_pci(hw, 0xEC, 0x05); /* write to i2c status control */
1736 1740
1737 i2c_write(hw, 0x001a0080, 0x0e, 0x08) 1741 i2c_write(hw, 0x001a0080, 0x0e, 0x08);
1738 i2c_write(hw, 0x001a0080, 0x18, 0x0a) 1742 i2c_write(hw, 0x001a0080, 0x18, 0x0a);
1739 i2c_write(hw, 0x001a0080, 0x28, 0x86) 1743 i2c_write(hw, 0x001a0080, 0x28, 0x86);
1740 i2c_write(hw, 0x001a0080, 0x2a, adcda 1744 i2c_write(hw, 0x001a0080, 0x2a, adcdata);
1741 1745
1742 if (mic20db) { 1746 if (mic20db) {
1743 i2c_write(hw, 0x001a0080, 0x1 1747 i2c_write(hw, 0x001a0080, 0x1c, 0xf7);
1744 i2c_write(hw, 0x001a0080, 0x1 1748 i2c_write(hw, 0x001a0080, 0x1e, 0xf7);
1745 } else { 1749 } else {
1746 i2c_write(hw, 0x001a0080, 0x1 1750 i2c_write(hw, 0x001a0080, 0x1c, 0xcf);
1747 i2c_write(hw, 0x001a0080, 0x1 1751 i2c_write(hw, 0x001a0080, 0x1e, 0xcf);
1748 } 1752 }
1749 1753
1750 if (!(hw_read_20kx(hw, ID0) & 0x100)) 1754 if (!(hw_read_20kx(hw, ID0) & 0x100))
1751 i2c_write(hw, 0x001a0080, 0x1 1755 i2c_write(hw, 0x001a0080, 0x16, 0x26);
1752 1756
1753 i2c_lock(hw); 1757 i2c_lock(hw);
1754 1758
1755 gpioorg = (u16)hw_read_20kx(hw, GPIO 1759 gpioorg = (u16)hw_read_20kx(hw, GPIO);
1756 gpioorg &= 0xfe7f; 1760 gpioorg &= 0xfe7f;
1757 gpioorg |= input_source; 1761 gpioorg |= input_source;
1758 hw_write_20kx(hw, GPIO, gpioorg); 1762 hw_write_20kx(hw, GPIO, gpioorg);
1759 1763
1760 return 0; 1764 return 0;
1761 } 1765 }
1762 1766
1763 static int hw_adc_init(struct hw *hw, const s 1767 static int hw_adc_init(struct hw *hw, const struct adc_conf *info)
1764 { 1768 {
1765 if (hw->model == CTSB055X) 1769 if (hw->model == CTSB055X)
1766 return adc_init_SB055x(hw, in 1770 return adc_init_SB055x(hw, info->input, info->mic20db);
1767 else 1771 else
1768 return adc_init_SBx(hw, info- 1772 return adc_init_SBx(hw, info->input, info->mic20db);
1769 } 1773 }
1770 1774
1771 static struct capabilities hw_capabilities(st 1775 static struct capabilities hw_capabilities(struct hw *hw)
1772 { 1776 {
1773 struct capabilities cap; 1777 struct capabilities cap;
1774 1778
1775 /* SB073x and Vista compatible cards 1779 /* SB073x and Vista compatible cards have no digit IO switch */
1776 cap.digit_io_switch = !(hw->model == 1780 cap.digit_io_switch = !(hw->model == CTSB073X || hw->model == CTUAA);
1777 cap.dedicated_mic = 0; 1781 cap.dedicated_mic = 0;
1778 cap.output_switch = 0; 1782 cap.output_switch = 0;
1779 cap.mic_source_switch = 0; 1783 cap.mic_source_switch = 0;
1780 1784
1781 return cap; 1785 return cap;
1782 } 1786 }
1783 1787
1784 #define CTLBITS(a, b, c, d) (((a) << 24) 1788 #define CTLBITS(a, b, c, d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d))
1785 1789
1786 #define UAA_CFG_PWRSTATUS 0x44 1790 #define UAA_CFG_PWRSTATUS 0x44
1787 #define UAA_CFG_SPACE_FLAG 0xA0 1791 #define UAA_CFG_SPACE_FLAG 0xA0
1788 #define UAA_CORE_CHANGE 0x3FFC 1792 #define UAA_CORE_CHANGE 0x3FFC
1789 static int uaa_to_xfi(struct pci_dev *pci) 1793 static int uaa_to_xfi(struct pci_dev *pci)
1790 { 1794 {
1791 unsigned int bar0, bar1, bar2, bar3, 1795 unsigned int bar0, bar1, bar2, bar3, bar4, bar5;
1792 unsigned int cmd, irq, cl_size, l_tim 1796 unsigned int cmd, irq, cl_size, l_timer, pwr;
1793 unsigned int is_uaa; 1797 unsigned int is_uaa;
1794 unsigned int data[4] = {0}; 1798 unsigned int data[4] = {0};
1795 unsigned int io_base; 1799 unsigned int io_base;
1796 void __iomem *mem_base; 1800 void __iomem *mem_base;
1797 int i; 1801 int i;
1798 const u32 CTLX = CTLBITS('C', 'T', 'L 1802 const u32 CTLX = CTLBITS('C', 'T', 'L', 'X');
1799 const u32 CTL_ = CTLBITS('C', 'T', 'L 1803 const u32 CTL_ = CTLBITS('C', 'T', 'L', '-');
1800 const u32 CTLF = CTLBITS('C', 'T', 'L 1804 const u32 CTLF = CTLBITS('C', 'T', 'L', 'F');
1801 const u32 CTLi = CTLBITS('C', 'T', 'L 1805 const u32 CTLi = CTLBITS('C', 'T', 'L', 'i');
1802 const u32 CTLA = CTLBITS('C', 'T', 'L 1806 const u32 CTLA = CTLBITS('C', 'T', 'L', 'A');
1803 const u32 CTLZ = CTLBITS('C', 'T', 'L 1807 const u32 CTLZ = CTLBITS('C', 'T', 'L', 'Z');
1804 const u32 CTLL = CTLBITS('C', 'T', 'L 1808 const u32 CTLL = CTLBITS('C', 'T', 'L', 'L');
1805 1809
1806 /* By default, Hendrix card UAA Bar0 1810 /* By default, Hendrix card UAA Bar0 should be using memory... */
1807 io_base = pci_resource_start(pci, 0); 1811 io_base = pci_resource_start(pci, 0);
1808 mem_base = ioremap(io_base, pci_resou 1812 mem_base = ioremap(io_base, pci_resource_len(pci, 0));
1809 if (!mem_base) 1813 if (!mem_base)
1810 return -ENOENT; 1814 return -ENOENT;
1811 1815
1812 /* Read current mode from Mode Change 1816 /* Read current mode from Mode Change Register */
1813 for (i = 0; i < 4; i++) 1817 for (i = 0; i < 4; i++)
1814 data[i] = readl(mem_base + UA 1818 data[i] = readl(mem_base + UAA_CORE_CHANGE);
1815 1819
1816 /* Determine current mode... */ 1820 /* Determine current mode... */
1817 if (data[0] == CTLA) { 1821 if (data[0] == CTLA) {
1818 is_uaa = ((data[1] == CTLZ && 1822 is_uaa = ((data[1] == CTLZ && data[2] == CTLL
1819 && data[3] == CTLA) 1823 && data[3] == CTLA) || (data[1] == CTLA
1820 && data[2] == CTLZ 1824 && data[2] == CTLZ && data[3] == CTLL));
1821 } else if (data[0] == CTLZ) { 1825 } else if (data[0] == CTLZ) {
1822 is_uaa = (data[1] == CTLL 1826 is_uaa = (data[1] == CTLL
1823 && data[2] == 1827 && data[2] == CTLA && data[3] == CTLA);
1824 } else if (data[0] == CTLL) { 1828 } else if (data[0] == CTLL) {
1825 is_uaa = (data[1] == CTLA 1829 is_uaa = (data[1] == CTLA
1826 && data[2] == 1830 && data[2] == CTLA && data[3] == CTLZ);
1827 } else { 1831 } else {
1828 is_uaa = 0; 1832 is_uaa = 0;
1829 } 1833 }
1830 1834
1831 if (!is_uaa) { 1835 if (!is_uaa) {
1832 /* Not in UAA mode currently. 1836 /* Not in UAA mode currently. Return directly. */
1833 iounmap(mem_base); 1837 iounmap(mem_base);
1834 return 0; 1838 return 0;
1835 } 1839 }
1836 1840
1837 pci_read_config_dword(pci, PCI_BASE_A 1841 pci_read_config_dword(pci, PCI_BASE_ADDRESS_0, &bar0);
1838 pci_read_config_dword(pci, PCI_BASE_A 1842 pci_read_config_dword(pci, PCI_BASE_ADDRESS_1, &bar1);
1839 pci_read_config_dword(pci, PCI_BASE_A 1843 pci_read_config_dword(pci, PCI_BASE_ADDRESS_2, &bar2);
1840 pci_read_config_dword(pci, PCI_BASE_A 1844 pci_read_config_dword(pci, PCI_BASE_ADDRESS_3, &bar3);
1841 pci_read_config_dword(pci, PCI_BASE_A 1845 pci_read_config_dword(pci, PCI_BASE_ADDRESS_4, &bar4);
1842 pci_read_config_dword(pci, PCI_BASE_A 1846 pci_read_config_dword(pci, PCI_BASE_ADDRESS_5, &bar5);
1843 pci_read_config_dword(pci, PCI_INTERR 1847 pci_read_config_dword(pci, PCI_INTERRUPT_LINE, &irq);
1844 pci_read_config_dword(pci, PCI_CACHE_ 1848 pci_read_config_dword(pci, PCI_CACHE_LINE_SIZE, &cl_size);
1845 pci_read_config_dword(pci, PCI_LATENC 1849 pci_read_config_dword(pci, PCI_LATENCY_TIMER, &l_timer);
1846 pci_read_config_dword(pci, UAA_CFG_PW 1850 pci_read_config_dword(pci, UAA_CFG_PWRSTATUS, &pwr);
1847 pci_read_config_dword(pci, PCI_COMMAN 1851 pci_read_config_dword(pci, PCI_COMMAND, &cmd);
1848 1852
1849 /* Set up X-Fi core PCI configuration 1853 /* Set up X-Fi core PCI configuration space. */
1850 /* Switch to X-Fi config space with B 1854 /* Switch to X-Fi config space with BAR0 exposed. */
1851 pci_write_config_dword(pci, UAA_CFG_S 1855 pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x87654321);
1852 /* Copy UAA's BAR5 into X-Fi BAR0 */ 1856 /* Copy UAA's BAR5 into X-Fi BAR0 */
1853 pci_write_config_dword(pci, PCI_BASE_ 1857 pci_write_config_dword(pci, PCI_BASE_ADDRESS_0, bar5);
1854 /* Switch to X-Fi config space withou 1858 /* Switch to X-Fi config space without BAR0 exposed. */
1855 pci_write_config_dword(pci, UAA_CFG_S 1859 pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x12345678);
1856 pci_write_config_dword(pci, PCI_BASE_ 1860 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, bar1);
1857 pci_write_config_dword(pci, PCI_BASE_ 1861 pci_write_config_dword(pci, PCI_BASE_ADDRESS_2, bar2);
1858 pci_write_config_dword(pci, PCI_BASE_ 1862 pci_write_config_dword(pci, PCI_BASE_ADDRESS_3, bar3);
1859 pci_write_config_dword(pci, PCI_BASE_ 1863 pci_write_config_dword(pci, PCI_BASE_ADDRESS_4, bar4);
1860 pci_write_config_dword(pci, PCI_INTER 1864 pci_write_config_dword(pci, PCI_INTERRUPT_LINE, irq);
1861 pci_write_config_dword(pci, PCI_CACHE 1865 pci_write_config_dword(pci, PCI_CACHE_LINE_SIZE, cl_size);
1862 pci_write_config_dword(pci, PCI_LATEN 1866 pci_write_config_dword(pci, PCI_LATENCY_TIMER, l_timer);
1863 pci_write_config_dword(pci, UAA_CFG_P 1867 pci_write_config_dword(pci, UAA_CFG_PWRSTATUS, pwr);
1864 pci_write_config_dword(pci, PCI_COMMA 1868 pci_write_config_dword(pci, PCI_COMMAND, cmd);
1865 1869
1866 /* Switch to X-Fi mode */ 1870 /* Switch to X-Fi mode */
1867 writel(CTLX, (mem_base + UAA_CORE_CHA 1871 writel(CTLX, (mem_base + UAA_CORE_CHANGE));
1868 writel(CTL_, (mem_base + UAA_CORE_CHA 1872 writel(CTL_, (mem_base + UAA_CORE_CHANGE));
1869 writel(CTLF, (mem_base + UAA_CORE_CHA 1873 writel(CTLF, (mem_base + UAA_CORE_CHANGE));
1870 writel(CTLi, (mem_base + UAA_CORE_CHA 1874 writel(CTLi, (mem_base + UAA_CORE_CHANGE));
1871 1875
1872 iounmap(mem_base); 1876 iounmap(mem_base);
1873 1877
1874 return 0; 1878 return 0;
1875 } 1879 }
1876 1880
1877 static irqreturn_t ct_20k1_interrupt(int irq, 1881 static irqreturn_t ct_20k1_interrupt(int irq, void *dev_id)
1878 { 1882 {
1879 struct hw *hw = dev_id; 1883 struct hw *hw = dev_id;
1880 unsigned int status; 1884 unsigned int status;
1881 1885
1882 status = hw_read_20kx(hw, GIP); 1886 status = hw_read_20kx(hw, GIP);
1883 if (!status) 1887 if (!status)
1884 return IRQ_NONE; 1888 return IRQ_NONE;
1885 1889
1886 if (hw->irq_callback) 1890 if (hw->irq_callback)
1887 hw->irq_callback(hw->irq_call 1891 hw->irq_callback(hw->irq_callback_data, status);
1888 1892
1889 hw_write_20kx(hw, GIP, status); 1893 hw_write_20kx(hw, GIP, status);
1890 return IRQ_HANDLED; 1894 return IRQ_HANDLED;
1891 } 1895 }
1892 1896
1893 static int hw_card_start(struct hw *hw) 1897 static int hw_card_start(struct hw *hw)
1894 { 1898 {
1895 int err; 1899 int err;
1896 struct pci_dev *pci = hw->pci; 1900 struct pci_dev *pci = hw->pci;
1897 const unsigned int dma_bits = BITS_PE 1901 const unsigned int dma_bits = BITS_PER_LONG;
1898 1902
1899 err = pci_enable_device(pci); 1903 err = pci_enable_device(pci);
1900 if (err < 0) 1904 if (err < 0)
1901 return err; 1905 return err;
1902 1906
1903 /* Set DMA transfer mask */ 1907 /* Set DMA transfer mask */
1904 if (dma_set_mask_and_coherent(&pci->d !! 1908 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) {
1905 dma_set_mask_and_coherent(&pc !! 1909 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits));
>> 1910 } else {
>> 1911 dma_set_mask(&pci->dev, DMA_BIT_MASK(32));
>> 1912 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32));
>> 1913 }
1906 1914
1907 if (!hw->io_base) { 1915 if (!hw->io_base) {
1908 err = pci_request_regions(pci 1916 err = pci_request_regions(pci, "XFi");
1909 if (err < 0) 1917 if (err < 0)
1910 goto error1; 1918 goto error1;
1911 1919
1912 if (hw->model == CTUAA) 1920 if (hw->model == CTUAA)
1913 hw->io_base = pci_res 1921 hw->io_base = pci_resource_start(pci, 5);
1914 else 1922 else
1915 hw->io_base = pci_res 1923 hw->io_base = pci_resource_start(pci, 0);
1916 1924
1917 } 1925 }
1918 1926
1919 /* Switch to X-Fi mode from UAA mode !! 1927 /* Switch to X-Fi mode from UAA mode if neeeded */
1920 if (hw->model == CTUAA) { 1928 if (hw->model == CTUAA) {
1921 err = uaa_to_xfi(pci); 1929 err = uaa_to_xfi(pci);
1922 if (err) 1930 if (err)
1923 goto error2; 1931 goto error2;
1924 1932
1925 } 1933 }
1926 1934
1927 if (hw->irq < 0) { 1935 if (hw->irq < 0) {
1928 err = request_irq(pci->irq, c 1936 err = request_irq(pci->irq, ct_20k1_interrupt, IRQF_SHARED,
1929 KBUILD_MODN 1937 KBUILD_MODNAME, hw);
1930 if (err < 0) { 1938 if (err < 0) {
1931 dev_err(hw->card->dev 1939 dev_err(hw->card->dev,
1932 "XFi: Cannot 1940 "XFi: Cannot get irq %d\n", pci->irq);
1933 goto error2; 1941 goto error2;
1934 } 1942 }
1935 hw->irq = pci->irq; 1943 hw->irq = pci->irq;
1936 hw->card->sync_irq = hw->irq; <<
1937 } 1944 }
1938 1945
1939 pci_set_master(pci); 1946 pci_set_master(pci);
1940 1947
1941 return 0; 1948 return 0;
1942 1949
1943 error2: 1950 error2:
1944 pci_release_regions(pci); 1951 pci_release_regions(pci);
1945 hw->io_base = 0; 1952 hw->io_base = 0;
1946 error1: 1953 error1:
1947 pci_disable_device(pci); 1954 pci_disable_device(pci);
1948 return err; 1955 return err;
1949 } 1956 }
1950 1957
1951 static int hw_card_stop(struct hw *hw) 1958 static int hw_card_stop(struct hw *hw)
1952 { 1959 {
1953 unsigned int data; 1960 unsigned int data;
1954 1961
1955 /* disable transport bus master and q 1962 /* disable transport bus master and queueing of request */
1956 hw_write_20kx(hw, TRNCTL, 0x00); 1963 hw_write_20kx(hw, TRNCTL, 0x00);
1957 1964
1958 /* disable pll */ 1965 /* disable pll */
1959 data = hw_read_20kx(hw, PLLCTL); 1966 data = hw_read_20kx(hw, PLLCTL);
1960 hw_write_20kx(hw, PLLCTL, (data & (~( 1967 hw_write_20kx(hw, PLLCTL, (data & (~(0x0F<<12))));
1961 1968
>> 1969 /* TODO: Disable interrupt and so on... */
>> 1970 if (hw->irq >= 0)
>> 1971 synchronize_irq(hw->irq);
1962 return 0; 1972 return 0;
1963 } 1973 }
1964 1974
1965 static int hw_card_shutdown(struct hw *hw) 1975 static int hw_card_shutdown(struct hw *hw)
1966 { 1976 {
1967 if (hw->irq >= 0) 1977 if (hw->irq >= 0)
1968 free_irq(hw->irq, hw); 1978 free_irq(hw->irq, hw);
1969 1979
1970 hw->irq = -1; 1980 hw->irq = -1;
1971 iounmap(hw->mem_base); 1981 iounmap(hw->mem_base);
1972 hw->mem_base = NULL; 1982 hw->mem_base = NULL;
1973 1983
1974 if (hw->io_base) 1984 if (hw->io_base)
1975 pci_release_regions(hw->pci); 1985 pci_release_regions(hw->pci);
1976 1986
1977 hw->io_base = 0; 1987 hw->io_base = 0;
1978 1988
1979 pci_disable_device(hw->pci); 1989 pci_disable_device(hw->pci);
1980 1990
1981 return 0; 1991 return 0;
1982 } 1992 }
1983 1993
1984 static int hw_card_init(struct hw *hw, struct 1994 static int hw_card_init(struct hw *hw, struct card_conf *info)
1985 { 1995 {
1986 int err; 1996 int err;
1987 unsigned int gctl; 1997 unsigned int gctl;
1988 u32 data; 1998 u32 data;
1989 struct dac_conf dac_info = {0}; 1999 struct dac_conf dac_info = {0};
1990 struct adc_conf adc_info = {0}; 2000 struct adc_conf adc_info = {0};
1991 struct daio_conf daio_info = {0}; 2001 struct daio_conf daio_info = {0};
1992 struct trn_conf trn_info = {0}; 2002 struct trn_conf trn_info = {0};
1993 2003
1994 /* Get PCI io port base address and d 2004 /* Get PCI io port base address and do Hendrix switch if needed. */
1995 err = hw_card_start(hw); 2005 err = hw_card_start(hw);
1996 if (err) 2006 if (err)
1997 return err; 2007 return err;
1998 2008
1999 /* PLL init */ 2009 /* PLL init */
2000 err = hw_pll_init(hw, info->rsr); 2010 err = hw_pll_init(hw, info->rsr);
2001 if (err < 0) 2011 if (err < 0)
2002 return err; 2012 return err;
2003 2013
2004 /* kick off auto-init */ 2014 /* kick off auto-init */
2005 err = hw_auto_init(hw); 2015 err = hw_auto_init(hw);
2006 if (err < 0) 2016 if (err < 0)
2007 return err; 2017 return err;
2008 2018
2009 /* Enable audio ring */ 2019 /* Enable audio ring */
2010 gctl = hw_read_20kx(hw, GCTL); 2020 gctl = hw_read_20kx(hw, GCTL);
2011 set_field(&gctl, GCTL_EAC, 1); 2021 set_field(&gctl, GCTL_EAC, 1);
2012 set_field(&gctl, GCTL_DBP, 1); 2022 set_field(&gctl, GCTL_DBP, 1);
2013 set_field(&gctl, GCTL_TBP, 1); 2023 set_field(&gctl, GCTL_TBP, 1);
2014 set_field(&gctl, GCTL_FBP, 1); 2024 set_field(&gctl, GCTL_FBP, 1);
2015 set_field(&gctl, GCTL_ET, 1); 2025 set_field(&gctl, GCTL_ET, 1);
2016 hw_write_20kx(hw, GCTL, gctl); 2026 hw_write_20kx(hw, GCTL, gctl);
2017 mdelay(10); 2027 mdelay(10);
2018 2028
2019 /* Reset all global pending interrupt 2029 /* Reset all global pending interrupts */
2020 hw_write_20kx(hw, GIE, 0); 2030 hw_write_20kx(hw, GIE, 0);
2021 /* Reset all SRC pending interrupts * 2031 /* Reset all SRC pending interrupts */
2022 hw_write_20kx(hw, SRCIP, 0); 2032 hw_write_20kx(hw, SRCIP, 0);
2023 msleep(30); 2033 msleep(30);
2024 2034
2025 /* Detect the card ID and configure G 2035 /* Detect the card ID and configure GPIO accordingly. */
2026 switch (hw->model) { 2036 switch (hw->model) {
2027 case CTSB055X: 2037 case CTSB055X:
2028 hw_write_20kx(hw, GPIOCTL, 0x 2038 hw_write_20kx(hw, GPIOCTL, 0x13fe);
2029 break; 2039 break;
2030 case CTSB073X: 2040 case CTSB073X:
2031 hw_write_20kx(hw, GPIOCTL, 0x 2041 hw_write_20kx(hw, GPIOCTL, 0x00e6);
2032 break; 2042 break;
2033 case CTUAA: 2043 case CTUAA:
2034 hw_write_20kx(hw, GPIOCTL, 0x 2044 hw_write_20kx(hw, GPIOCTL, 0x00c2);
2035 break; 2045 break;
2036 default: 2046 default:
2037 hw_write_20kx(hw, GPIOCTL, 0x 2047 hw_write_20kx(hw, GPIOCTL, 0x01e6);
2038 break; 2048 break;
2039 } 2049 }
2040 2050
2041 trn_info.vm_pgt_phys = info->vm_pgt_p 2051 trn_info.vm_pgt_phys = info->vm_pgt_phys;
2042 err = hw_trn_init(hw, &trn_info); 2052 err = hw_trn_init(hw, &trn_info);
2043 if (err < 0) 2053 if (err < 0)
2044 return err; 2054 return err;
2045 2055
2046 daio_info.msr = info->msr; 2056 daio_info.msr = info->msr;
2047 err = hw_daio_init(hw, &daio_info); 2057 err = hw_daio_init(hw, &daio_info);
2048 if (err < 0) 2058 if (err < 0)
2049 return err; 2059 return err;
2050 2060
2051 dac_info.msr = info->msr; 2061 dac_info.msr = info->msr;
2052 err = hw_dac_init(hw, &dac_info); 2062 err = hw_dac_init(hw, &dac_info);
2053 if (err < 0) 2063 if (err < 0)
2054 return err; 2064 return err;
2055 2065
2056 adc_info.msr = info->msr; 2066 adc_info.msr = info->msr;
2057 adc_info.input = ADC_LINEIN; 2067 adc_info.input = ADC_LINEIN;
2058 adc_info.mic20db = 0; 2068 adc_info.mic20db = 0;
2059 err = hw_adc_init(hw, &adc_info); 2069 err = hw_adc_init(hw, &adc_info);
2060 if (err < 0) 2070 if (err < 0)
2061 return err; 2071 return err;
2062 2072
2063 data = hw_read_20kx(hw, SRCMCTL); 2073 data = hw_read_20kx(hw, SRCMCTL);
2064 data |= 0x1; /* Enables input from th 2074 data |= 0x1; /* Enables input from the audio ring */
2065 hw_write_20kx(hw, SRCMCTL, data); 2075 hw_write_20kx(hw, SRCMCTL, data);
2066 2076
2067 return 0; 2077 return 0;
2068 } 2078 }
2069 2079
2070 #ifdef CONFIG_PM_SLEEP 2080 #ifdef CONFIG_PM_SLEEP
2071 static int hw_suspend(struct hw *hw) 2081 static int hw_suspend(struct hw *hw)
2072 { 2082 {
2073 struct pci_dev *pci = hw->pci; 2083 struct pci_dev *pci = hw->pci;
2074 2084
2075 hw_card_stop(hw); 2085 hw_card_stop(hw);
2076 2086
2077 if (hw->model == CTUAA) { 2087 if (hw->model == CTUAA) {
2078 /* Switch to UAA config space 2088 /* Switch to UAA config space. */
2079 pci_write_config_dword(pci, U 2089 pci_write_config_dword(pci, UAA_CFG_SPACE_FLAG, 0x0);
2080 } 2090 }
2081 2091
2082 return 0; 2092 return 0;
2083 } 2093 }
2084 2094
2085 static int hw_resume(struct hw *hw, struct ca 2095 static int hw_resume(struct hw *hw, struct card_conf *info)
2086 { 2096 {
2087 /* Re-initialize card hardware. */ 2097 /* Re-initialize card hardware. */
2088 return hw_card_init(hw, info); 2098 return hw_card_init(hw, info);
2089 } 2099 }
2090 #endif 2100 #endif
2091 2101
2092 static u32 hw_read_20kx(struct hw *hw, u32 re 2102 static u32 hw_read_20kx(struct hw *hw, u32 reg)
2093 { 2103 {
2094 u32 value; 2104 u32 value;
2095 unsigned long flags; 2105 unsigned long flags;
2096 2106
2097 spin_lock_irqsave( 2107 spin_lock_irqsave(
2098 &container_of(hw, struct hw20 2108 &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
2099 outl(reg, hw->io_base + 0x0); 2109 outl(reg, hw->io_base + 0x0);
2100 value = inl(hw->io_base + 0x4); 2110 value = inl(hw->io_base + 0x4);
2101 spin_unlock_irqrestore( 2111 spin_unlock_irqrestore(
2102 &container_of(hw, struct hw20 2112 &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
2103 2113
2104 return value; 2114 return value;
2105 } 2115 }
2106 2116
2107 static void hw_write_20kx(struct hw *hw, u32 2117 static void hw_write_20kx(struct hw *hw, u32 reg, u32 data)
2108 { 2118 {
2109 unsigned long flags; 2119 unsigned long flags;
2110 2120
2111 spin_lock_irqsave( 2121 spin_lock_irqsave(
2112 &container_of(hw, struct hw20 2122 &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
2113 outl(reg, hw->io_base + 0x0); 2123 outl(reg, hw->io_base + 0x0);
2114 outl(data, hw->io_base + 0x4); 2124 outl(data, hw->io_base + 0x4);
2115 spin_unlock_irqrestore( 2125 spin_unlock_irqrestore(
2116 &container_of(hw, struct hw20 2126 &container_of(hw, struct hw20k1, hw)->reg_20k1_lock, flags);
2117 2127
2118 } 2128 }
2119 2129
2120 static u32 hw_read_pci(struct hw *hw, u32 reg 2130 static u32 hw_read_pci(struct hw *hw, u32 reg)
2121 { 2131 {
2122 u32 value; 2132 u32 value;
2123 unsigned long flags; 2133 unsigned long flags;
2124 2134
2125 spin_lock_irqsave( 2135 spin_lock_irqsave(
2126 &container_of(hw, struct hw20 2136 &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
2127 outl(reg, hw->io_base + 0x10); 2137 outl(reg, hw->io_base + 0x10);
2128 value = inl(hw->io_base + 0x14); 2138 value = inl(hw->io_base + 0x14);
2129 spin_unlock_irqrestore( 2139 spin_unlock_irqrestore(
2130 &container_of(hw, struct hw20 2140 &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
2131 2141
2132 return value; 2142 return value;
2133 } 2143 }
2134 2144
2135 static void hw_write_pci(struct hw *hw, u32 r 2145 static void hw_write_pci(struct hw *hw, u32 reg, u32 data)
2136 { 2146 {
2137 unsigned long flags; 2147 unsigned long flags;
2138 2148
2139 spin_lock_irqsave( 2149 spin_lock_irqsave(
2140 &container_of(hw, struct hw20 2150 &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
2141 outl(reg, hw->io_base + 0x10); 2151 outl(reg, hw->io_base + 0x10);
2142 outl(data, hw->io_base + 0x14); 2152 outl(data, hw->io_base + 0x14);
2143 spin_unlock_irqrestore( 2153 spin_unlock_irqrestore(
2144 &container_of(hw, struct hw20 2154 &container_of(hw, struct hw20k1, hw)->reg_pci_lock, flags);
2145 } 2155 }
2146 2156
2147 static const struct hw ct20k1_preset = { 2157 static const struct hw ct20k1_preset = {
2148 .irq = -1, 2158 .irq = -1,
2149 2159
2150 .card_init = hw_card_init, 2160 .card_init = hw_card_init,
2151 .card_stop = hw_card_stop, 2161 .card_stop = hw_card_stop,
2152 .pll_init = hw_pll_init, 2162 .pll_init = hw_pll_init,
2153 .is_adc_source_selected = hw_is_adc_i 2163 .is_adc_source_selected = hw_is_adc_input_selected,
2154 .select_adc_source = hw_adc_input_sel 2164 .select_adc_source = hw_adc_input_select,
2155 .capabilities = hw_capabilities, 2165 .capabilities = hw_capabilities,
2156 #ifdef CONFIG_PM_SLEEP 2166 #ifdef CONFIG_PM_SLEEP
2157 .suspend = hw_suspend, 2167 .suspend = hw_suspend,
2158 .resume = hw_resume, 2168 .resume = hw_resume,
2159 #endif 2169 #endif
2160 2170
2161 .src_rsc_get_ctrl_blk = src_get_rsc_c 2171 .src_rsc_get_ctrl_blk = src_get_rsc_ctrl_blk,
2162 .src_rsc_put_ctrl_blk = src_put_rsc_c 2172 .src_rsc_put_ctrl_blk = src_put_rsc_ctrl_blk,
2163 .src_mgr_get_ctrl_blk = src_mgr_get_c 2173 .src_mgr_get_ctrl_blk = src_mgr_get_ctrl_blk,
2164 .src_mgr_put_ctrl_blk = src_mgr_put_c 2174 .src_mgr_put_ctrl_blk = src_mgr_put_ctrl_blk,
2165 .src_set_state = src_set_state, 2175 .src_set_state = src_set_state,
2166 .src_set_bm = src_set_bm, 2176 .src_set_bm = src_set_bm,
2167 .src_set_rsr = src_set_rsr, 2177 .src_set_rsr = src_set_rsr,
2168 .src_set_sf = src_set_sf, 2178 .src_set_sf = src_set_sf,
2169 .src_set_wr = src_set_wr, 2179 .src_set_wr = src_set_wr,
2170 .src_set_pm = src_set_pm, 2180 .src_set_pm = src_set_pm,
2171 .src_set_rom = src_set_rom, 2181 .src_set_rom = src_set_rom,
2172 .src_set_vo = src_set_vo, 2182 .src_set_vo = src_set_vo,
2173 .src_set_st = src_set_st, 2183 .src_set_st = src_set_st,
2174 .src_set_ie = src_set_ie, 2184 .src_set_ie = src_set_ie,
2175 .src_set_ilsz = src_set_ilsz, 2185 .src_set_ilsz = src_set_ilsz,
2176 .src_set_bp = src_set_bp, 2186 .src_set_bp = src_set_bp,
2177 .src_set_cisz = src_set_cisz, 2187 .src_set_cisz = src_set_cisz,
2178 .src_set_ca = src_set_ca, 2188 .src_set_ca = src_set_ca,
2179 .src_set_sa = src_set_sa, 2189 .src_set_sa = src_set_sa,
2180 .src_set_la = src_set_la, 2190 .src_set_la = src_set_la,
2181 .src_set_pitch = src_set_pitch, 2191 .src_set_pitch = src_set_pitch,
2182 .src_set_dirty = src_set_dirty, 2192 .src_set_dirty = src_set_dirty,
2183 .src_set_clear_zbufs = src_set_clear_ 2193 .src_set_clear_zbufs = src_set_clear_zbufs,
2184 .src_set_dirty_all = src_set_dirty_al 2194 .src_set_dirty_all = src_set_dirty_all,
2185 .src_commit_write = src_commit_write, 2195 .src_commit_write = src_commit_write,
2186 .src_get_ca = src_get_ca, 2196 .src_get_ca = src_get_ca,
2187 .src_get_dirty = src_get_dirty, 2197 .src_get_dirty = src_get_dirty,
2188 .src_dirty_conj_mask = src_dirty_conj 2198 .src_dirty_conj_mask = src_dirty_conj_mask,
2189 .src_mgr_enbs_src = src_mgr_enbs_src, 2199 .src_mgr_enbs_src = src_mgr_enbs_src,
2190 .src_mgr_enb_src = src_mgr_enb_src, 2200 .src_mgr_enb_src = src_mgr_enb_src,
2191 .src_mgr_dsb_src = src_mgr_dsb_src, 2201 .src_mgr_dsb_src = src_mgr_dsb_src,
2192 .src_mgr_commit_write = src_mgr_commi 2202 .src_mgr_commit_write = src_mgr_commit_write,
2193 2203
2194 .srcimp_mgr_get_ctrl_blk = srcimp_mgr 2204 .srcimp_mgr_get_ctrl_blk = srcimp_mgr_get_ctrl_blk,
2195 .srcimp_mgr_put_ctrl_blk = srcimp_mgr 2205 .srcimp_mgr_put_ctrl_blk = srcimp_mgr_put_ctrl_blk,
2196 .srcimp_mgr_set_imaparc = srcimp_mgr_ 2206 .srcimp_mgr_set_imaparc = srcimp_mgr_set_imaparc,
2197 .srcimp_mgr_set_imapuser = srcimp_mgr 2207 .srcimp_mgr_set_imapuser = srcimp_mgr_set_imapuser,
2198 .srcimp_mgr_set_imapnxt = srcimp_mgr_ 2208 .srcimp_mgr_set_imapnxt = srcimp_mgr_set_imapnxt,
2199 .srcimp_mgr_set_imapaddr = srcimp_mgr 2209 .srcimp_mgr_set_imapaddr = srcimp_mgr_set_imapaddr,
2200 .srcimp_mgr_commit_write = srcimp_mgr 2210 .srcimp_mgr_commit_write = srcimp_mgr_commit_write,
2201 2211
2202 .amixer_rsc_get_ctrl_blk = amixer_rsc 2212 .amixer_rsc_get_ctrl_blk = amixer_rsc_get_ctrl_blk,
2203 .amixer_rsc_put_ctrl_blk = amixer_rsc 2213 .amixer_rsc_put_ctrl_blk = amixer_rsc_put_ctrl_blk,
2204 .amixer_mgr_get_ctrl_blk = amixer_mgr 2214 .amixer_mgr_get_ctrl_blk = amixer_mgr_get_ctrl_blk,
2205 .amixer_mgr_put_ctrl_blk = amixer_mgr 2215 .amixer_mgr_put_ctrl_blk = amixer_mgr_put_ctrl_blk,
2206 .amixer_set_mode = amixer_set_mode, 2216 .amixer_set_mode = amixer_set_mode,
2207 .amixer_set_iv = amixer_set_iv, 2217 .amixer_set_iv = amixer_set_iv,
2208 .amixer_set_x = amixer_set_x, 2218 .amixer_set_x = amixer_set_x,
2209 .amixer_set_y = amixer_set_y, 2219 .amixer_set_y = amixer_set_y,
2210 .amixer_set_sadr = amixer_set_sadr, 2220 .amixer_set_sadr = amixer_set_sadr,
2211 .amixer_set_se = amixer_set_se, 2221 .amixer_set_se = amixer_set_se,
2212 .amixer_set_dirty = amixer_set_dirty, 2222 .amixer_set_dirty = amixer_set_dirty,
2213 .amixer_set_dirty_all = amixer_set_di 2223 .amixer_set_dirty_all = amixer_set_dirty_all,
2214 .amixer_commit_write = amixer_commit_ 2224 .amixer_commit_write = amixer_commit_write,
2215 .amixer_get_y = amixer_get_y, 2225 .amixer_get_y = amixer_get_y,
2216 .amixer_get_dirty = amixer_get_dirty, 2226 .amixer_get_dirty = amixer_get_dirty,
2217 2227
2218 .dai_get_ctrl_blk = dai_get_ctrl_blk, 2228 .dai_get_ctrl_blk = dai_get_ctrl_blk,
2219 .dai_put_ctrl_blk = dai_put_ctrl_blk, 2229 .dai_put_ctrl_blk = dai_put_ctrl_blk,
2220 .dai_srt_set_srco = dai_srt_set_srcr, 2230 .dai_srt_set_srco = dai_srt_set_srcr,
2221 .dai_srt_set_srcm = dai_srt_set_srcl, 2231 .dai_srt_set_srcm = dai_srt_set_srcl,
2222 .dai_srt_set_rsr = dai_srt_set_rsr, 2232 .dai_srt_set_rsr = dai_srt_set_rsr,
2223 .dai_srt_set_drat = dai_srt_set_drat, 2233 .dai_srt_set_drat = dai_srt_set_drat,
2224 .dai_srt_set_ec = dai_srt_set_ec, 2234 .dai_srt_set_ec = dai_srt_set_ec,
2225 .dai_srt_set_et = dai_srt_set_et, 2235 .dai_srt_set_et = dai_srt_set_et,
2226 .dai_commit_write = dai_commit_write, 2236 .dai_commit_write = dai_commit_write,
2227 2237
2228 .dao_get_ctrl_blk = dao_get_ctrl_blk, 2238 .dao_get_ctrl_blk = dao_get_ctrl_blk,
2229 .dao_put_ctrl_blk = dao_put_ctrl_blk, 2239 .dao_put_ctrl_blk = dao_put_ctrl_blk,
2230 .dao_set_spos = dao_set_spos, 2240 .dao_set_spos = dao_set_spos,
2231 .dao_commit_write = dao_commit_write, 2241 .dao_commit_write = dao_commit_write,
2232 .dao_get_spos = dao_get_spos, 2242 .dao_get_spos = dao_get_spos,
2233 2243
2234 .daio_mgr_get_ctrl_blk = daio_mgr_get 2244 .daio_mgr_get_ctrl_blk = daio_mgr_get_ctrl_blk,
2235 .daio_mgr_put_ctrl_blk = daio_mgr_put 2245 .daio_mgr_put_ctrl_blk = daio_mgr_put_ctrl_blk,
2236 .daio_mgr_enb_dai = daio_mgr_enb_dai, 2246 .daio_mgr_enb_dai = daio_mgr_enb_dai,
2237 .daio_mgr_dsb_dai = daio_mgr_dsb_dai, 2247 .daio_mgr_dsb_dai = daio_mgr_dsb_dai,
2238 .daio_mgr_enb_dao = daio_mgr_enb_dao, 2248 .daio_mgr_enb_dao = daio_mgr_enb_dao,
2239 .daio_mgr_dsb_dao = daio_mgr_dsb_dao, 2249 .daio_mgr_dsb_dao = daio_mgr_dsb_dao,
2240 .daio_mgr_dao_init = daio_mgr_dao_ini 2250 .daio_mgr_dao_init = daio_mgr_dao_init,
2241 .daio_mgr_set_imaparc = daio_mgr_set_ 2251 .daio_mgr_set_imaparc = daio_mgr_set_imaparc,
2242 .daio_mgr_set_imapnxt = daio_mgr_set_ 2252 .daio_mgr_set_imapnxt = daio_mgr_set_imapnxt,
2243 .daio_mgr_set_imapaddr = daio_mgr_set 2253 .daio_mgr_set_imapaddr = daio_mgr_set_imapaddr,
2244 .daio_mgr_commit_write = daio_mgr_com 2254 .daio_mgr_commit_write = daio_mgr_commit_write,
2245 2255
2246 .set_timer_irq = set_timer_irq, 2256 .set_timer_irq = set_timer_irq,
2247 .set_timer_tick = set_timer_tick, 2257 .set_timer_tick = set_timer_tick,
2248 .get_wc = get_wc, 2258 .get_wc = get_wc,
2249 }; 2259 };
2250 2260
2251 int create_20k1_hw_obj(struct hw **rhw) 2261 int create_20k1_hw_obj(struct hw **rhw)
2252 { 2262 {
2253 struct hw20k1 *hw20k1; 2263 struct hw20k1 *hw20k1;
2254 2264
2255 *rhw = NULL; 2265 *rhw = NULL;
2256 hw20k1 = kzalloc(sizeof(*hw20k1), GFP 2266 hw20k1 = kzalloc(sizeof(*hw20k1), GFP_KERNEL);
2257 if (!hw20k1) 2267 if (!hw20k1)
2258 return -ENOMEM; 2268 return -ENOMEM;
2259 2269
2260 spin_lock_init(&hw20k1->reg_20k1_lock 2270 spin_lock_init(&hw20k1->reg_20k1_lock);
2261 spin_lock_init(&hw20k1->reg_pci_lock) 2271 spin_lock_init(&hw20k1->reg_pci_lock);
2262 2272
2263 hw20k1->hw = ct20k1_preset; 2273 hw20k1->hw = ct20k1_preset;
2264 2274
2265 *rhw = &hw20k1->hw; 2275 *rhw = &hw20k1->hw;
2266 2276
2267 return 0; 2277 return 0;
2268 } 2278 }
2269 2279
2270 int destroy_20k1_hw_obj(struct hw *hw) 2280 int destroy_20k1_hw_obj(struct hw *hw)
2271 { 2281 {
2272 if (hw->io_base) 2282 if (hw->io_base)
2273 hw_card_shutdown(hw); 2283 hw_card_shutdown(hw);
2274 2284
2275 kfree(container_of(hw, struct hw20k1, 2285 kfree(container_of(hw, struct hw20k1, hw));
2276 return 0; 2286 return 0;
2277 } 2287 }
2278 2288
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