1 /* SPDX-License-Identifier: GPL-2.0-or-later * <<
2 /* 1 /*
3 * Copyright (c) by James Courtier-Dutton <Ja 2 * Copyright (c) by James Courtier-Dutton <James@superbug.demon.co.uk>
4 * Driver p16v chips 3 * Driver p16v chips
>> 4 * Version: 0.21
>> 5 *
>> 6 * FEATURES currently supported:
>> 7 * Output fixed at S32_LE, 2 channel to hw:0,0
>> 8 * Rates: 44.1, 48, 96, 192.
>> 9 *
>> 10 * Changelog:
>> 11 * 0.8
>> 12 * Use separate card based buffer for periods table.
>> 13 * 0.9
>> 14 * Use 2 channel output streams instead of 8 channel.
>> 15 * (8 channel output streams might be good for ASIO type output)
>> 16 * Corrected speaker output, so Front -> Front etc.
>> 17 * 0.10
>> 18 * Fixed missed interrupts.
>> 19 * 0.11
>> 20 * Add Sound card model number and names.
>> 21 * Add Analog volume controls.
>> 22 * 0.12
>> 23 * Corrected playback interrupts. Now interrupt per period, instead of half period.
>> 24 * 0.13
>> 25 * Use single trigger for multichannel.
>> 26 * 0.14
>> 27 * Mic capture now works at fixed: S32_LE, 96000Hz, Stereo.
>> 28 * 0.15
>> 29 * Force buffer_size / period_size == INTEGER.
>> 30 * 0.16
>> 31 * Update p16v.c to work with changed alsa api.
>> 32 * 0.17
>> 33 * Update p16v.c to work with changed alsa api. Removed boot_devs.
>> 34 * 0.18
>> 35 * Merging with snd-emu10k1 driver.
>> 36 * 0.19
>> 37 * One stereo channel at 24bit now works.
>> 38 * 0.20
>> 39 * Added better register defines.
>> 40 * 0.21
>> 41 * Split from p16v.c
>> 42 *
>> 43 *
>> 44 * BUGS:
>> 45 * Some stability problems when unloading the snd-p16v kernel module.
>> 46 * --
>> 47 *
>> 48 * TODO:
>> 49 * SPDIF out.
>> 50 * Find out how to change capture sample rates. E.g. To record SPDIF at 48000Hz.
>> 51 * Currently capture fixed at 48000Hz.
>> 52 *
>> 53 * --
>> 54 * GENERAL INFO:
>> 55 * Model: SB0240
>> 56 * P16V Chip: CA0151-DBS
>> 57 * Audigy 2 Chip: CA0102-IAT
>> 58 * AC97 Codec: STAC 9721
>> 59 * ADC: Philips 1361T (Stereo 24bit)
>> 60 * DAC: CS4382-K (8-channel, 24bit, 192Khz)
5 * 61 *
6 * This code was initially based on code from 62 * This code was initially based on code from ALSA's emu10k1x.c which is:
7 * Copyright (c) by Francisco Moraes <fmoraes 63 * Copyright (c) by Francisco Moraes <fmoraes@nc.rr.com>
>> 64 *
>> 65 * This program is free software; you can redistribute it and/or modify
>> 66 * it under the terms of the GNU General Public License as published by
>> 67 * the Free Software Foundation; either version 2 of the License, or
>> 68 * (at your option) any later version.
>> 69 *
>> 70 * This program is distributed in the hope that it will be useful,
>> 71 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 72 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 73 * GNU General Public License for more details.
>> 74 *
>> 75 * You should have received a copy of the GNU General Public License
>> 76 * along with this program; if not, write to the Free Software
>> 77 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
>> 78 *
8 */ 79 */
9 80
10 /********************************************* 81 /********************************************************************************************************/
11 /* Audigy2 P16V pointer-offset register set, a !! 82 /* Audigy2 P16V pointer-offset register set, accessed through the PTR2 and DATA2 registers */
12 /********************************************* 83 /********************************************************************************************************/
13 84
14 /* The sample rate of the SPDIF outputs is set 85 /* The sample rate of the SPDIF outputs is set by modifying a register in the EMU10K2 PTR register A_SPDIF_SAMPLERATE.
15 * The sample rate is also controlled by the s 86 * The sample rate is also controlled by the same registers that control the rate of the EMU10K2 sample rate converters.
16 */ 87 */
17 88
18 /* Initially all registers from 0x00 to 0x3f h 89 /* Initially all registers from 0x00 to 0x3f have zero contents. */
19 #define PLAYBACK_LIST_ADDR 0x00 90 #define PLAYBACK_LIST_ADDR 0x00 /* Base DMA address of a list of pointers to each period/size */
20 91 /* One list entry: 4 bytes for DMA address,
21 92 * 4 bytes for period_size << 16.
22 93 * One list entry is 8 bytes long.
23 94 * One list entry for each period in the buffer.
24 95 */
25 #define PLAYBACK_LIST_SIZE 0x01 96 #define PLAYBACK_LIST_SIZE 0x01 /* Size of list in bytes << 16. E.g. 8 periods -> 0x00380000 */
26 #define PLAYBACK_LIST_PTR 0x02 97 #define PLAYBACK_LIST_PTR 0x02 /* Pointer to the current period being played */
27 #define PLAYBACK_UNKNOWN3 0x03 98 #define PLAYBACK_UNKNOWN3 0x03 /* Not used */
28 #define PLAYBACK_DMA_ADDR 0x04 99 #define PLAYBACK_DMA_ADDR 0x04 /* Playback DMA address */
29 #define PLAYBACK_PERIOD_SIZE 0x05 100 #define PLAYBACK_PERIOD_SIZE 0x05 /* Playback period size. win2000 uses 0x04000000 */
30 #define PLAYBACK_POINTER 0x06 101 #define PLAYBACK_POINTER 0x06 /* Playback period pointer. Used with PLAYBACK_LIST_PTR to determine buffer position currently in DAC */
31 #define PLAYBACK_FIFO_END_ADDRESS 0x07 102 #define PLAYBACK_FIFO_END_ADDRESS 0x07 /* Playback FIFO end address */
32 #define PLAYBACK_FIFO_POINTER 0x08 103 #define PLAYBACK_FIFO_POINTER 0x08 /* Playback FIFO pointer and number of valid sound samples in cache */
33 #define PLAYBACK_UNKNOWN9 0x09 104 #define PLAYBACK_UNKNOWN9 0x09 /* Not used */
34 #define CAPTURE_DMA_ADDR 0x10 105 #define CAPTURE_DMA_ADDR 0x10 /* Capture DMA address */
35 #define CAPTURE_BUFFER_SIZE 0x11 106 #define CAPTURE_BUFFER_SIZE 0x11 /* Capture buffer size */
36 #define CAPTURE_POINTER 0x12 107 #define CAPTURE_POINTER 0x12 /* Capture buffer pointer. Sample currently in ADC */
37 #define CAPTURE_FIFO_POINTER 0x13 108 #define CAPTURE_FIFO_POINTER 0x13 /* Capture FIFO pointer and number of valid sound samples in cache */
38 #define CAPTURE_P16V_VOLUME1 0x14 109 #define CAPTURE_P16V_VOLUME1 0x14 /* Low: Capture volume 0xXXXX3030 */
39 #define CAPTURE_P16V_VOLUME2 0x15 110 #define CAPTURE_P16V_VOLUME2 0x15 /* High:Has no effect on capture volume */
40 #define CAPTURE_P16V_SOURCE 0x16 111 #define CAPTURE_P16V_SOURCE 0x16 /* P16V source select. Set to 0x0700E4E5 for AC97 CAPTURE */
41 112 /* [0:1] Capture input 0 channel select. 0 = Capture output 0.
42 113 * 1 = Capture output 1.
43 114 * 2 = Capture output 2.
44 115 * 3 = Capture output 3.
45 116 * [3:2] Capture input 1 channel select. 0 = Capture output 0.
46 117 * 1 = Capture output 1.
47 118 * 2 = Capture output 2.
48 119 * 3 = Capture output 3.
49 120 * [5:4] Capture input 2 channel select. 0 = Capture output 0.
50 121 * 1 = Capture output 1.
51 122 * 2 = Capture output 2.
52 123 * 3 = Capture output 3.
53 124 * [7:6] Capture input 3 channel select. 0 = Capture output 0.
54 125 * 1 = Capture output 1.
55 126 * 2 = Capture output 2.
56 127 * 3 = Capture output 3.
57 128 * [9:8] Playback input 0 channel select. 0 = Play output 0.
58 129 * 1 = Play output 1.
59 130 * 2 = Play output 2.
60 131 * 3 = Play output 3.
61 132 * [11:10] Playback input 1 channel select. 0 = Play output 0.
62 133 * 1 = Play output 1.
63 134 * 2 = Play output 2.
64 135 * 3 = Play output 3.
65 136 * [13:12] Playback input 2 channel select. 0 = Play output 0.
66 137 * 1 = Play output 1.
67 138 * 2 = Play output 2.
68 139 * 3 = Play output 3.
69 140 * [15:14] Playback input 3 channel select. 0 = Play output 0.
70 141 * 1 = Play output 1.
71 142 * 2 = Play output 2.
72 143 * 3 = Play output 3.
73 144 * [19:16] Playback mixer output enable. 1 bit per channel.
74 145 * [23:20] Capture mixer output enable. 1 bit per channel.
75 146 * [26:24] FX engine channel capture 0 = 0x60-0x67.
76 147 * 1 = 0x68-0x6f.
77 148 * 2 = 0x70-0x77.
78 149 * 3 = 0x78-0x7f.
79 150 * 4 = 0x80-0x87.
80 151 * 5 = 0x88-0x8f.
81 152 * 6 = 0x90-0x97.
82 153 * 7 = 0x98-0x9f.
83 154 * [31:27] Not used.
84 155 */
85 156
86 157 /* 0x1 = capture on.
87 158 * 0x100 = capture off.
88 159 * 0x200 = capture off.
89 160 * 0x1000 = capture off.
90 161 */
91 #define CAPTURE_RATE_STATUS 0x17 162 #define CAPTURE_RATE_STATUS 0x17 /* Capture sample rate. Read only */
92 163 /* [15:0] Not used.
93 164 * [18:16] Channel 0 Detected sample rate. 0 - 44.1khz
94 165 * 1 - 48 khz
95 166 * 2 - 96 khz
96 167 * 3 - 192 khz
97 168 * 7 - undefined rate.
98 169 * [19] Channel 0. 1 - Valid, 0 - Not Valid.
99 170 * [22:20] Channel 1 Detected sample rate.
100 171 * [23] Channel 1. 1 - Valid, 0 - Not Valid.
101 172 * [26:24] Channel 2 Detected sample rate.
102 173 * [27] Channel 2. 1 - Valid, 0 - Not Valid.
103 174 * [30:28] Channel 3 Detected sample rate.
104 175 * [31] Channel 3. 1 - Valid, 0 - Not Valid.
105 176 */
106 /* 0x18 - 0x1f unused */ 177 /* 0x18 - 0x1f unused */
107 #define PLAYBACK_LAST_SAMPLE 0x20 178 #define PLAYBACK_LAST_SAMPLE 0x20 /* The sample currently being played. Read only */
108 /* 0x21 - 0x3f unused */ 179 /* 0x21 - 0x3f unused */
109 #define BASIC_INTERRUPT 0x40 180 #define BASIC_INTERRUPT 0x40 /* Used by both playback and capture interrupt handler */
110 181 /* Playback (0x1<<channel_id) Don't touch high 16bits. */
111 182 /* Capture (0x100<<channel_id). not tested */
112 183 /* Start Playback [3:0] (one bit per channel)
113 184 * Start Capture [11:8] (one bit per channel)
114 185 * Record source select for channel 0 [18:16]
115 186 * Record source select for channel 1 [22:20]
116 187 * Record source select for channel 2 [26:24]
117 188 * Record source select for channel 3 [30:28]
118 189 * 0 - SPDIF channel.
119 190 * 1 - I2S channel.
120 191 * 2 - SRC48 channel.
121 192 * 3 - SRCMulti_SPDIF channel.
122 193 * 4 - SRCMulti_I2S channel.
123 194 * 5 - SPDIF channel.
124 195 * 6 - fxengine capture.
125 196 * 7 - AC97 capture.
126 197 */
127 198 /* Default 41110000.
128 199 * Writing 0xffffffff hangs the PC.
129 200 * Writing 0xffff0000 -> 77770000 so it must be some sort of route.
130 201 * bit 0x1 starts DMA playback on channel_id 0
131 202 */
132 /* 0x41,42 take values from 0 - 0xffffffff, bu 203 /* 0x41,42 take values from 0 - 0xffffffff, but have no effect on playback */
133 /* 0x43,0x48 do not remember settings */ 204 /* 0x43,0x48 do not remember settings */
134 /* 0x41-45 unused */ 205 /* 0x41-45 unused */
135 #define WATERMARK 0x46 206 #define WATERMARK 0x46 /* Test bit to indicate cache level usage */
136 207 /* Values it can have while playing on channel 0.
137 208 * 0000f000, 0000f004, 0000f008, 0000f00c.
138 209 * Readonly.
139 210 */
140 /* 0x47-0x4f unused */ 211 /* 0x47-0x4f unused */
141 /* 0x50-0x5f Capture cache data */ 212 /* 0x50-0x5f Capture cache data */
142 #define SRCSel 0x60 213 #define SRCSel 0x60 /* SRCSel. Default 0x4. Bypass P16V 0x14 */
143 214 /* [0] 0 = 10K2 audio, 1 = SRC48 mixer output.
144 215 * [2] 0 = 10K2 audio, 1 = SRCMulti SPDIF mixer output.
145 216 * [4] 0 = 10K2 audio, 1 = SRCMulti I2S mixer output.
146 217 */
147 218 /* SRC48 converts samples rates 44.1, 48, 96, 192 to 48 khz. */
148 219 /* SRCMulti converts 48khz samples rates to 44.1, 48, 96, 192 to 48. */
149 220 /* SRC48 and SRCMULTI sample rate select and output select. */
150 221 /* 0xffffffff -> 0xC0000015
151 222 * 0xXXXXXXX4 = Enable Front Left/Right
152 223 * Enable PCMs
153 224 */
154 225
155 /* 0x61 -> 0x6c are Volume controls */ 226 /* 0x61 -> 0x6c are Volume controls */
156 #define PLAYBACK_VOLUME_MIXER1 0x61 227 #define PLAYBACK_VOLUME_MIXER1 0x61 /* SRC48 Low to mixer input volume control. */
157 #define PLAYBACK_VOLUME_MIXER2 0x62 228 #define PLAYBACK_VOLUME_MIXER2 0x62 /* SRC48 High to mixer input volume control. */
158 #define PLAYBACK_VOLUME_MIXER3 0x63 229 #define PLAYBACK_VOLUME_MIXER3 0x63 /* SRCMULTI SPDIF Low to mixer input volume control. */
159 #define PLAYBACK_VOLUME_MIXER4 0x64 230 #define PLAYBACK_VOLUME_MIXER4 0x64 /* SRCMULTI SPDIF High to mixer input volume control. */
160 #define PLAYBACK_VOLUME_MIXER5 0x65 231 #define PLAYBACK_VOLUME_MIXER5 0x65 /* SRCMULTI I2S Low to mixer input volume control. */
161 #define PLAYBACK_VOLUME_MIXER6 0x66 232 #define PLAYBACK_VOLUME_MIXER6 0x66 /* SRCMULTI I2S High to mixer input volume control. */
162 #define PLAYBACK_VOLUME_MIXER7 0x67 233 #define PLAYBACK_VOLUME_MIXER7 0x67 /* P16V Low to SRCMULTI SPDIF mixer input volume control. */
163 #define PLAYBACK_VOLUME_MIXER8 0x68 234 #define PLAYBACK_VOLUME_MIXER8 0x68 /* P16V High to SRCMULTI SPDIF mixer input volume control. */
164 #define PLAYBACK_VOLUME_MIXER9 0x69 235 #define PLAYBACK_VOLUME_MIXER9 0x69 /* P16V Low to SRCMULTI I2S mixer input volume control. */
165 236 /* 0xXXXX3030 = PCM0 Volume (Front).
166 237 * 0x3030XXXX = PCM1 Volume (Center)
167 238 */
168 #define PLAYBACK_VOLUME_MIXER10 0x6a 239 #define PLAYBACK_VOLUME_MIXER10 0x6a /* P16V High to SRCMULTI I2S mixer input volume control. */
169 240 /* 0x3030XXXX = PCM3 Volume (Rear). */
170 #define PLAYBACK_VOLUME_MIXER11 0x6b 241 #define PLAYBACK_VOLUME_MIXER11 0x6b /* E10K2 Low to SRC48 mixer input volume control. */
171 #define PLAYBACK_VOLUME_MIXER12 0x6c 242 #define PLAYBACK_VOLUME_MIXER12 0x6c /* E10K2 High to SRC48 mixer input volume control. */
172 243
173 #define SRC48_ENABLE 0x6d 244 #define SRC48_ENABLE 0x6d /* SRC48 input audio enable */
174 245 /* SRC48 converts samples rates 44.1, 48, 96, 192 to 48 khz. */
175 246 /* [23:16] The corresponding P16V channel to SRC48 enabled if == 1.
176 247 * [31:24] The corresponding E10K2 channel to SRC48 enabled.
177 248 */
178 #define SRCMULTI_ENABLE 0x6e 249 #define SRCMULTI_ENABLE 0x6e /* SRCMulti input audio enable. Default 0xffffffff */
179 250 /* SRCMulti converts 48khz samples rates to 44.1, 48, 96, 192 to 48. */
180 251 /* [7:0] The corresponding P16V channel to SRCMulti_I2S enabled if == 1.
181 252 * [15:8] The corresponding E10K2 channel to SRCMulti I2S enabled.
182 253 * [23:16] The corresponding P16V channel to SRCMulti SPDIF enabled.
183 254 * [31:24] The corresponding E10K2 channel to SRCMulti SPDIF enabled.
184 255 */
185 256 /* Bypass P16V 0xff00ff00
186 257 * Bitmap. 0 = Off, 1 = On.
187 258 * P16V playback outputs:
188 259 * 0xXXXXXXX1 = PCM0 Left. (Front)
189 260 * 0xXXXXXXX2 = PCM0 Right.
190 261 * 0xXXXXXXX4 = PCM1 Left. (Center/LFE)
191 262 * 0xXXXXXXX8 = PCM1 Right.
192 263 * 0xXXXXXX1X = PCM2 Left. (Unknown)
193 264 * 0xXXXXXX2X = PCM2 Right.
194 265 * 0xXXXXXX4X = PCM3 Left. (Rear)
195 266 * 0xXXXXXX8X = PCM3 Right.
196 267 */
197 #define AUDIO_OUT_ENABLE 0x6f 268 #define AUDIO_OUT_ENABLE 0x6f /* Default: 000100FF */
198 269 /* [3:0] Does something, but not documented. Probably capture enable.
199 270 * [7:4] Playback channels enable. not documented.
200 271 * [16] AC97 output enable if == 1
201 272 * [30] 0 = SRCMulti_I2S input from fxengine 0x68-0x6f.
202 273 * 1 = SRCMulti_I2S input from SRC48 output.
203 274 * [31] 0 = SRCMulti_SPDIF input from fxengine 0x60-0x67.
204 275 * 1 = SRCMulti_SPDIF input from SRC48 output.
205 276 */
206 277 /* 0xffffffff -> C00100FF */
207 278 /* 0 -> Not playback sound, irq still running */
208 279 /* 0xXXXXXX10 = PCM0 Left/Right On. (Front)
209 280 * 0xXXXXXX20 = PCM1 Left/Right On. (Center/LFE)
210 281 * 0xXXXXXX40 = PCM2 Left/Right On. (Unknown)
211 282 * 0xXXXXXX80 = PCM3 Left/Right On. (Rear)
212 283 */
213 #define PLAYBACK_SPDIF_SELECT 0x70 284 #define PLAYBACK_SPDIF_SELECT 0x70 /* Default: 12030F00 */
214 285 /* 0xffffffff -> 3FF30FFF */
215 286 /* 0x00000001 pauses stream/irq fail. */
216 287 /* All other bits do not effect playback */
217 #define PLAYBACK_SPDIF_SRC_SELECT 0x71 288 #define PLAYBACK_SPDIF_SRC_SELECT 0x71 /* Default: 0000E4E4 */
218 289 /* 0xffffffff -> F33FFFFF */
219 290 /* All bits do not effect playback */
220 #define PLAYBACK_SPDIF_USER_DATA0 0x72 291 #define PLAYBACK_SPDIF_USER_DATA0 0x72 /* SPDIF out user data 0 */
221 #define PLAYBACK_SPDIF_USER_DATA1 0x73 292 #define PLAYBACK_SPDIF_USER_DATA1 0x73 /* SPDIF out user data 1 */
222 /* 0x74-0x75 unknown */ 293 /* 0x74-0x75 unknown */
223 #define CAPTURE_SPDIF_CONTROL 0x76 294 #define CAPTURE_SPDIF_CONTROL 0x76 /* SPDIF in control setting */
224 #define CAPTURE_SPDIF_STATUS 0x77 295 #define CAPTURE_SPDIF_STATUS 0x77 /* SPDIF in status */
225 #define CAPURE_SPDIF_USER_DATA0 0x78 296 #define CAPURE_SPDIF_USER_DATA0 0x78 /* SPDIF in user data 0 */
226 #define CAPURE_SPDIF_USER_DATA1 0x79 297 #define CAPURE_SPDIF_USER_DATA1 0x79 /* SPDIF in user data 1 */
227 #define CAPURE_SPDIF_USER_DATA2 0x7a 298 #define CAPURE_SPDIF_USER_DATA2 0x7a /* SPDIF in user data 2 */
228 299
229 300
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