1 /* SPDX-License-Identifier: GPL-2.0-or-later * << 2 #ifndef __SOUND_PHASE_H 1 #ifndef __SOUND_PHASE_H 3 #define __SOUND_PHASE_H 2 #define __SOUND_PHASE_H 4 3 5 /* 4 /* 6 * ALSA driver for ICEnsemble ICE1712 (Envy2 5 * ALSA driver for ICEnsemble ICE1712 (Envy24) 7 * 6 * 8 * Lowlevel functions for Terratec PHASE 22 7 * Lowlevel functions for Terratec PHASE 22 9 * 8 * 10 * Copyright (c) 2005 Misha Zhilin <misha 9 * Copyright (c) 2005 Misha Zhilin <misha@epiphan.com> >> 10 * >> 11 * This program is free software; you can redistribute it and/or modify >> 12 * it under the terms of the GNU General Public License as published by >> 13 * the Free Software Foundation; either version 2 of the License, or >> 14 * (at your option) any later version. >> 15 * >> 16 * This program is distributed in the hope that it will be useful, >> 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of >> 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> 19 * GNU General Public License for more details. >> 20 * >> 21 * You should have received a copy of the GNU General Public License >> 22 * along with this program; if not, write to the Free Software >> 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA >> 24 * 11 */ 25 */ 12 26 13 #define PHASE_DEVICE_DESC "{Terratec,Pha 27 #define PHASE_DEVICE_DESC "{Terratec,Phase 22},"\ 14 "{Terratec,Pha 28 "{Terratec,Phase 28},"\ 15 "{Terrasoniq,T 29 "{Terrasoniq,TS22}," 16 30 17 #define VT1724_SUBDEVICE_PHASE22 0x3b15 31 #define VT1724_SUBDEVICE_PHASE22 0x3b155011 18 #define VT1724_SUBDEVICE_PHASE28 0x3b15 32 #define VT1724_SUBDEVICE_PHASE28 0x3b154911 19 #define VT1724_SUBDEVICE_TS22 0x3b15 33 #define VT1724_SUBDEVICE_TS22 0x3b157b11 20 34 21 /* entry point */ 35 /* entry point */ 22 extern struct snd_ice1712_card_info snd_vt1724 36 extern struct snd_ice1712_card_info snd_vt1724_phase_cards[]; 23 37 24 /* PHASE28 GPIO bits */ 38 /* PHASE28 GPIO bits */ 25 #define PHASE28_SPI_MISO (1 << 21) 39 #define PHASE28_SPI_MISO (1 << 21) 26 #define PHASE28_WM_RESET (1 << 20) 40 #define PHASE28_WM_RESET (1 << 20) 27 #define PHASE28_SPI_CLK (1 << 19) 41 #define PHASE28_SPI_CLK (1 << 19) 28 #define PHASE28_SPI_MOSI (1 << 18) 42 #define PHASE28_SPI_MOSI (1 << 18) 29 #define PHASE28_WM_RW (1 << 17) 43 #define PHASE28_WM_RW (1 << 17) 30 #define PHASE28_AC97_RESET (1 << 16) 44 #define PHASE28_AC97_RESET (1 << 16) 31 #define PHASE28_DIGITAL_SEL1 (1 << 15) 45 #define PHASE28_DIGITAL_SEL1 (1 << 15) 32 #define PHASE28_HP_SEL (1 << 14) 46 #define PHASE28_HP_SEL (1 << 14) 33 #define PHASE28_WM_CS (1 << 12) 47 #define PHASE28_WM_CS (1 << 12) 34 #define PHASE28_AC97_COMMIT (1 << 11) 48 #define PHASE28_AC97_COMMIT (1 << 11) 35 #define PHASE28_AC97_ADDR (1 << 10) 49 #define PHASE28_AC97_ADDR (1 << 10) 36 #define PHASE28_AC97_DATA_LOW (1 << 9) 50 #define PHASE28_AC97_DATA_LOW (1 << 9) 37 #define PHASE28_AC97_DATA_HIGH (1 << 8) 51 #define PHASE28_AC97_DATA_HIGH (1 << 8) 38 #define PHASE28_AC97_DATA_MASK 0xFF 52 #define PHASE28_AC97_DATA_MASK 0xFF 39 #endif /* __SOUND_PHASE */ 53 #endif /* __SOUND_PHASE */ 40 54
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