1 // SPDX-License-Identifier: GPL-2.0-or-later <<
2 /* 1 /*
3 * ALSA driver for ICEnsemble VT1724 (Envy24 2 * ALSA driver for ICEnsemble VT1724 (Envy24HT)
4 * 3 *
5 * Lowlevel functions for Pontis MS300 4 * Lowlevel functions for Pontis MS300
6 * 5 *
7 * Copyright (c) 2004 Takashi Iwai <tiwai 6 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
>> 7 *
>> 8 * This program is free software; you can redistribute it and/or modify
>> 9 * it under the terms of the GNU General Public License as published by
>> 10 * the Free Software Foundation; either version 2 of the License, or
>> 11 * (at your option) any later version.
>> 12 *
>> 13 * This program is distributed in the hope that it will be useful,
>> 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 16 * GNU General Public License for more details.
>> 17 *
>> 18 * You should have received a copy of the GNU General Public License
>> 19 * along with this program; if not, write to the Free Software
>> 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
>> 21 *
8 */ 22 */
9 23
10 #include <linux/delay.h> 24 #include <linux/delay.h>
11 #include <linux/interrupt.h> 25 #include <linux/interrupt.h>
12 #include <linux/init.h> 26 #include <linux/init.h>
13 #include <linux/slab.h> 27 #include <linux/slab.h>
14 #include <linux/mutex.h> 28 #include <linux/mutex.h>
15 29
16 #include <sound/core.h> 30 #include <sound/core.h>
17 #include <sound/info.h> 31 #include <sound/info.h>
18 #include <sound/tlv.h> 32 #include <sound/tlv.h>
19 33
20 #include "ice1712.h" 34 #include "ice1712.h"
21 #include "envy24ht.h" 35 #include "envy24ht.h"
22 #include "pontis.h" 36 #include "pontis.h"
23 37
24 /* I2C addresses */ 38 /* I2C addresses */
25 #define WM_DEV 0x34 39 #define WM_DEV 0x34
26 #define CS_DEV 0x20 40 #define CS_DEV 0x20
27 41
28 /* WM8776 registers */ 42 /* WM8776 registers */
29 #define WM_HP_ATTEN_L 0x00 /* hea 43 #define WM_HP_ATTEN_L 0x00 /* headphone left attenuation */
30 #define WM_HP_ATTEN_R 0x01 /* hea 44 #define WM_HP_ATTEN_R 0x01 /* headphone left attenuation */
31 #define WM_HP_MASTER 0x02 /* hea 45 #define WM_HP_MASTER 0x02 /* headphone master (both channels) */
32 /* ove 46 /* override LLR */
33 #define WM_DAC_ATTEN_L 0x03 /* dig 47 #define WM_DAC_ATTEN_L 0x03 /* digital left attenuation */
34 #define WM_DAC_ATTEN_R 0x04 48 #define WM_DAC_ATTEN_R 0x04
35 #define WM_DAC_MASTER 0x05 49 #define WM_DAC_MASTER 0x05
36 #define WM_PHASE_SWAP 0x06 /* DAC 50 #define WM_PHASE_SWAP 0x06 /* DAC phase swap */
37 #define WM_DAC_CTRL1 0x07 51 #define WM_DAC_CTRL1 0x07
38 #define WM_DAC_MUTE 0x08 52 #define WM_DAC_MUTE 0x08
39 #define WM_DAC_CTRL2 0x09 53 #define WM_DAC_CTRL2 0x09
40 #define WM_DAC_INT 0x0a 54 #define WM_DAC_INT 0x0a
41 #define WM_ADC_INT 0x0b 55 #define WM_ADC_INT 0x0b
42 #define WM_MASTER_CTRL 0x0c 56 #define WM_MASTER_CTRL 0x0c
43 #define WM_POWERDOWN 0x0d 57 #define WM_POWERDOWN 0x0d
44 #define WM_ADC_ATTEN_L 0x0e 58 #define WM_ADC_ATTEN_L 0x0e
45 #define WM_ADC_ATTEN_R 0x0f 59 #define WM_ADC_ATTEN_R 0x0f
46 #define WM_ALC_CTRL1 0x10 60 #define WM_ALC_CTRL1 0x10
47 #define WM_ALC_CTRL2 0x11 61 #define WM_ALC_CTRL2 0x11
48 #define WM_ALC_CTRL3 0x12 62 #define WM_ALC_CTRL3 0x12
49 #define WM_NOISE_GATE 0x13 63 #define WM_NOISE_GATE 0x13
50 #define WM_LIMITER 0x14 64 #define WM_LIMITER 0x14
51 #define WM_ADC_MUX 0x15 65 #define WM_ADC_MUX 0x15
52 #define WM_OUT_MUX 0x16 66 #define WM_OUT_MUX 0x16
53 #define WM_RESET 0x17 67 #define WM_RESET 0x17
54 68
55 /* 69 /*
56 * GPIO 70 * GPIO
57 */ 71 */
58 #define PONTIS_CS_CS (1<<4) /* CS 72 #define PONTIS_CS_CS (1<<4) /* CS */
59 #define PONTIS_CS_CLK (1<<5) /* CLK 73 #define PONTIS_CS_CLK (1<<5) /* CLK */
60 #define PONTIS_CS_RDATA (1<<6) /* CS8 74 #define PONTIS_CS_RDATA (1<<6) /* CS8416 -> VT1720 */
61 #define PONTIS_CS_WDATA (1<<7) /* VT1 75 #define PONTIS_CS_WDATA (1<<7) /* VT1720 -> CS8416 */
62 76
63 77
64 /* 78 /*
65 * get the current register value of WM codec 79 * get the current register value of WM codec
66 */ 80 */
67 static unsigned short wm_get(struct snd_ice171 81 static unsigned short wm_get(struct snd_ice1712 *ice, int reg)
68 { 82 {
69 reg <<= 1; 83 reg <<= 1;
70 return ((unsigned short)ice->akm[0].im 84 return ((unsigned short)ice->akm[0].images[reg] << 8) |
71 ice->akm[0].images[reg + 1]; 85 ice->akm[0].images[reg + 1];
72 } 86 }
73 87
74 /* 88 /*
75 * set the register value of WM codec and reme 89 * set the register value of WM codec and remember it
76 */ 90 */
77 static void wm_put_nocache(struct snd_ice1712 91 static void wm_put_nocache(struct snd_ice1712 *ice, int reg, unsigned short val)
78 { 92 {
79 unsigned short cval; 93 unsigned short cval;
80 cval = (reg << 9) | val; 94 cval = (reg << 9) | val;
81 snd_vt1724_write_i2c(ice, WM_DEV, cval 95 snd_vt1724_write_i2c(ice, WM_DEV, cval >> 8, cval & 0xff);
82 } 96 }
83 97
84 static void wm_put(struct snd_ice1712 *ice, in 98 static void wm_put(struct snd_ice1712 *ice, int reg, unsigned short val)
85 { 99 {
86 wm_put_nocache(ice, reg, val); 100 wm_put_nocache(ice, reg, val);
87 reg <<= 1; 101 reg <<= 1;
88 ice->akm[0].images[reg] = val >> 8; 102 ice->akm[0].images[reg] = val >> 8;
89 ice->akm[0].images[reg + 1] = val; 103 ice->akm[0].images[reg + 1] = val;
90 } 104 }
91 105
92 /* 106 /*
93 * DAC volume attenuation mixer control (-64dB 107 * DAC volume attenuation mixer control (-64dB to 0dB)
94 */ 108 */
95 109
96 #define DAC_0dB 0xff 110 #define DAC_0dB 0xff
97 #define DAC_RES 128 111 #define DAC_RES 128
98 #define DAC_MIN (DAC_0dB - DAC_RES) 112 #define DAC_MIN (DAC_0dB - DAC_RES)
99 113
100 static int wm_dac_vol_info(struct snd_kcontrol 114 static int wm_dac_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
101 { 115 {
102 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTE 116 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
103 uinfo->count = 2; 117 uinfo->count = 2;
104 uinfo->value.integer.min = 0; /* mut 118 uinfo->value.integer.min = 0; /* mute */
105 uinfo->value.integer.max = DAC_RES; 119 uinfo->value.integer.max = DAC_RES; /* 0dB, 0.5dB step */
106 return 0; 120 return 0;
107 } 121 }
108 122
109 static int wm_dac_vol_get(struct snd_kcontrol 123 static int wm_dac_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
110 { 124 {
111 struct snd_ice1712 *ice = snd_kcontrol 125 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
112 unsigned short val; 126 unsigned short val;
113 int i; 127 int i;
114 128
115 mutex_lock(&ice->gpio_mutex); 129 mutex_lock(&ice->gpio_mutex);
116 for (i = 0; i < 2; i++) { 130 for (i = 0; i < 2; i++) {
117 val = wm_get(ice, WM_DAC_ATTEN 131 val = wm_get(ice, WM_DAC_ATTEN_L + i) & 0xff;
118 val = val > DAC_MIN ? (val - D 132 val = val > DAC_MIN ? (val - DAC_MIN) : 0;
119 ucontrol->value.integer.value[ 133 ucontrol->value.integer.value[i] = val;
120 } 134 }
121 mutex_unlock(&ice->gpio_mutex); 135 mutex_unlock(&ice->gpio_mutex);
122 return 0; 136 return 0;
123 } 137 }
124 138
125 static int wm_dac_vol_put(struct snd_kcontrol 139 static int wm_dac_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
126 { 140 {
127 struct snd_ice1712 *ice = snd_kcontrol 141 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
128 unsigned short oval, nval; 142 unsigned short oval, nval;
129 int i, idx, change = 0; 143 int i, idx, change = 0;
130 144
131 mutex_lock(&ice->gpio_mutex); 145 mutex_lock(&ice->gpio_mutex);
132 for (i = 0; i < 2; i++) { 146 for (i = 0; i < 2; i++) {
133 nval = ucontrol->value.integer 147 nval = ucontrol->value.integer.value[i];
134 nval = (nval ? (nval + DAC_MIN 148 nval = (nval ? (nval + DAC_MIN) : 0) & 0xff;
135 idx = WM_DAC_ATTEN_L + i; 149 idx = WM_DAC_ATTEN_L + i;
136 oval = wm_get(ice, idx) & 0xff 150 oval = wm_get(ice, idx) & 0xff;
137 if (oval != nval) { 151 if (oval != nval) {
138 wm_put(ice, idx, nval) 152 wm_put(ice, idx, nval);
139 wm_put_nocache(ice, id 153 wm_put_nocache(ice, idx, nval | 0x100);
140 change = 1; 154 change = 1;
141 } 155 }
142 } 156 }
143 mutex_unlock(&ice->gpio_mutex); 157 mutex_unlock(&ice->gpio_mutex);
144 return change; 158 return change;
145 } 159 }
146 160
147 /* 161 /*
148 * ADC gain mixer control (-64dB to 0dB) 162 * ADC gain mixer control (-64dB to 0dB)
149 */ 163 */
150 164
151 #define ADC_0dB 0xcf 165 #define ADC_0dB 0xcf
152 #define ADC_RES 128 166 #define ADC_RES 128
153 #define ADC_MIN (ADC_0dB - ADC_RES) 167 #define ADC_MIN (ADC_0dB - ADC_RES)
154 168
155 static int wm_adc_vol_info(struct snd_kcontrol 169 static int wm_adc_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
156 { 170 {
157 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTE 171 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
158 uinfo->count = 2; 172 uinfo->count = 2;
159 uinfo->value.integer.min = 0; /* mut 173 uinfo->value.integer.min = 0; /* mute (-64dB) */
160 uinfo->value.integer.max = ADC_RES; 174 uinfo->value.integer.max = ADC_RES; /* 0dB, 0.5dB step */
161 return 0; 175 return 0;
162 } 176 }
163 177
164 static int wm_adc_vol_get(struct snd_kcontrol 178 static int wm_adc_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
165 { 179 {
166 struct snd_ice1712 *ice = snd_kcontrol 180 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
167 unsigned short val; 181 unsigned short val;
168 int i; 182 int i;
169 183
170 mutex_lock(&ice->gpio_mutex); 184 mutex_lock(&ice->gpio_mutex);
171 for (i = 0; i < 2; i++) { 185 for (i = 0; i < 2; i++) {
172 val = wm_get(ice, WM_ADC_ATTEN 186 val = wm_get(ice, WM_ADC_ATTEN_L + i) & 0xff;
173 val = val > ADC_MIN ? (val - A 187 val = val > ADC_MIN ? (val - ADC_MIN) : 0;
174 ucontrol->value.integer.value[ 188 ucontrol->value.integer.value[i] = val;
175 } 189 }
176 mutex_unlock(&ice->gpio_mutex); 190 mutex_unlock(&ice->gpio_mutex);
177 return 0; 191 return 0;
178 } 192 }
179 193
180 static int wm_adc_vol_put(struct snd_kcontrol 194 static int wm_adc_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
181 { 195 {
182 struct snd_ice1712 *ice = snd_kcontrol 196 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
183 unsigned short ovol, nvol; 197 unsigned short ovol, nvol;
184 int i, idx, change = 0; 198 int i, idx, change = 0;
185 199
186 mutex_lock(&ice->gpio_mutex); 200 mutex_lock(&ice->gpio_mutex);
187 for (i = 0; i < 2; i++) { 201 for (i = 0; i < 2; i++) {
188 nvol = ucontrol->value.integer 202 nvol = ucontrol->value.integer.value[i];
189 nvol = nvol ? (nvol + ADC_MIN) 203 nvol = nvol ? (nvol + ADC_MIN) : 0;
190 idx = WM_ADC_ATTEN_L + i; 204 idx = WM_ADC_ATTEN_L + i;
191 ovol = wm_get(ice, idx) & 0xff 205 ovol = wm_get(ice, idx) & 0xff;
192 if (ovol != nvol) { 206 if (ovol != nvol) {
193 wm_put(ice, idx, nvol) 207 wm_put(ice, idx, nvol);
194 change = 1; 208 change = 1;
195 } 209 }
196 } 210 }
197 mutex_unlock(&ice->gpio_mutex); 211 mutex_unlock(&ice->gpio_mutex);
198 return change; 212 return change;
199 } 213 }
200 214
201 /* 215 /*
202 * ADC input mux mixer control 216 * ADC input mux mixer control
203 */ 217 */
204 #define wm_adc_mux_info snd_ctl_boolea 218 #define wm_adc_mux_info snd_ctl_boolean_mono_info
205 219
206 static int wm_adc_mux_get(struct snd_kcontrol 220 static int wm_adc_mux_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
207 { 221 {
208 struct snd_ice1712 *ice = snd_kcontrol 222 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
209 int bit = kcontrol->private_value; 223 int bit = kcontrol->private_value;
210 224
211 mutex_lock(&ice->gpio_mutex); 225 mutex_lock(&ice->gpio_mutex);
212 ucontrol->value.integer.value[0] = (wm 226 ucontrol->value.integer.value[0] = (wm_get(ice, WM_ADC_MUX) & (1 << bit)) ? 1 : 0;
213 mutex_unlock(&ice->gpio_mutex); 227 mutex_unlock(&ice->gpio_mutex);
214 return 0; 228 return 0;
215 } 229 }
216 230
217 static int wm_adc_mux_put(struct snd_kcontrol 231 static int wm_adc_mux_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
218 { 232 {
219 struct snd_ice1712 *ice = snd_kcontrol 233 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
220 int bit = kcontrol->private_value; 234 int bit = kcontrol->private_value;
221 unsigned short oval, nval; 235 unsigned short oval, nval;
222 int change; 236 int change;
223 237
224 mutex_lock(&ice->gpio_mutex); 238 mutex_lock(&ice->gpio_mutex);
225 nval = oval = wm_get(ice, WM_ADC_MUX); 239 nval = oval = wm_get(ice, WM_ADC_MUX);
226 if (ucontrol->value.integer.value[0]) 240 if (ucontrol->value.integer.value[0])
227 nval |= (1 << bit); 241 nval |= (1 << bit);
228 else 242 else
229 nval &= ~(1 << bit); 243 nval &= ~(1 << bit);
230 change = nval != oval; 244 change = nval != oval;
231 if (change) { 245 if (change) {
232 wm_put(ice, WM_ADC_MUX, nval); 246 wm_put(ice, WM_ADC_MUX, nval);
233 } 247 }
234 mutex_unlock(&ice->gpio_mutex); 248 mutex_unlock(&ice->gpio_mutex);
235 return change; 249 return change;
236 } 250 }
237 251
238 /* 252 /*
239 * Analog bypass (In -> Out) 253 * Analog bypass (In -> Out)
240 */ 254 */
241 #define wm_bypass_info snd_ctl_boolea 255 #define wm_bypass_info snd_ctl_boolean_mono_info
242 256
243 static int wm_bypass_get(struct snd_kcontrol * 257 static int wm_bypass_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
244 { 258 {
245 struct snd_ice1712 *ice = snd_kcontrol 259 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
246 260
247 mutex_lock(&ice->gpio_mutex); 261 mutex_lock(&ice->gpio_mutex);
248 ucontrol->value.integer.value[0] = (wm 262 ucontrol->value.integer.value[0] = (wm_get(ice, WM_OUT_MUX) & 0x04) ? 1 : 0;
249 mutex_unlock(&ice->gpio_mutex); 263 mutex_unlock(&ice->gpio_mutex);
250 return 0; 264 return 0;
251 } 265 }
252 266
253 static int wm_bypass_put(struct snd_kcontrol * 267 static int wm_bypass_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
254 { 268 {
255 struct snd_ice1712 *ice = snd_kcontrol 269 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
256 unsigned short val, oval; 270 unsigned short val, oval;
257 int change = 0; 271 int change = 0;
258 272
259 mutex_lock(&ice->gpio_mutex); 273 mutex_lock(&ice->gpio_mutex);
260 val = oval = wm_get(ice, WM_OUT_MUX); 274 val = oval = wm_get(ice, WM_OUT_MUX);
261 if (ucontrol->value.integer.value[0]) 275 if (ucontrol->value.integer.value[0])
262 val |= 0x04; 276 val |= 0x04;
263 else 277 else
264 val &= ~0x04; 278 val &= ~0x04;
265 if (val != oval) { 279 if (val != oval) {
266 wm_put(ice, WM_OUT_MUX, val); 280 wm_put(ice, WM_OUT_MUX, val);
267 change = 1; 281 change = 1;
268 } 282 }
269 mutex_unlock(&ice->gpio_mutex); 283 mutex_unlock(&ice->gpio_mutex);
270 return change; 284 return change;
271 } 285 }
272 286
273 /* 287 /*
274 * Left/Right swap 288 * Left/Right swap
275 */ 289 */
276 #define wm_chswap_info snd_ctl_boolea 290 #define wm_chswap_info snd_ctl_boolean_mono_info
277 291
278 static int wm_chswap_get(struct snd_kcontrol * 292 static int wm_chswap_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
279 { 293 {
280 struct snd_ice1712 *ice = snd_kcontrol 294 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
281 295
282 mutex_lock(&ice->gpio_mutex); 296 mutex_lock(&ice->gpio_mutex);
283 ucontrol->value.integer.value[0] = (wm 297 ucontrol->value.integer.value[0] = (wm_get(ice, WM_DAC_CTRL1) & 0xf0) != 0x90;
284 mutex_unlock(&ice->gpio_mutex); 298 mutex_unlock(&ice->gpio_mutex);
285 return 0; 299 return 0;
286 } 300 }
287 301
288 static int wm_chswap_put(struct snd_kcontrol * 302 static int wm_chswap_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
289 { 303 {
290 struct snd_ice1712 *ice = snd_kcontrol 304 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
291 unsigned short val, oval; 305 unsigned short val, oval;
292 int change = 0; 306 int change = 0;
293 307
294 mutex_lock(&ice->gpio_mutex); 308 mutex_lock(&ice->gpio_mutex);
295 oval = wm_get(ice, WM_DAC_CTRL1); 309 oval = wm_get(ice, WM_DAC_CTRL1);
296 val = oval & 0x0f; 310 val = oval & 0x0f;
297 if (ucontrol->value.integer.value[0]) 311 if (ucontrol->value.integer.value[0])
298 val |= 0x60; 312 val |= 0x60;
299 else 313 else
300 val |= 0x90; 314 val |= 0x90;
301 if (val != oval) { 315 if (val != oval) {
302 wm_put(ice, WM_DAC_CTRL1, val) 316 wm_put(ice, WM_DAC_CTRL1, val);
303 wm_put_nocache(ice, WM_DAC_CTR 317 wm_put_nocache(ice, WM_DAC_CTRL1, val);
304 change = 1; 318 change = 1;
305 } 319 }
306 mutex_unlock(&ice->gpio_mutex); 320 mutex_unlock(&ice->gpio_mutex);
307 return change; 321 return change;
308 } 322 }
309 323
310 /* 324 /*
311 * write data in the SPI mode 325 * write data in the SPI mode
312 */ 326 */
313 static void set_gpio_bit(struct snd_ice1712 *i 327 static void set_gpio_bit(struct snd_ice1712 *ice, unsigned int bit, int val)
314 { 328 {
315 unsigned int tmp = snd_ice1712_gpio_re 329 unsigned int tmp = snd_ice1712_gpio_read(ice);
316 if (val) 330 if (val)
317 tmp |= bit; 331 tmp |= bit;
318 else 332 else
319 tmp &= ~bit; 333 tmp &= ~bit;
320 snd_ice1712_gpio_write(ice, tmp); 334 snd_ice1712_gpio_write(ice, tmp);
321 } 335 }
322 336
323 static void spi_send_byte(struct snd_ice1712 * 337 static void spi_send_byte(struct snd_ice1712 *ice, unsigned char data)
324 { 338 {
325 int i; 339 int i;
326 for (i = 0; i < 8; i++) { 340 for (i = 0; i < 8; i++) {
327 set_gpio_bit(ice, PONTIS_CS_CL 341 set_gpio_bit(ice, PONTIS_CS_CLK, 0);
328 udelay(1); 342 udelay(1);
329 set_gpio_bit(ice, PONTIS_CS_WD 343 set_gpio_bit(ice, PONTIS_CS_WDATA, data & 0x80);
330 udelay(1); 344 udelay(1);
331 set_gpio_bit(ice, PONTIS_CS_CL 345 set_gpio_bit(ice, PONTIS_CS_CLK, 1);
332 udelay(1); 346 udelay(1);
333 data <<= 1; 347 data <<= 1;
334 } 348 }
335 } 349 }
336 350
337 static unsigned int spi_read_byte(struct snd_i 351 static unsigned int spi_read_byte(struct snd_ice1712 *ice)
338 { 352 {
339 int i; 353 int i;
340 unsigned int val = 0; 354 unsigned int val = 0;
341 355
342 for (i = 0; i < 8; i++) { 356 for (i = 0; i < 8; i++) {
343 val <<= 1; 357 val <<= 1;
344 set_gpio_bit(ice, PONTIS_CS_CL 358 set_gpio_bit(ice, PONTIS_CS_CLK, 0);
345 udelay(1); 359 udelay(1);
346 if (snd_ice1712_gpio_read(ice) 360 if (snd_ice1712_gpio_read(ice) & PONTIS_CS_RDATA)
347 val |= 1; 361 val |= 1;
348 udelay(1); 362 udelay(1);
349 set_gpio_bit(ice, PONTIS_CS_CL 363 set_gpio_bit(ice, PONTIS_CS_CLK, 1);
350 udelay(1); 364 udelay(1);
351 } 365 }
352 return val; 366 return val;
353 } 367 }
354 368
355 369
356 static void spi_write(struct snd_ice1712 *ice, 370 static void spi_write(struct snd_ice1712 *ice, unsigned int dev, unsigned int reg, unsigned int data)
357 { 371 {
358 snd_ice1712_gpio_set_dir(ice, PONTIS_C 372 snd_ice1712_gpio_set_dir(ice, PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK);
359 snd_ice1712_gpio_set_mask(ice, ~(PONTI 373 snd_ice1712_gpio_set_mask(ice, ~(PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK));
360 set_gpio_bit(ice, PONTIS_CS_CS, 0); 374 set_gpio_bit(ice, PONTIS_CS_CS, 0);
361 spi_send_byte(ice, dev & ~1); /* WRITE 375 spi_send_byte(ice, dev & ~1); /* WRITE */
362 spi_send_byte(ice, reg); /* MAP */ 376 spi_send_byte(ice, reg); /* MAP */
363 spi_send_byte(ice, data); /* DATA */ 377 spi_send_byte(ice, data); /* DATA */
364 /* trigger */ 378 /* trigger */
365 set_gpio_bit(ice, PONTIS_CS_CS, 1); 379 set_gpio_bit(ice, PONTIS_CS_CS, 1);
366 udelay(1); 380 udelay(1);
367 /* restore */ 381 /* restore */
368 snd_ice1712_gpio_set_mask(ice, ice->gp 382 snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
369 snd_ice1712_gpio_set_dir(ice, ice->gpi 383 snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
370 } 384 }
371 385
372 static unsigned int spi_read(struct snd_ice171 386 static unsigned int spi_read(struct snd_ice1712 *ice, unsigned int dev, unsigned int reg)
373 { 387 {
374 unsigned int val; 388 unsigned int val;
375 snd_ice1712_gpio_set_dir(ice, PONTIS_C 389 snd_ice1712_gpio_set_dir(ice, PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK);
376 snd_ice1712_gpio_set_mask(ice, ~(PONTI 390 snd_ice1712_gpio_set_mask(ice, ~(PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK));
377 set_gpio_bit(ice, PONTIS_CS_CS, 0); 391 set_gpio_bit(ice, PONTIS_CS_CS, 0);
378 spi_send_byte(ice, dev & ~1); /* WRITE 392 spi_send_byte(ice, dev & ~1); /* WRITE */
379 spi_send_byte(ice, reg); /* MAP */ 393 spi_send_byte(ice, reg); /* MAP */
380 /* trigger */ 394 /* trigger */
381 set_gpio_bit(ice, PONTIS_CS_CS, 1); 395 set_gpio_bit(ice, PONTIS_CS_CS, 1);
382 udelay(1); 396 udelay(1);
383 set_gpio_bit(ice, PONTIS_CS_CS, 0); 397 set_gpio_bit(ice, PONTIS_CS_CS, 0);
384 spi_send_byte(ice, dev | 1); /* READ * 398 spi_send_byte(ice, dev | 1); /* READ */
385 val = spi_read_byte(ice); 399 val = spi_read_byte(ice);
386 /* trigger */ 400 /* trigger */
387 set_gpio_bit(ice, PONTIS_CS_CS, 1); 401 set_gpio_bit(ice, PONTIS_CS_CS, 1);
388 udelay(1); 402 udelay(1);
389 /* restore */ 403 /* restore */
390 snd_ice1712_gpio_set_mask(ice, ice->gp 404 snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
391 snd_ice1712_gpio_set_dir(ice, ice->gpi 405 snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
392 return val; 406 return val;
393 } 407 }
394 408
395 409
396 /* 410 /*
397 * SPDIF input source 411 * SPDIF input source
398 */ 412 */
399 static int cs_source_info(struct snd_kcontrol 413 static int cs_source_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
400 { 414 {
401 static const char * const texts[] = { 415 static const char * const texts[] = {
402 "Coax", /* RXP0 */ 416 "Coax", /* RXP0 */
403 "Optical", /* RXP1 */ 417 "Optical", /* RXP1 */
404 "CD", /* RXP2 */ 418 "CD", /* RXP2 */
405 }; 419 };
406 return snd_ctl_enum_info(uinfo, 1, 3, 420 return snd_ctl_enum_info(uinfo, 1, 3, texts);
407 } 421 }
408 422
409 static int cs_source_get(struct snd_kcontrol * 423 static int cs_source_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
410 { 424 {
411 struct snd_ice1712 *ice = snd_kcontrol 425 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
412 426
413 mutex_lock(&ice->gpio_mutex); 427 mutex_lock(&ice->gpio_mutex);
414 ucontrol->value.enumerated.item[0] = i 428 ucontrol->value.enumerated.item[0] = ice->gpio.saved[0];
415 mutex_unlock(&ice->gpio_mutex); 429 mutex_unlock(&ice->gpio_mutex);
416 return 0; 430 return 0;
417 } 431 }
418 432
419 static int cs_source_put(struct snd_kcontrol * 433 static int cs_source_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
420 { 434 {
421 struct snd_ice1712 *ice = snd_kcontrol 435 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
422 unsigned char val; 436 unsigned char val;
423 int change = 0; 437 int change = 0;
424 438
425 mutex_lock(&ice->gpio_mutex); 439 mutex_lock(&ice->gpio_mutex);
426 if (ucontrol->value.enumerated.item[0] 440 if (ucontrol->value.enumerated.item[0] != ice->gpio.saved[0]) {
427 ice->gpio.saved[0] = ucontrol- 441 ice->gpio.saved[0] = ucontrol->value.enumerated.item[0] & 3;
428 val = 0x80 | (ice->gpio.saved[ 442 val = 0x80 | (ice->gpio.saved[0] << 3);
429 spi_write(ice, CS_DEV, 0x04, v 443 spi_write(ice, CS_DEV, 0x04, val);
430 change = 1; 444 change = 1;
431 } 445 }
432 mutex_unlock(&ice->gpio_mutex); 446 mutex_unlock(&ice->gpio_mutex);
433 return change; 447 return change;
434 } 448 }
435 449
436 450
437 /* 451 /*
438 * GPIO controls 452 * GPIO controls
439 */ 453 */
440 static int pontis_gpio_mask_info(struct snd_kc 454 static int pontis_gpio_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
441 { 455 {
442 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTE 456 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
443 uinfo->count = 1; 457 uinfo->count = 1;
444 uinfo->value.integer.min = 0; 458 uinfo->value.integer.min = 0;
445 uinfo->value.integer.max = 0xffff; /* 459 uinfo->value.integer.max = 0xffff; /* 16bit */
446 return 0; 460 return 0;
447 } 461 }
448 462
449 static int pontis_gpio_mask_get(struct snd_kco 463 static int pontis_gpio_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
450 { 464 {
451 struct snd_ice1712 *ice = snd_kcontrol 465 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
452 mutex_lock(&ice->gpio_mutex); 466 mutex_lock(&ice->gpio_mutex);
453 /* 4-7 reserved */ 467 /* 4-7 reserved */
454 ucontrol->value.integer.value[0] = (~i 468 ucontrol->value.integer.value[0] = (~ice->gpio.write_mask & 0xffff) | 0x00f0;
455 mutex_unlock(&ice->gpio_mutex); 469 mutex_unlock(&ice->gpio_mutex);
456 return 0; 470 return 0;
457 } 471 }
458 472
459 static int pontis_gpio_mask_put(struct snd_kco 473 static int pontis_gpio_mask_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
460 { 474 {
461 struct snd_ice1712 *ice = snd_kcontrol 475 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
462 unsigned int val; 476 unsigned int val;
463 int changed; 477 int changed;
464 mutex_lock(&ice->gpio_mutex); 478 mutex_lock(&ice->gpio_mutex);
465 /* 4-7 reserved */ 479 /* 4-7 reserved */
466 val = (~ucontrol->value.integer.value[ 480 val = (~ucontrol->value.integer.value[0] & 0xffff) | 0x00f0;
467 changed = val != ice->gpio.write_mask; 481 changed = val != ice->gpio.write_mask;
468 ice->gpio.write_mask = val; 482 ice->gpio.write_mask = val;
469 mutex_unlock(&ice->gpio_mutex); 483 mutex_unlock(&ice->gpio_mutex);
470 return changed; 484 return changed;
471 } 485 }
472 486
473 static int pontis_gpio_dir_get(struct snd_kcon 487 static int pontis_gpio_dir_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
474 { 488 {
475 struct snd_ice1712 *ice = snd_kcontrol 489 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
476 mutex_lock(&ice->gpio_mutex); 490 mutex_lock(&ice->gpio_mutex);
477 /* 4-7 reserved */ 491 /* 4-7 reserved */
478 ucontrol->value.integer.value[0] = ice 492 ucontrol->value.integer.value[0] = ice->gpio.direction & 0xff0f;
479 mutex_unlock(&ice->gpio_mutex); 493 mutex_unlock(&ice->gpio_mutex);
480 return 0; 494 return 0;
481 } 495 }
482 496
483 static int pontis_gpio_dir_put(struct snd_kcon 497 static int pontis_gpio_dir_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
484 { 498 {
485 struct snd_ice1712 *ice = snd_kcontrol 499 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
486 unsigned int val; 500 unsigned int val;
487 int changed; 501 int changed;
488 mutex_lock(&ice->gpio_mutex); 502 mutex_lock(&ice->gpio_mutex);
489 /* 4-7 reserved */ 503 /* 4-7 reserved */
490 val = ucontrol->value.integer.value[0] 504 val = ucontrol->value.integer.value[0] & 0xff0f;
491 changed = (val != ice->gpio.direction) 505 changed = (val != ice->gpio.direction);
492 ice->gpio.direction = val; 506 ice->gpio.direction = val;
493 mutex_unlock(&ice->gpio_mutex); 507 mutex_unlock(&ice->gpio_mutex);
494 return changed; 508 return changed;
495 } 509 }
496 510
497 static int pontis_gpio_data_get(struct snd_kco 511 static int pontis_gpio_data_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
498 { 512 {
499 struct snd_ice1712 *ice = snd_kcontrol 513 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
500 mutex_lock(&ice->gpio_mutex); 514 mutex_lock(&ice->gpio_mutex);
501 snd_ice1712_gpio_set_dir(ice, ice->gpi 515 snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
502 snd_ice1712_gpio_set_mask(ice, ice->gp 516 snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
503 ucontrol->value.integer.value[0] = snd 517 ucontrol->value.integer.value[0] = snd_ice1712_gpio_read(ice) & 0xffff;
504 mutex_unlock(&ice->gpio_mutex); 518 mutex_unlock(&ice->gpio_mutex);
505 return 0; 519 return 0;
506 } 520 }
507 521
508 static int pontis_gpio_data_put(struct snd_kco 522 static int pontis_gpio_data_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
509 { 523 {
510 struct snd_ice1712 *ice = snd_kcontrol 524 struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
511 unsigned int val, nval; 525 unsigned int val, nval;
512 int changed = 0; 526 int changed = 0;
513 mutex_lock(&ice->gpio_mutex); 527 mutex_lock(&ice->gpio_mutex);
514 snd_ice1712_gpio_set_dir(ice, ice->gpi 528 snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
515 snd_ice1712_gpio_set_mask(ice, ice->gp 529 snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
516 val = snd_ice1712_gpio_read(ice) & 0xf 530 val = snd_ice1712_gpio_read(ice) & 0xffff;
517 nval = ucontrol->value.integer.value[0 531 nval = ucontrol->value.integer.value[0] & 0xffff;
518 if (val != nval) { 532 if (val != nval) {
519 snd_ice1712_gpio_write(ice, nv 533 snd_ice1712_gpio_write(ice, nval);
520 changed = 1; 534 changed = 1;
521 } 535 }
522 mutex_unlock(&ice->gpio_mutex); 536 mutex_unlock(&ice->gpio_mutex);
523 return changed; 537 return changed;
524 } 538 }
525 539
526 static const DECLARE_TLV_DB_SCALE(db_scale_vol 540 static const DECLARE_TLV_DB_SCALE(db_scale_volume, -6400, 50, 1);
527 541
528 /* 542 /*
529 * mixers 543 * mixers
530 */ 544 */
531 545
532 static const struct snd_kcontrol_new pontis_co !! 546 static struct snd_kcontrol_new pontis_controls[] = {
533 { 547 {
534 .iface = SNDRV_CTL_ELEM_IFACE_ 548 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
535 .access = (SNDRV_CTL_ELEM_ACCE 549 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
536 SNDRV_CTL_ELEM_ACCE 550 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
537 .name = "PCM Playback Volume", 551 .name = "PCM Playback Volume",
538 .info = wm_dac_vol_info, 552 .info = wm_dac_vol_info,
539 .get = wm_dac_vol_get, 553 .get = wm_dac_vol_get,
540 .put = wm_dac_vol_put, 554 .put = wm_dac_vol_put,
541 .tlv = { .p = db_scale_volume 555 .tlv = { .p = db_scale_volume },
542 }, 556 },
543 { 557 {
544 .iface = SNDRV_CTL_ELEM_IFACE_ 558 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
545 .access = (SNDRV_CTL_ELEM_ACCE 559 .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
546 SNDRV_CTL_ELEM_ACCE 560 SNDRV_CTL_ELEM_ACCESS_TLV_READ),
547 .name = "Capture Volume", 561 .name = "Capture Volume",
548 .info = wm_adc_vol_info, 562 .info = wm_adc_vol_info,
549 .get = wm_adc_vol_get, 563 .get = wm_adc_vol_get,
550 .put = wm_adc_vol_put, 564 .put = wm_adc_vol_put,
551 .tlv = { .p = db_scale_volume 565 .tlv = { .p = db_scale_volume },
552 }, 566 },
553 { 567 {
554 .iface = SNDRV_CTL_ELEM_IFACE_ 568 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
555 .name = "CD Capture Switch", 569 .name = "CD Capture Switch",
556 .info = wm_adc_mux_info, 570 .info = wm_adc_mux_info,
557 .get = wm_adc_mux_get, 571 .get = wm_adc_mux_get,
558 .put = wm_adc_mux_put, 572 .put = wm_adc_mux_put,
559 .private_value = 0, 573 .private_value = 0,
560 }, 574 },
561 { 575 {
562 .iface = SNDRV_CTL_ELEM_IFACE_ 576 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
563 .name = "Line Capture Switch", 577 .name = "Line Capture Switch",
564 .info = wm_adc_mux_info, 578 .info = wm_adc_mux_info,
565 .get = wm_adc_mux_get, 579 .get = wm_adc_mux_get,
566 .put = wm_adc_mux_put, 580 .put = wm_adc_mux_put,
567 .private_value = 1, 581 .private_value = 1,
568 }, 582 },
569 { 583 {
570 .iface = SNDRV_CTL_ELEM_IFACE_ 584 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
571 .name = "Analog Bypass Switch" 585 .name = "Analog Bypass Switch",
572 .info = wm_bypass_info, 586 .info = wm_bypass_info,
573 .get = wm_bypass_get, 587 .get = wm_bypass_get,
574 .put = wm_bypass_put, 588 .put = wm_bypass_put,
575 }, 589 },
576 { 590 {
577 .iface = SNDRV_CTL_ELEM_IFACE_ 591 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
578 .name = "Swap Output Channels" 592 .name = "Swap Output Channels",
579 .info = wm_chswap_info, 593 .info = wm_chswap_info,
580 .get = wm_chswap_get, 594 .get = wm_chswap_get,
581 .put = wm_chswap_put, 595 .put = wm_chswap_put,
582 }, 596 },
583 { 597 {
584 .iface = SNDRV_CTL_ELEM_IFACE_ 598 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
585 .name = "IEC958 Input Source", 599 .name = "IEC958 Input Source",
586 .info = cs_source_info, 600 .info = cs_source_info,
587 .get = cs_source_get, 601 .get = cs_source_get,
588 .put = cs_source_put, 602 .put = cs_source_put,
589 }, 603 },
590 /* FIXME: which interface? */ 604 /* FIXME: which interface? */
591 { 605 {
592 .iface = SNDRV_CTL_ELEM_IFACE_ 606 .iface = SNDRV_CTL_ELEM_IFACE_CARD,
593 .name = "GPIO Mask", 607 .name = "GPIO Mask",
594 .info = pontis_gpio_mask_info, 608 .info = pontis_gpio_mask_info,
595 .get = pontis_gpio_mask_get, 609 .get = pontis_gpio_mask_get,
596 .put = pontis_gpio_mask_put, 610 .put = pontis_gpio_mask_put,
597 }, 611 },
598 { 612 {
599 .iface = SNDRV_CTL_ELEM_IFACE_ 613 .iface = SNDRV_CTL_ELEM_IFACE_CARD,
600 .name = "GPIO Direction", 614 .name = "GPIO Direction",
601 .info = pontis_gpio_mask_info, 615 .info = pontis_gpio_mask_info,
602 .get = pontis_gpio_dir_get, 616 .get = pontis_gpio_dir_get,
603 .put = pontis_gpio_dir_put, 617 .put = pontis_gpio_dir_put,
604 }, 618 },
605 { 619 {
606 .iface = SNDRV_CTL_ELEM_IFACE_ 620 .iface = SNDRV_CTL_ELEM_IFACE_CARD,
607 .name = "GPIO Data", 621 .name = "GPIO Data",
608 .info = pontis_gpio_mask_info, 622 .info = pontis_gpio_mask_info,
609 .get = pontis_gpio_data_get, 623 .get = pontis_gpio_data_get,
610 .put = pontis_gpio_data_put, 624 .put = pontis_gpio_data_put,
611 }, 625 },
612 }; 626 };
613 627
614 628
615 /* 629 /*
616 * WM codec registers 630 * WM codec registers
617 */ 631 */
618 static void wm_proc_regs_write(struct snd_info 632 static void wm_proc_regs_write(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
619 { 633 {
620 struct snd_ice1712 *ice = entry->priva 634 struct snd_ice1712 *ice = entry->private_data;
621 char line[64]; 635 char line[64];
622 unsigned int reg, val; 636 unsigned int reg, val;
623 mutex_lock(&ice->gpio_mutex); 637 mutex_lock(&ice->gpio_mutex);
624 while (!snd_info_get_line(buffer, line 638 while (!snd_info_get_line(buffer, line, sizeof(line))) {
625 if (sscanf(line, "%x %x", ® 639 if (sscanf(line, "%x %x", ®, &val) != 2)
626 continue; 640 continue;
627 if (reg <= 0x17 && val <= 0xff 641 if (reg <= 0x17 && val <= 0xffff)
628 wm_put(ice, reg, val); 642 wm_put(ice, reg, val);
629 } 643 }
630 mutex_unlock(&ice->gpio_mutex); 644 mutex_unlock(&ice->gpio_mutex);
631 } 645 }
632 646
633 static void wm_proc_regs_read(struct snd_info_ 647 static void wm_proc_regs_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
634 { 648 {
635 struct snd_ice1712 *ice = entry->priva 649 struct snd_ice1712 *ice = entry->private_data;
636 int reg, val; 650 int reg, val;
637 651
638 mutex_lock(&ice->gpio_mutex); 652 mutex_lock(&ice->gpio_mutex);
639 for (reg = 0; reg <= 0x17; reg++) { 653 for (reg = 0; reg <= 0x17; reg++) {
640 val = wm_get(ice, reg); 654 val = wm_get(ice, reg);
641 snd_iprintf(buffer, "%02x = %0 655 snd_iprintf(buffer, "%02x = %04x\n", reg, val);
642 } 656 }
643 mutex_unlock(&ice->gpio_mutex); 657 mutex_unlock(&ice->gpio_mutex);
644 } 658 }
645 659
646 static void wm_proc_init(struct snd_ice1712 *i 660 static void wm_proc_init(struct snd_ice1712 *ice)
647 { 661 {
648 snd_card_rw_proc_new(ice->card, "wm_co 662 snd_card_rw_proc_new(ice->card, "wm_codec", ice, wm_proc_regs_read,
649 wm_proc_regs_writ 663 wm_proc_regs_write);
650 } 664 }
651 665
652 static void cs_proc_regs_read(struct snd_info_ 666 static void cs_proc_regs_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
653 { 667 {
654 struct snd_ice1712 *ice = entry->priva 668 struct snd_ice1712 *ice = entry->private_data;
655 int reg, val; 669 int reg, val;
656 670
657 mutex_lock(&ice->gpio_mutex); 671 mutex_lock(&ice->gpio_mutex);
658 for (reg = 0; reg <= 0x26; reg++) { 672 for (reg = 0; reg <= 0x26; reg++) {
659 val = spi_read(ice, CS_DEV, re 673 val = spi_read(ice, CS_DEV, reg);
660 snd_iprintf(buffer, "%02x = %0 674 snd_iprintf(buffer, "%02x = %02x\n", reg, val);
661 } 675 }
662 val = spi_read(ice, CS_DEV, 0x7f); 676 val = spi_read(ice, CS_DEV, 0x7f);
663 snd_iprintf(buffer, "%02x = %02x\n", 0 677 snd_iprintf(buffer, "%02x = %02x\n", 0x7f, val);
664 mutex_unlock(&ice->gpio_mutex); 678 mutex_unlock(&ice->gpio_mutex);
665 } 679 }
666 680
667 static void cs_proc_init(struct snd_ice1712 *i 681 static void cs_proc_init(struct snd_ice1712 *ice)
668 { 682 {
669 snd_card_ro_proc_new(ice->card, "cs_co 683 snd_card_ro_proc_new(ice->card, "cs_codec", ice, cs_proc_regs_read);
670 } 684 }
671 685
672 686
673 static int pontis_add_controls(struct snd_ice1 687 static int pontis_add_controls(struct snd_ice1712 *ice)
674 { 688 {
675 unsigned int i; 689 unsigned int i;
676 int err; 690 int err;
677 691
678 for (i = 0; i < ARRAY_SIZE(pontis_cont 692 for (i = 0; i < ARRAY_SIZE(pontis_controls); i++) {
679 err = snd_ctl_add(ice->card, s 693 err = snd_ctl_add(ice->card, snd_ctl_new1(&pontis_controls[i], ice));
680 if (err < 0) 694 if (err < 0)
681 return err; 695 return err;
682 } 696 }
683 697
684 wm_proc_init(ice); 698 wm_proc_init(ice);
685 cs_proc_init(ice); 699 cs_proc_init(ice);
686 700
687 return 0; 701 return 0;
688 } 702 }
689 703
690 704
691 /* 705 /*
692 * initialize the chip 706 * initialize the chip
693 */ 707 */
694 static int pontis_init(struct snd_ice1712 *ice 708 static int pontis_init(struct snd_ice1712 *ice)
695 { 709 {
696 static const unsigned short wm_inits[] 710 static const unsigned short wm_inits[] = {
697 /* These come first to reduce 711 /* These come first to reduce init pop noise */
698 WM_ADC_MUX, 0x00c0, /* ADC 712 WM_ADC_MUX, 0x00c0, /* ADC mute */
699 WM_DAC_MUTE, 0x0001, /* DAC 713 WM_DAC_MUTE, 0x0001, /* DAC softmute */
700 WM_DAC_CTRL1, 0x0000, /* DAC 714 WM_DAC_CTRL1, 0x0000, /* DAC mute */
701 715
702 WM_POWERDOWN, 0x0008, /* All 716 WM_POWERDOWN, 0x0008, /* All power-up except HP */
703 WM_RESET, 0x0000, /* res 717 WM_RESET, 0x0000, /* reset */
704 }; 718 };
705 static const unsigned short wm_inits2[ 719 static const unsigned short wm_inits2[] = {
706 WM_MASTER_CTRL, 0x0022, /* 256 720 WM_MASTER_CTRL, 0x0022, /* 256fs, slave mode */
707 WM_DAC_INT, 0x0022, /* I2S 721 WM_DAC_INT, 0x0022, /* I2S, normal polarity, 24bit */
708 WM_ADC_INT, 0x0022, /* I2S 722 WM_ADC_INT, 0x0022, /* I2S, normal polarity, 24bit */
709 WM_DAC_CTRL1, 0x0090, /* DAC 723 WM_DAC_CTRL1, 0x0090, /* DAC L/R */
710 WM_OUT_MUX, 0x0001, /* OUT 724 WM_OUT_MUX, 0x0001, /* OUT DAC */
711 WM_HP_ATTEN_L, 0x0179, /* HP 725 WM_HP_ATTEN_L, 0x0179, /* HP 0dB */
712 WM_HP_ATTEN_R, 0x0179, /* HP 726 WM_HP_ATTEN_R, 0x0179, /* HP 0dB */
713 WM_DAC_ATTEN_L, 0x0000, /* DAC 727 WM_DAC_ATTEN_L, 0x0000, /* DAC 0dB */
714 WM_DAC_ATTEN_L, 0x0100, /* DAC 728 WM_DAC_ATTEN_L, 0x0100, /* DAC 0dB */
715 WM_DAC_ATTEN_R, 0x0000, /* DAC 729 WM_DAC_ATTEN_R, 0x0000, /* DAC 0dB */
716 WM_DAC_ATTEN_R, 0x0100, /* DAC 730 WM_DAC_ATTEN_R, 0x0100, /* DAC 0dB */
717 /* WM_DAC_MASTER, 0x0100 731 /* WM_DAC_MASTER, 0x0100, */ /* DAC master muted */
718 WM_PHASE_SWAP, 0x0000, /* pha 732 WM_PHASE_SWAP, 0x0000, /* phase normal */
719 WM_DAC_CTRL2, 0x0000, /* no 733 WM_DAC_CTRL2, 0x0000, /* no deemphasis, no ZFLG */
720 WM_ADC_ATTEN_L, 0x0000, /* ADC 734 WM_ADC_ATTEN_L, 0x0000, /* ADC muted */
721 WM_ADC_ATTEN_R, 0x0000, /* ADC 735 WM_ADC_ATTEN_R, 0x0000, /* ADC muted */
722 #if 0 736 #if 0
723 WM_ALC_CTRL1, 0x007b, /* */ 737 WM_ALC_CTRL1, 0x007b, /* */
724 WM_ALC_CTRL2, 0x0000, /* */ 738 WM_ALC_CTRL2, 0x0000, /* */
725 WM_ALC_CTRL3, 0x0000, /* */ 739 WM_ALC_CTRL3, 0x0000, /* */
726 WM_NOISE_GATE, 0x0000, /* */ 740 WM_NOISE_GATE, 0x0000, /* */
727 #endif 741 #endif
728 WM_DAC_MUTE, 0x0000, /* DAC 742 WM_DAC_MUTE, 0x0000, /* DAC unmute */
729 WM_ADC_MUX, 0x0003, /* ADC 743 WM_ADC_MUX, 0x0003, /* ADC unmute, both CD/Line On */
730 }; 744 };
731 static const unsigned char cs_inits[] 745 static const unsigned char cs_inits[] = {
732 0x04, 0x80, /* RUN, RXP0 * 746 0x04, 0x80, /* RUN, RXP0 */
733 0x05, 0x05, /* slave, 24bi 747 0x05, 0x05, /* slave, 24bit */
734 0x01, 0x00, 748 0x01, 0x00,
735 0x02, 0x00, 749 0x02, 0x00,
736 0x03, 0x00, 750 0x03, 0x00,
737 }; 751 };
738 unsigned int i; 752 unsigned int i;
739 753
740 ice->vt1720 = 1; 754 ice->vt1720 = 1;
741 ice->num_total_dacs = 2; 755 ice->num_total_dacs = 2;
742 ice->num_total_adcs = 2; 756 ice->num_total_adcs = 2;
743 757
744 /* to remember the register values */ 758 /* to remember the register values */
745 ice->akm = kzalloc(sizeof(struct snd_a 759 ice->akm = kzalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
746 if (! ice->akm) 760 if (! ice->akm)
747 return -ENOMEM; 761 return -ENOMEM;
748 ice->akm_codecs = 1; 762 ice->akm_codecs = 1;
749 763
750 /* HACK - use this as the SPDIF source 764 /* HACK - use this as the SPDIF source.
751 * don't call snd_ice1712_gpio_get/put 765 * don't call snd_ice1712_gpio_get/put(), otherwise it's overwritten
752 */ 766 */
753 ice->gpio.saved[0] = 0; 767 ice->gpio.saved[0] = 0;
754 768
755 /* initialize WM8776 codec */ 769 /* initialize WM8776 codec */
756 for (i = 0; i < ARRAY_SIZE(wm_inits); 770 for (i = 0; i < ARRAY_SIZE(wm_inits); i += 2)
757 wm_put(ice, wm_inits[i], wm_in 771 wm_put(ice, wm_inits[i], wm_inits[i+1]);
758 schedule_timeout_uninterruptible(1); 772 schedule_timeout_uninterruptible(1);
759 for (i = 0; i < ARRAY_SIZE(wm_inits2); 773 for (i = 0; i < ARRAY_SIZE(wm_inits2); i += 2)
760 wm_put(ice, wm_inits2[i], wm_i 774 wm_put(ice, wm_inits2[i], wm_inits2[i+1]);
761 775
762 /* initialize CS8416 codec */ 776 /* initialize CS8416 codec */
763 /* assert PRST#; MT05 bit 7 */ 777 /* assert PRST#; MT05 bit 7 */
764 outb(inb(ICEMT1724(ice, AC97_CMD)) | 0 778 outb(inb(ICEMT1724(ice, AC97_CMD)) | 0x80, ICEMT1724(ice, AC97_CMD));
765 mdelay(5); 779 mdelay(5);
766 /* deassert PRST# */ 780 /* deassert PRST# */
767 outb(inb(ICEMT1724(ice, AC97_CMD)) & ~ 781 outb(inb(ICEMT1724(ice, AC97_CMD)) & ~0x80, ICEMT1724(ice, AC97_CMD));
768 782
769 for (i = 0; i < ARRAY_SIZE(cs_inits); 783 for (i = 0; i < ARRAY_SIZE(cs_inits); i += 2)
770 spi_write(ice, CS_DEV, cs_init 784 spi_write(ice, CS_DEV, cs_inits[i], cs_inits[i+1]);
771 785
772 return 0; 786 return 0;
773 } 787 }
774 788
775 789
776 /* 790 /*
777 * Pontis boards don't provide the EEPROM data 791 * Pontis boards don't provide the EEPROM data at all.
778 * hence the driver needs to sets up it proper 792 * hence the driver needs to sets up it properly.
779 */ 793 */
780 794
781 static const unsigned char pontis_eeprom[] = { !! 795 static unsigned char pontis_eeprom[] = {
782 [ICE_EEP2_SYSCONF] = 0x08, /* clo 796 [ICE_EEP2_SYSCONF] = 0x08, /* clock 256, mpu401, spdif-in/ADC, 1DAC */
783 [ICE_EEP2_ACLINK] = 0x80, /* I2S 797 [ICE_EEP2_ACLINK] = 0x80, /* I2S */
784 [ICE_EEP2_I2S] = 0xf8, /* vol 798 [ICE_EEP2_I2S] = 0xf8, /* vol, 96k, 24bit, 192k */
785 [ICE_EEP2_SPDIF] = 0xc3, /* out 799 [ICE_EEP2_SPDIF] = 0xc3, /* out-en, out-int, spdif-in */
786 [ICE_EEP2_GPIO_DIR] = 0x07, 800 [ICE_EEP2_GPIO_DIR] = 0x07,
787 [ICE_EEP2_GPIO_DIR1] = 0x00, 801 [ICE_EEP2_GPIO_DIR1] = 0x00,
788 [ICE_EEP2_GPIO_DIR2] = 0x00, /* ign 802 [ICE_EEP2_GPIO_DIR2] = 0x00, /* ignored */
789 [ICE_EEP2_GPIO_MASK] = 0x0f, /* 4-7 803 [ICE_EEP2_GPIO_MASK] = 0x0f, /* 4-7 reserved for CS8416 */
790 [ICE_EEP2_GPIO_MASK1] = 0xff, 804 [ICE_EEP2_GPIO_MASK1] = 0xff,
791 [ICE_EEP2_GPIO_MASK2] = 0x00, /* ign 805 [ICE_EEP2_GPIO_MASK2] = 0x00, /* ignored */
792 [ICE_EEP2_GPIO_STATE] = 0x06, /* 0-l 806 [ICE_EEP2_GPIO_STATE] = 0x06, /* 0-low, 1-high, 2-high */
793 [ICE_EEP2_GPIO_STATE1] = 0x00, 807 [ICE_EEP2_GPIO_STATE1] = 0x00,
794 [ICE_EEP2_GPIO_STATE2] = 0x00, /* ign 808 [ICE_EEP2_GPIO_STATE2] = 0x00, /* ignored */
795 }; 809 };
796 810
797 /* entry point */ 811 /* entry point */
798 struct snd_ice1712_card_info snd_vt1720_pontis 812 struct snd_ice1712_card_info snd_vt1720_pontis_cards[] = {
799 { 813 {
800 .subvendor = VT1720_SUBDEVICE_ 814 .subvendor = VT1720_SUBDEVICE_PONTIS_MS300,
801 .name = "Pontis MS300", 815 .name = "Pontis MS300",
802 .model = "ms300", 816 .model = "ms300",
803 .chip_init = pontis_init, 817 .chip_init = pontis_init,
804 .build_controls = pontis_add_c 818 .build_controls = pontis_add_controls,
805 .eeprom_size = sizeof(pontis_e 819 .eeprom_size = sizeof(pontis_eeprom),
806 .eeprom_data = pontis_eeprom, 820 .eeprom_data = pontis_eeprom,
807 }, 821 },
808 { } /* terminator */ 822 { } /* terminator */
809 }; 823 };
810 824
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